JPH11313071A - Atm switch buffer read controller and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To disperse the readout sequence of respective connection outputs in the read scheduling of a cell retained in a buffer on an ATM switch. SOLUTION: A counter circuit 1 counts up one by one by a cell read timing signal and the counter value is transmitted to an exchange circuit 5. The exchange circuit 5 inversely exchanges the arrangement of the bits of a counter value shown by a binary number. An output band judgement circuit 6 compares the output value K of the exchange circuit 5 with a value Z which a period setting holding circuit 2 holds. When K>Z, a skip signal is sent to a counter skip circuit 7. When the skip signal is inputted, the counter skip circuit 7 counts up a counter circuit 1 by one and an operation is repeated. A connection selection circuit retrieves a connection band setting holding circuit 3 with a value passing through the output band judgement circuit 6 as an address and outputs a connection number which is held.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer read control circuit provided in an ATM switch, and more particularly to a buffer read control circuit of an ATM switch for dispersing a read output for each connection.

[0002]

2. Description of the Related Art Conventionally, such a buffer read control circuit is generally used for selecting a read connection when reading cells staying for each connection in a buffer of an ATM switch.

FIG. 8 is a block diagram showing an example of a conventional ATM switch buffer read control circuit. This conventional example includes a counter circuit 1, a synchronization setting holding circuit 2, a connection band setting holding circuit 3, and a connection selection circuit 4.

The counter circuit 1 periodically counts up. The cycle setting holding circuit 2 holds the cycle of the counter. The connection band setting holding circuit 3 holds an occupied band value for each connection. The connection selection circuit 4 compares the output value of the counter circuit 1 with the value held by the connection band setting holding circuit 3 and selects a corresponding connection number.

Next, the operation will be described. When the output band of the ATM switch is X and the minimum setting band of each connection is Y, the cycle setting holding circuit 2 holds the value of X / Y-1 (hereinafter referred to as Z). First, when the set bandwidth of the connection number C1 is W1, C1 is set to addresses 0 to W1 / Y-1 of the connection band setting holding circuit 3, and then, when the set bandwidth of the connection number C2 is W2, Address W1 / Y to W of band setting holding circuit 3
Set C2 to 1 / Y + W2 / Y-1. Hereinafter, similarly, the set bandwidth of each connection is set in the connection bandwidth setting holding circuit 3. The counter circuit 1 counts up by +1 according to a cell read timing signal input every cell processing time from a control circuit inside the ATM switch, and returns to an initial value (= 0) when the output value becomes equal to Z. The connection selection circuit 4 searches for the corresponding connection number held in the connection band setting holding circuit 3 using the counter value output from the counter circuit 1 for each cell processing time as an address.

Thus, the counter circuit 1 operates for one cycle (0
ＺZ), each connection is output by the number of cells corresponding to the set band.

[0007]

However, in this technique, the operation of continuously outputting the number of cells of the set bandwidth for each connection in one cycle of the counter is performed. There is a problem in that the cells of the same connection arrive in a concentrated manner in the unit, and if these cells cannot be processed, they may cause instantaneous cell discard. Further, if the sum of the set bandwidths of all the connections is less than the output bandwidth of the switch, the unallocated portion of the bandwidth (the empty portion) is displayed in the latter half of one cycle of the counter when the output of the switch is viewed as a whole. (Cell output) is concentrated, so that the output becomes bursty. For this reason, there is also a problem that it is necessary to increase the circuit scale and the like more than necessary in consideration of the burst property in the input processing unit and the like in a device subsequent to this switch. A main object of the present invention is to provide an ATM switch buffer read control circuit in which a read operation for each connection is averaged in one cycle of a counter and cells of the same connection are output in a dispersed manner.

[0008]

In order to achieve the above object, an ATM switch buffer read control device according to the present invention comprises:
In response to a cell read timing signal input from outside,
A conversion signal generating means for outputting a conversion signal for specifying the connection number to be read out, and a connection selecting means for outputting a connection number for specifying the connection in accordance with the conversion signal.

Here, the conversion signal generating means counts the number of pulses included in the input clock signal, and outputs the counting signal. The converting means converts the counting signal according to a predetermined rule. A switching means for outputting a converted signal may be provided.

Further, the ATM switch buffer read control device compares the conversion signal with a predetermined band upper limit value, and outputs the result as a comparison signal. If the converted signal is larger than the band upper limit, the counter means may include a counter reading means for outputting a counter operation signal for instructing the counter means to perform an extra counting.

Further, the replacement means may be arranged so that each digit of the binary display value of the count signal is rearranged in the reverse order and output as a converted signal. A configuration may be adopted in which values sequentially read out according to the count value are output as conversion signals.

Alternatively, the replacement means receives a predetermined initial value as an initial value signal and sequentially adds a predetermined natural number of 2 or more to the initial value signal in accordance with an increase in the count signal. A first conversion means for outputting a natural number obtained as a first conversion signal, and comparing a natural number determined by the first conversion signal with a predetermined maximum number to obtain a first conversion signal. Is not large, the first converted signal is output as the converted signal. If the first converted signal is large, a value obtained by adding 1 to the initial value signal is used as the initial value signal as the first signal. A second input to the conversion means and output as the conversion signal
May be provided.

[0013] Also, the replacement means sequentially increases the conversion from the count signal to the conversion signal by a predetermined natural number by two or more natural numbers in accordance with an increase in the count signal. When the increased natural number obtained by the calculation is not larger than a predetermined natural number, the converted natural number is used as the conversion signal. When the increased natural number is larger than the predetermined natural number, a value obtained by adding 1 to the initial value is used. It may have the function of replacing the initial value with the converted signal.

The switching means may be a fixed wiring between input / output terminals, a matrix switch for selectively connecting input terminals and output terminals based on a control signal applied from the outside, And a memory element connected to an address input terminal for inputting a signal for designating an address, and outputting stored data as the conversion signal.

The switching means may be configured to change the predetermined rule based on information on cell discarding input from a device to which the output of the ATM switch is input. If a matrix switch is used, a configuration may be adopted in which a cell discard alarm for notifying the occurrence or an increase in the frequency of cell discard input from a device to which the output of the ATM switch is input is input as the control signal. Further, if the memory element is used, the cell input alarm and the counting signal, which notify the occurrence or increase of the frequency of cell input from the device to which the output of the ATM switch is input, are input to the address input terminal. May be adopted.

Furthermore, as another configuration, the ATM of the present invention
The switch buffer read control device includes a shift register unit having a predetermined number of stages, and an exclusive OR signal obtained by inputting outputs of at least one predetermined stage of the shift register unit and calculating an exclusive OR. And exclusive OR means for feeding back to the first stage of the shift register means, and connection selecting means for outputting a predetermined connection number in response to an output signal of a predetermined stage of the shift register means. . Also, the AT according to the present invention
The M-switch buffer read control method includes a counting step of counting the number of pulses included in a clock signal input from the outside, and a conversion step of converting a count value obtained in the counting step into a connection number according to a predetermined rule. Contains.

Here, the conversion step may include a reference step of determining the connection number with reference to a table defining the correspondence between the count value and the connection number, or The method may include a numerical value conversion step of converting the conversion value into a conversion value in accordance with a predetermined rule, and a reference step of determining the connection number with reference to a table defining the correspondence between the conversion value and the connection number.

Further, the converting step includes a numerical value converting step of converting the count value into a converted value in accordance with a predetermined rule, a comparing step of comparing the converted value with a predetermined value, As a result of the step, when it is found that the conversion value is larger, the feedback step for temporarily interrupting the counting step, and the connection number with reference to a table defining the correspondence between the conversion value and the connection number And a reference step of determining

Further, the numerical value conversion step may include a step of using a binary display value obtained by rearranging the respective digits in the case where the count value is displayed in a binary number in the reverse order as the conversion value, or The method may further include, as a conversion value, a value sequentially read from a predetermined position in one cycle of the pseudo random sequence in accordance with the count value.

Further, in the numerical value conversion step, the conversion from the counted value to the converted value is performed by setting a predetermined initial value to:
When the incremented natural number obtained by sequentially increasing according to the increase of the count signal is not larger than a predetermined natural number by two or more predetermined natural numbers, the increased natural number is set as the conversion value, and the increased natural number is When the value is larger than the predetermined natural number, the method may include a step of adding a value obtained by adding 1 to the initial value as the converted value and further replacing the converted value with the initial value.

Further, the ATM switch buffer read control method may further include an algorithm changing step of monitoring an operation state of an external device and changing the predetermined rule in the conversion step according to the result. .

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows the configuration of the first embodiment of the present invention. In FIG. 1, components with the same reference numerals as those in FIG. 8 indicate that they are the same as those in the conventional example. In this embodiment, an MSB-LSB replacement circuit 5, an output band determination circuit 6, and a counter reading skipping circuit 7 are newly added to the conventional example.

The present ATM switch buffer read control circuit includes an MSB-LSB exchange circuit 5 for exchanging the MSB and LSB of the output signal from the counter circuit 1 and a counter circuit when the value is larger than that of the cycle setting holding circuit 2. An output band determination circuit 6 for sending a skip signal for 1
And a counter skip circuit 7 for ORing the skip signal from the output band determination circuit 6 and the cell read timing signal to operate the counter circuit 1.

The operation of this embodiment will be described below. The cycle setting and holding circuit 2 and the connection band setting and holding circuit 3 are set and held in the same manner as in the conventional example.
The counter circuit 1 counts up by one every one cell processing time in response to the cell read timing signal, and sends the count value to the MSB-LSB switching circuit 5. MSB
As shown in FIG. 2, the -LSB replacement circuit 5 reversely switches the most significant bit (MSB) to the least significant bit (LSB) of the counter value represented by a binary number. The output band determination circuit 6 compares the value (hereinafter referred to as K) from the MSB-LSB switching circuit 5 with the value (Z) held in the cycle setting holding circuit 2, and skips the counter reading when K> Z. A skip signal is sent to the circuit 7. The counter skip circuit 7 sends a counter operation signal to the counter circuit 1 when either the skip signal or the cell read timing signal is input. Therefore, the counter further counts up by +1 and repeats the above operation. In connection selection circuit 4, output band determination circuit 6
The connection band setting and holding circuit 3 is searched in the same manner as in the prior art, using the value passed through as the address, and the corresponding connection number held is output. FIG. 3 shows a flowchart of the operation of this circuit.

An output value represented by a binary number of the counter circuit 1 is represented by the following equation (1).

A0 * (2 ＾ 0) + A1 * (2 ＾ 1) + A2 * (2 ＾ 2) +... + A (n-1) * (2 ＾ (n-1)) + An * (2 ＾ n) -(1) (A0, A1, A2,..., An are all 0 or 1) MSB-LSB in the MSB-LSB switching circuit 5
The exchanged value K can be expressed as in equation (2).

An * (2 ＾ 0) + A (n−1) * (2 ＾ 1) +... + A1 * (2 ＾ (n−1)) + A0 * (2 ＾ n) (2) , (1) increases by one, and (2) increases or decreases to take an intermediate value as shown in FIG. Therefore, the output connection numbers can be distributed by detecting the connection numbers from the connection band setting and holding circuit 3 based on this value.

FIG. 5 shows the holding value Z = 1 of the cycle setting holding circuit 2.
It is explanatory drawing which shows the specific example in case of 1. As shown in FIG. 5A, the connection band setting and holding circuit 3 stores 4/12 for the connection number 1, 2/12 for the connection number 2, and 4/1 for the connection number 3.
2, 2/12 is allocated as an empty band. FIG.
As shown in (b), the counter circuit 1 has an output value = 3,
In the case of 7, 11, and 15, the output value of the MSB-LSB exchange circuit = 12, 14, 13, 15> 11, so that the reading is skipped and +1 is counted up again. In this state, the connection number is output according to the output value of the counter circuit 1 as shown in FIG. 5C. By using this circuit, the frequency of continuous appearance of the same connection number can be reduced as shown in FIG. It becomes possible to reduce.

In the present embodiment, the output of the counter circuit 1 is supplied to the MSB-LSB switching circuit 5 for the MSB-LSB switching circuit 5.
Although the rearrangement is performed so that B and LSB are reversed, the rearrangement method is not limited to this, and an appropriate method is possible. For example, a replacement circuit that adopts a method of sequentially adding a certain natural number to a certain initial value and converting it to a natural number may be used. In this case, for example, assuming that 2 is added to Z = 11, the output values 1, 2, 3,.
1 is 1, 3, 5, 7, 9, 11, 2, 4, 6,
It is converted to 8, 10. In this configuration, the result of the addition is Z
Is exceeded, the value obtained by adding 1 to the initial value is set as a new initial value, and 2 is similarly added. Further, it is also possible to prepare a plurality of natural numbers to be sequentially added and to select an appropriate natural number in accordance with a control signal input from the outside to the replacement circuit. When this configuration is adopted, a cell discard alarm that is output when cell discard occurs or increases in frequency in a device connected downstream of the ATM switch can be used as the control signal. By using this configuration, it is possible to change the replacement algorithm so as to prevent an increase in cell discard in a subsequent device.

The replacement circuit includes: B. Configuration with fixed wiring between input and output terminals; B. a configuration including a matrix switch that selectively connects an input terminal and an output terminal by a control signal input from outside; A memory element in which an input signal is used as a read address signal and data written in a corresponding address is read as a replacement signal can be used. In particular, B. And C.I. When the configuration of B. is adopted, Uses the above-mentioned cell discard alarm as a control signal. In, by using K and a cell discard alarm as input signals, it is possible to adopt a configuration capable of preventing an increase in cell discard of the above-described subsequent apparatus.

FIG. 6 shows the configuration of the second embodiment of the present invention. In this embodiment, a shift register 91 and an exclusive OR 92 are used instead of the counter circuit 1 and the MSB-LSB replacement circuit 5 in the first embodiment.
An M-sequence generation circuit 21 having the configuration shown in FIG. 7 is used. Each time the rising edge of the cell read timing signal arrives at the M-sequence generation circuit 21, the output of each stage of the shift register 91 changes. In order to reset the shift register 91 every time a certain number of cell read timings arrive and return to the initial value, the output obtained by inputting the cell read timing to the counter 93 is input to the comparator 94. When the comparator 94 detects that the output of the counter 93 has reached the predetermined value, the comparator 94 sends a reset signal to the shift register 91 and the counter 93, and resets both. Since the change of the signal formed by the output of each stage of the shift register 91 has a sufficient randomness, the frequency at which the same connection number is continuously output from the connection selection circuit 4 is sufficiently small. In the present embodiment, the shift register 91 constituting the M-sequence generation circuit 21
The number of stages is set to four, but an appropriate number of stages can be selected according to the value of Z.

[0033]

As described above, according to the present invention, the rearrangement of the binary output value of the counter (for example, M
In the case of a value outside the output band, the counter value is skipped, thereby diversifying the connection numbers to be output, and the burstiness of the output for each connection as much as possible. And an ATM switch that realizes a reduction in

Further, by changing the rearrangement method in response to a cell discard alarm from a subsequent device, it is possible to more reliably prevent an increase in cell discard.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 shows MSB-LS in the first embodiment of the present invention.
It is a figure explaining B exchange operation.

FIG. 3 is a flowchart showing the operation of the first embodiment of the present invention.

FIG. 4 shows MSB-LS in the first embodiment of the present invention.
It is a figure explaining the value after B exchange.

FIG. 5 is a diagram illustrating the operation of the first embodiment of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of an M-sequence generation circuit 21 according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 counter circuit 2 cycle setting holding circuit 3 connection band setting holding circuit 4 connection selection circuit 5 MSB-LSB replacement circuit 6 output band determining circuit 7, 67 counter skipping circuit 16 output determining circuit 21 M-sequence generating circuit 91 shift register 92 exclusive Logical OR circuit 93 counter 94 comparator

Claims (23)

[Claims] 1. An ATM switch buffer read control device in an ATM switch accommodating a plurality of connections of different bands, wherein an ATM switch buffer read control device receives an externally input cell read timing signal.
A conversion signal generation unit that outputs a conversion signal for specifying the number of the connection to be read; and a connection selection unit that outputs a connection number that specifies the connection in accordance with the conversion signal. ATM switch buffer read control device. 2. The ATM switch buffer read control device according to claim 1, wherein said conversion signal generation means outputs a result of counting the number of pulses included in the input cell read timing signal as a count signal. Means for converting the counting signal according to a predetermined rule and outputting the converted signal. 3. The ATM switch buffer read control device according to claim 2, wherein said predetermined rule is to reduce the number of continuous outputs of the same connection number from said connection selecting means. An ATM switch buffer reading control device characterized by the above-mentioned. 4. The ATM switch buffer read control device according to claim 2, wherein the ATM switch buffer read control device further compares a number determined by the conversion signal with a predetermined band upper limit value, Output band determination means for outputting the result as a comparison signal; and when the comparison signal is input and the number determined by the conversion signal is larger than the band upper limit value, the counter means is counted by one extra. An ATM switch buffer reading control device, comprising: counter reading means for outputting a counter operation signal for instructing the reading. 5. The ATM switch buffer read control device according to claim 2, wherein said exchange means reverses each digit of the binary display value of said count signal. An ATM switch buffer read control device, wherein the read data is output as a converted signal. 6. The ATM switch buffer read control device according to claim 2, wherein said switching means is configured to perform the counting from a predetermined position in one period of the pseudo random sequence. An ATM switch buffer read control device for outputting, as a conversion signal, values sequentially read in accordance with numerical values. 7. The ATM switch buffer read control device according to claim 2, wherein said switching means receives a predetermined initial value as an initial value signal. A first conversion unit that outputs, as a first conversion signal, a natural number obtained by sequentially adding to the initial value signal in accordance with an increase in the count signal by two or more predetermined natural numbers, and Is compared with a predetermined maximum number, and if the first converted signal is not large, the first converted signal is output as the converted signal, and the first converted signal is output.
When the converted signal is large, a second converting means for inputting a value obtained by adding 1 to the initial value signal to the first converting means as the initial value signal and outputting the same as the converted signal is provided. An ATM switch buffer reading control device characterized by the above-mentioned. 8. The ATM switch buffer read control device according to claim 2, wherein said switching means performs a conversion from said counting signal to said conversion signal in advance. A predetermined initial value is replaced with a predetermined 2
Each of the above natural numbers, if the increased natural number obtained by sequentially increasing according to the increase of the counting signal is not larger than a predetermined natural number, the increased natural number is the converted signal, and the increased natural number is the predetermined natural number. An ATM switch buffer read control device characterized in that when the value is larger than a natural number, a value obtained by adding 1 to the initial value is used as the conversion signal, and the conversion signal is replaced with the initial value. 9. The ATM switch buffer read control device according to claim 2, wherein said switching means comprises fixed wiring between input / output terminals. An ATM switch buffer read control device, characterized in that: 10. The ATM switch buffer read control device according to claim 2, wherein said switching means controls said input terminal and output terminal to be applied from outside. An ATM switch buffer read control device comprising a matrix switch selectively connected based on a signal. 11. The ATM switch buffer read control device according to claim 2, wherein the input means inputs a signal for designating a read address. An ATM switch buffer read control device, comprising: a memory element connected to an address input terminal to output stored data as the conversion signal. 12. The ATM switch buffer read control device according to claim 2, wherein said switching means is inputted from a device to which an output of said ATM switch is inputted. An ATM switch buffer read control device, wherein the predetermined rule is changed based on a cell discard alarm notifying the occurrence or increase of the frequency of cell discard. 13. The ATM switch buffer read control device according to claim 10, wherein the matrix switch is notified of the occurrence or increase of the frequency of cell discarding input from a device to which the output of the ATM switch is input. An ATM switch buffer read control device, wherein a cell discard alarm is input as the control signal. 14. The ATM switch buffer read control device according to claim 11, wherein the address input terminal is notified of the occurrence or increase of the frequency of cell discarding input from a device to which the output of the ATM switch is input. An ATM switch buffer read control device, to which a cell discard alarm and the counting signal are inputted. 15. An ATM switch buffer read control device in an ATM switch accommodating a plurality of connections of different bands, comprising: a predetermined number of shift register means; and at least one predetermined stage of the shift register means. An exclusive-OR means for receiving an output, calculating an exclusive-OR, and feeding back an exclusive-OR signal obtained by calculating the exclusive-OR to a first stage of the shift register means; An ATM switch buffer reading control device, comprising: a connection selecting means for outputting a predetermined connection number. 16. An ATM switch buffer read control method in an ATM switch accommodating a plurality of different bandwidth connections, comprising: a counting step of counting the number of pulses included in a cell read timing signal input from the outside; According to a predetermined rule, the count value obtained in the counting process
Converting a connection number assigned to a connection accommodated in the M-switch into a connection number assigned to the M-switch. 17. The AT according to claim 16, wherein said conversion step includes a reference step of determining said connection number by referring to a table defining a correspondence relationship between said count value and said connection number.
M switch buffer read control method. 18. The numerical value conversion step of converting the count value into a conversion value according to a predetermined rule, and the connection number by referring to a table defining the correspondence between the conversion value and the connection number. 17. The method according to claim 16, further comprising the step of:
TM switch buffer read control method. 19. The conversion step, wherein the conversion step converts the count value into a conversion value according to a predetermined rule; a comparison step of comparing the conversion value with a predetermined value; As a result of the step, when it is found that the converted value is larger, the feedback step of temporarily interrupting the counting step, and the connection number with reference to a table defining the correspondence between the converted value and the connection number 17. The method according to claim 16, further comprising the step of:
TM switch buffer read control method. 20. The numerical value conversion step includes a step of, as the conversion value, a binary display value obtained by rearranging each digit in the case where the count value is displayed in binary number in reverse order. An ATM switch buffer read control method according to any one of claims 18 and 19. 21. The method according to claim 18, wherein the numerical value conversion step includes a step of, as a converted value, a value sequentially read from a predetermined position in one period of a pseudo random sequence in accordance with the count value. An ATM switch buffer read control method according to claim 19. 22. The numerical value conversion step includes: converting the count value into the converted value by a predetermined initial value, by a predetermined natural number of 2 or more, sequentially according to an increase in the count signal. When the increased natural number obtained by increasing is not larger than a predetermined natural number, the increased natural number is set as the conversion value, and when the increased natural number is larger than the predetermined natural number, a value obtained by adding 1 to the initial value. 18. The method of claim 18, further comprising the step of:
An ATM switch buffer read control method according to claim 9. 23. The ATM switch buffer read control method according to claim 16, wherein said ATM switch buffer read control method further comprises monitoring an operation state of an external device. An ATM switch buffer read control method, comprising an algorithm change step of changing the predetermined rule in the conversion step according to the result.