JPH1131071A - Sequence arithmetic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the sequence arithmetic circuit which can reduce the power consumption of a register group while relaxing restrictions of the arithmetic time of the arithmetic circuit. SOLUTION: The registers 21 to 24 of a register group 2 each consist of a one-stage flip-flop FF21 and a multiplexer MUX 25 which selects the input to the flip-flop FF21 at a rise of a clock. The flip-flop FF 23 is shared by the registers, selected by the multiplexer MUX 22 and determined at a fall of the clock, and a multiplexer MUX 24 selects the outputs of FF21 and FF23 and inputs them to an arithmetic part 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram-based sequence operation circuit, and more particularly to a register group configuration.

[0002]

2. Description of the Related Art As shown in FIG. 3, a sequence operation circuit of this type includes an operation unit 1 for operating operation source data and outputting the result, and a register group for holding and storing the operation source data and the operation result. 2 (2 _{1 to} 2 ₄ ).

In the register group 2, for example, when an operation of A + 1 → B is performed, a register for holding and storing data of A as an operation source is an operation source register, and holding and storing of data of B as an operation result. This register becomes the operation result storage register. The selection of the operation source register and the operation result storage register is performed by a microprogram.

[0004] each of the registers ₂₁ to ₂₄ is, of the two-stage flip-flop FF13, FF14 and multiplexer MUX12
It consists of. The output of the register group 2 is selected by the multiplexer MUX11 and input to the operation unit 1.

[0005] Of the register group 2, the operation source register selected by the microprogram inputs the output of the second-stage flip-flop FF14 to the operation unit 1 via the multiplexer MUX11. The operation unit 1 inputs the operation result to one of the register groups 2.

The register group 2 includes a multiplexer MUX1
At 2, the operation result storage register is selected, and the operation result from the operation unit 1 is stored in the first-stage flip-flop FF13. Other unselected registers take in the output of their own second-stage flip-flop FF14 into the first-stage flip-flop FF13.

The selection of the multiplexers MUX11 and MUX12 is determined by the selection signals SEL1 and SEL2. The data update of the flip-flops FF13 and FF14 is 2
The timing is controlled by the phase clocks CLK1 and CLK2. This relationship is as shown in the time chart of FIG.

[0008]

In a conventional sequence operation circuit, a register for transferring data by using a two-phase clock can have a time difference between the operations of the two-stage flip-flops, so that the data can be updated stably. And the occurrence of racing can be prevented.

However, the time from the data update of the flip-flop FF14 to the data update of the flip-flop FF13 is, as apparent from the time chart of FIG.
This is the time obtained by subtracting the time difference between the two-phase clocks from one cycle of the clock. For this reason, since the arithmetic circuit calculates the data of the flip-flop FF14 and stores the data in the flip-flop FF13, it is necessary to suppress the arithmetic time of the arithmetic unit 1 within the above update time. Restrictions become strong, and malfunction may occur.

Further, in the conventional circuit, since each register requires two stages of flip-flops, current consumption tends to increase. The power consumption of the register group accounts for a large proportion of the power consumption of the entire sequence operation circuit, and the influence on the entire sequence operation circuit increases.

An object of the present invention is to provide a sequence operation circuit capable of reducing the power consumption of a register group while relaxing the restriction on the operation time of the operation circuit.

[0012]

According to the present invention, in order to solve the above-mentioned problem, a flip-flop of a register group is constituted by one stage, and a second stage flip-flop is shared by each register, so that the rising and falling edges of a clock are used. Each of the outputs is determined, and is characterized by the following configuration.

An operation unit for operating the operation source data and outputting the operation result; and a register group for holding and storing the operation source data and the operation result. In a sequence operation circuit to select as a destination register, each register of the register group selects an output from the operation unit when the register is selected as an operation result storage destination,
A first multiplexer that selects its own output when not selected, and a first flip-flop that determines the output through the multiplexer at the rising edge of the clock, and A second multiplexer that selects an output, a second flip-flop that determines the output of the second multiplexer at the falling edge of the clock, an output of the second multiplexer, and an output of the second flip-flop. And a third multiplexer for selecting the signal according to the “low level” and “high level” of the clock and taking in the arithmetic unit.

[0014]

FIG. 1 is a configuration diagram of a sequence operation circuit showing an embodiment of the present invention. Register group 2A
Is provided with a single flip-flop FF21 and a multiplexer MUX25, respectively, and as a second-stage flip-flop, a flip-flop FF23 shared with a register is provided downstream of the multiplexer MUX22, thereby halving the number of flip-flops in the register group. Flip-flop FF
A multiplexer MUX 24 for register selection is provided between the arithmetic unit 23 and the arithmetic unit 1.

The flip-flop FF21 has a clock CL
The output is determined at the rise of K, and the flip-flop FF
23 determines the output at the falling edge of the clock CLK.

FIG. 2 shows a time chart of the sequence operation circuit according to the present embodiment. At the rise of the clock CLK, the output of the FF 21 is determined, and the multiplexer MUX2
2 inputs the output of the register selected as the operation source to the flip-flop FF23. Flip-flop FF2
In No. 3, since the output is determined at the falling edge of the clock, the operation between the two flip-flops FF21 and FF23 can secure a time difference of a half cycle of the clock CLK, and can prevent racing as in the related art.

The multiplexer MUX 24 selects the outputs of the flip-flops FF21 and FF23 and supplies the outputs to the operation unit 1. In this selection, the output of the flip-flop FF23 is input to the arithmetic unit 1 when the clock CLK is at the "low level" by the selection signal SEL1, and the "high level"
In the case of, the output of the flip-flop FF21 is
, The output of the multiplexer MUX24 always changes in synchronization with the rise of the clock CLK.

The register selected as the operation result storage destination selects the output of the operation unit by the multiplexer MUX25 and takes it into the flip-flop FF21. Other unselected registers are their own flip-flops FF21
Capture the output of Thus, one cycle from the rising edge of the clock CLK to the next rising edge can be used for the delay time of the arithmetic circuit.

[0019]

As described above, according to the present invention, the flip-flops of the register group have a single-stage configuration, and the flip-flops of the second stage are shared by the registers so that the respective outputs are output at the rising and falling edges of the clock. The following effects are obtained because the determination is made.

(1) The time margin of the arithmetic circuit is conventionally limited to a value obtained by excluding the time difference between two-phase clocks, but one cycle of the clock can be secured.

(2) Set the flip-flop of the register group to 1
A stage configuration can be employed, and power consumption can be reduced by halving the number of flip-flops in the register group.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a sequence operation circuit according to an embodiment of the present invention.

FIG. 2 is a time chart in the embodiment.

FIG. 3 is a configuration diagram of a conventional sequence operation circuit.

FIG. 4 is a conventional time chart.

[Explanation of symbols]

1 ... arithmetic unit 2 ... register group ₂₁ to ₂₄ ... register FF 21, FF 23 ... flip-flop MUX25, MUX22, MUX24 ... multiplexer

Claims (1)

[Claims] 1. An operation unit for calculating operation source data and outputting the result, and a register group for holding and storing the operation source data and the operation result, wherein the register group is operated by a microprogram with the operation source register. In a sequence operation circuit for selecting as a result storage destination register, each register of the register group selects an output from the operation unit when the register is selected as an operation result storage destination, and outputs its own output when not selected. And a first flip-flop that determines the output through the multiplexer at the rising edge of the clock, and a second flip-flop that selects the output of the register that is the operation source among the registers. A multiplexer for determining an output of the second multiplexer at a falling edge of the clock; A flip-flop, and a third multiplexer that selects an output of the second multiplexer and an output of the second flip-flop in accordance with a “low level” and a “high level” of a clock and takes in the arithmetic unit. A sequence operation circuit.