JPH11307733A - Manufacturing ferroelectric integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the harmful ineffects of hydrogen and hold superior electrical characteristics of a ferroelectric. SOLUTION: This integrated circuit is formed so as to have a ferroelectric material having a metal oxide material having at least two metals, various methods and structures are applied to minimize the performance reduction of ferroelectric characteristics due to hydrogen appearing during the formation of circuits, and oxygen is added during forming of the circuits to an element of the integrated circuit so as to act as an hydrogen getter. To minimize the performance reduction due to hydrogen, the ferroelectric compound is made from a liq. precursor containing at least one of component metals excessively about the stoichiometric concentration and preferably an hydrogen barrier layer containing. TiN is formed to cover the top of the ferroelectric. The hydrogen heat treatment in hydrogen gas at 200-350 deg.C for less than 30 min is executed for the integrated circuit to recover other characteristics of the integrated circuit and minimize the performance reduction of the ferroelectric characteristics. The oxygen recovery anneal at 800 deg.C recovers the ferroelectric characteristics after the high temperature and long time hydrogen process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for producing a layered superlattice material and an ABO ₃ type metal oxide, and more particularly to a ferroelectric integrated circuit for protecting a ferroelectric element from being damaged by hydrogen. It relates to a manufacturing method.

[0002]

2. Description of the Related Art Ferroelectric compounds are disclosed in U.S. Pat.
As described in U.S. Pat. No. 5,046,043 (mirror), it has favorable characteristics in using a nonvolatile integrated circuit memory. Ferroelectric devices such as capacitors are useful as non-volatile memories when they have desired electrical properties such as high remanent polarization, moderate coercive field, high fatigue resistance, and low leakage current.

[0003] PZT (lead zirconate titanate), PLZT
Lead-containing ABO ₃ -type ferroelectric oxides such as (lanthanum-added lead zirconate titanate) have been studied for practical use in integrated circuits.

On the other hand, for layered superlattice oxide materials,
As described in U.S. Pat. No. 5,434,102 (mirror), research is being conducted for practical use in integrated circuits. The layered superlattice material compound is PZT
And ferroelectric memory characteristics superior to those of PLZT compounds.

[0005] On the other hand, although a prototype of a ferroelectric memory using a layered superlattice material compound has been manufactured, ABO has been developed.
Manufacturing processes that use either a type ₃ metal oxide and a layered superlattice material compound to economically fabricate a commercially viable quantity of memory with the desired electrical properties have yet to be proposed. It is not at present.

[0006]

One reason that there is no economic and commercial process for producing high quality ferroelectric integrated circuits is that metal oxide compounds are reduced by hydrogen during hydrogen annealing. It is easy to be done. Hydrogen annealing is a process commonly performed in the manufacture of CMOS integrated circuits, and causes a reduction in the performance of ferroelectric characteristics. This is especially true for layered superlattice material compounds. This is because the layered superlattice compound is a complex layered oxide whose performance tends to be deteriorated by hydrogen.

A typical ferroelectric memory device in an integrated circuit includes a semiconductor substrate and a metal oxide field effect transistor (MOSFET). This transistor is typically electrically connected to a ferroelectric device such as a ferroelectric capacitor. The ferroelectric capacitor typically includes a ferroelectric thin film located between a first lower electrode and a second upper electrode, and these electrodes typically include platinum. I have.

During the manufacture of integrated circuits, MOSFETs
It is placed under conditions that cause defects in the silicon substrate. For example, manufacturing processes typically include high energy steps such as ion milling etching and plasma etching. Such defects are at relatively high temperatures (often in the range of 500-900C).
Also occurs during the heat treatment for crystallizing the ferroelectric thin film.

As a result, many defects occur in the single crystal structure of the semiconductor silicon substrate. This is MOSFET
Leads to the deterioration of the electrical characteristics. MOSFET / CMO
In order to restore the silicon properties of S, the manufacturing process usually includes a hydrogen annealing process. In this step, defects such as dangling bonds are eliminated by utilizing the reduction characteristics of hydrogen. Various techniques have been developed to achieve hydrogen annealing, such as hydrogen gas heat treatment under atmospheric pressure conditions.

Generally, the hydrogen treatment is performed at 350 ° C. to 550 ° C.
C., typically around 400.degree. C. for about 30 minutes. In addition, there are several integrated circuit fabrication processes that expose the integrated circuit to hydrogen. This process may be a CVD process for depositing metal or silane or T
This is a process performed at a high temperature such as growth of silicon oxide from an EOS source.

During the process involving hydrogen, the hydrogen diffuses through the top electrode and the sides of the capacitor to the ferroelectric thin film, reducing the oxides contained in the ferroelectric material. The absorbed hydrogen metallizes the surface of the ferroelectric thin film.

The adhesion of the ferroelectric thin film to the upper electrode is weakened by a chemical change occurring at the interface. Alternatively, the upper electrode is pushed up by oxygen gas, water, and other products of the redox reaction. As a result of these effects, the electrical characteristics of the capacitor are reduced, and "peeling" is more likely to occur between the upper electrode and the ferroelectric thin film.

Further, when the hydrogen reaches the lower electrode, the internal stress causes the capacitor to peel off from the substrate.

This problem is a serious problem in ferroelectric memories containing a layered superlattice material compound. This is because these oxides are particularly complicated and are liable to deteriorate in performance due to hydrogen reduction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. It is an object of the present invention to reduce the harmful effects of hydrogen heat treatment and to improve the ferroelectric properties. The purpose is to maintain electrical characteristics.

[0016]

According to one embodiment of the present invention, there is provided a method of manufacturing a ferroelectric integrated circuit, the method comprising the steps of: A circuit portion is formed, and the integrated circuit portion is heat-treated at a temperature of 350 ° C. or lower in an atmosphere containing hydrogen.

Further, it is desirable that the heat treatment step is performed for a period of less than 30 minutes.

Here, the hydrogen is contained in an amount of 0.01% to 50% by volume of the atmosphere.

Further, the manufacturing method may further comprise, before the heat treatment,
Forming a hydrogen barrier layer directly on at least a portion of the metal oxide material.

Here, the hydrogen barrier layer has titanium nitride or silicon nitride.

Preferably, the heat treatment is performed for a period of less than 30 minutes and the volume percentage of hydrogen in the hydrogen atmosphere is between 0.01 percent and 50 percent.

It is preferable that the metal oxide material has an oxide containing at least two metal elements, and at least one of the metals is present in an excessive amount in the material.

Further, the metal oxide material comprises a layered superlattice compound.

It is desirable that the excess metal element is either niobium or bismuth.

The layered superlattice compound preferably contains strontium bismuth tantalum niobate.

The metal present in an excess amount is preferably niobium.

Further, the manufacturing step includes the steps of providing a precursor liquid for the substrate and the metal oxide material, depositing the precursor on the substrate, and treating it to form the metal oxide material. The metal oxide material has an oxide containing at least two metal elements, and one of the metal elements is present in an excessive amount in the precursor.

The metal element present in an excessive amount is preferably a metal which does not form a nonvolatile compound dispersed in the manufacturing process.

The forming step includes a precursor liquid for the substrate and the metal oxide material, depositing the precursor on the substrate, treating the precursor to form the metal oxide material, Has strontium, bismuth, tantalum, niobium, and the precursor has the stoichiometric formula SrB
i _{2.18 Contains} strontium, bismuth, tantalum, and niobium as chemical elements having a relative molar ratio substantially corresponding to Ta _2-x Nb _x O ₉ (0 ≦ X ≦ 2).

The precursor has the formula SrBi _2.18 Ta
_It is preferable to include a loading of bismuth corresponding to between 0% and 40%, in excess of the stoichiometric amount represented by _2-X Nb _X O ₉ (0 ≦ X ≦ 2).

The precursor has the formula SrBi _2.18 Ta
_It contains the relative molar ratios of strontium, bismuth, tantalum, and niobium, which are elements substantially corresponding to _2-X Nb _X O ₉ .

The precursor is represented by the formula SrBi _2.18
It is desirable to include an excess of niobium corresponding to between 0% and 40% beyond the stoichiometric amount represented by Ta _2-X Nb _X O ₉ .

Further, the manufacturing method includes a step of performing an oxygen recovery annealing in a hydrogen-containing atmosphere after the heat treatment step.
It is carried out in a temperature range of 00 ° C. for a period of from 20 minutes to 2 hours.

According to another embodiment of the present invention, in a method of manufacturing a ferroelectric integrated circuit, an integrated circuit portion including a thin film made of a metal oxide material is formed, and the integrated circuit portion is placed in an atmosphere containing hydrogen. And a heat treatment for 30 minutes or less.

Further, the manufacturing method includes a step of performing an oxygen recovery annealing in a hydrogen atmosphere after the heat treatment step.
It is carried out in a temperature range of ° C. for between 20 minutes and 2 hours.

Further, before the heat treatment, a step of forming a hydrogen barrier layer directly on at least a part of the metal oxide material is provided.

Preferably, the metal oxide material has an oxide containing at least two metals, and at least one of the metal elements is present in an excessive amount in the material.

Further, according to another embodiment of the present invention, there is provided a method of manufacturing a ferroelectric integrated circuit including a metal oxide material, comprising the steps of: forming a metal oxide having a layered superlattice compound having an excess amount of a B-site element; Forming a part of an integrated circuit including a thin film of a material, exposing a part of the integrated circuit to hydrogen, and including a thin film of a metal oxide material in a component of the integrated circuit.
Complete the integrated circuit.

Further, the manufacturing method includes a step of heat-treating the integrated circuit portion while the integrated circuit is exposed to hydrogen.

Further, the manufacturing method has a step of performing an oxygen recovery annealing after the step of exposing the integrated circuit portion to hydrogen.

Here, the oxygen recovery annealing is performed at a temperature range of 300 ° C. to 1000 ° C. for 20 minutes to 2 hours.

Further, the manufacturing method has a step of forming a hydrogen barrier layer directly on at least a part of the metal oxide material before the step of exposing to hydrogen.

The hydrogen barrier layer preferably contains titanium nitride or silicon nitride.

The layered superlattice compound contains strontium bismuth tantalum niobate.

The excess metal element is niobium, and the superlattice compound has an excess amount of bismuth.

In the forming step, a precursor liquid for the substrate and the metal oxide material is prepared, and the precursor is attached to the substrate.
Treating the precursor to form a thin film of a metal oxide material.

[0047]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, it should be understood that FIGS. 1, 3 and 4 show a ferroelectric integrated circuit device.
Does not necessarily correspond to the plane or cross section of an actual integrated circuit. That is, in a real device, the layers will not be regular and their thicknesses may also have different proportions. In practical devices, the various layers often have bent or overlapping ends.

[0048] Instead, the drawings illustrate an ideal representative, which more clearly and fully describes the structure and process of the present invention. It should also be noted that the drawings show only one of many variations of a ferroelectric device manufactured using the method of the present invention.

FIG. 1 shows a ferroelectric memory including a field effect transistor type switch electrically connected to a ferroelectric capacitor. However, the method of the present invention can also be used to manufacture a ferroelectric FET in which a ferroelectric element is incorporated in a switch element. like this,
Ferroelectric FETs are disclosed in US Pat. No. 5,523,96.
No. 4 (McMillan). Similarly,
Other integrated circuits manufactured using the method of the present invention may have other components and material compositions.

Referring to FIG. 1, there is shown a cross-sectional view of a typical nonvolatile ferroelectric memory manufactured by the method of the present invention. A typical manufacturing process for manufacturing integrated circuits including MOSFETs and ferroelectric capacitors is:
U.S. Patent No. 5,561,307 (Yoshimo
ri), the integrated circuit of FIG. 1 will be described only briefly here. Conventional manufacturing methods are also disclosed in other documents.

In FIG. 1, field oxide region 102
Are formed on the surface of the silicon substrate 104. A source region 106 and a drain region 108 are formed in the silicon substrate 104 so as to be separated from each other. Further, the gate insulating layer 112 is
Over the source and drain regions 106, 1
08 is formed. Further, the gate electrode 110
Are formed on the gate insulating layer 112. The source region 106, the drain region 108, the gate insulating layer 112, and the gate electrode 110 form a MOSFE.
T113 is configured.

Further, a first interlayer dielectric layer (ILD) 114 formed of BPSG (boron-doped phosphosilicate glass) is provided on the substrate 104,
In addition, it is formed on field oxide region 102.
Further, an adhesive layer 116 is formed on a part of the ILD 114, and furthermore, the ferroelectric thin film capacitor 11
8 is formed on the adhesive layer 116.

Here, the adhesive layer 116 is formed of, for example, titanium, and typically has a thickness of 200 °. The ferroelectric capacitor 118 is preferably formed on a common wafer 140 that is an insulator such as silicon, gallium arsenide, other semiconductors, or glass or magnesium oxide (MgO).

The lower and upper electrodes of the ferroelectric capacitor contain platinum as before. here,
The lower electrode 120 preferably contains a noble metal that is not easily oxidized, such as platinum, palladium, silver, and gold. In addition to precious metals, aluminum, aluminum alloys, aluminum silicon,
Metals such as aluminum nickel, nickel alloys, copper alloys, and aluminum copper may be used as the electrodes of the ferroelectric memory.

An adhesive layer 116, such as titanium, enhances the adhesion of the electrode to the adjacent underlying or top layer of the circuit.

In FIG. 1, a ferroelectric capacitor 11
8 includes a lower electrode 120, a ferroelectric thin film 122, and an upper electrode 124. Here, the lower electrode 122
Is made of platinum and has a thickness of 2000 mm. The ferroelectric thin film 124 is formed on the lower electrode 122. The upper electrode 124 made of platinum is formed on the ferroelectric thin film 122 and has a thickness of 2000 °. Further, preferably,
An electrically conductive hydrogen barrier layer 126 is formed on top electrode 124 and has a thickness of 500-2000 °.

The hydrogen barrier layer 126 may be composed of a single film, for example, titanium nitride or silicon nitride. Alternatively, two or more films, for example, a titanium film may be provided at the bottom, and a titanium nitride film may be subsequently provided.

When the hydrogen barrier layer 126 is formed of an electrically conductive material such as titanium nitride, and acts as a conductor, the hydrogen barrier layer 126 and the upper electrode 124 are self-aligned. The hydrogen barrier layer 126 is patterned together with the upper electrode 124.

[0059] The hydrogen barrier layer 126 is deposited by conventional sputtering techniques. The composition of the ferroelectric thin film 122 will be described in more detail below.

A second interlayer dielectric layer (ILD) 128 made of NSG (non-doped silicate glass)
It is formed on the ILD layer 114. A PSG (phosphosilicate glass) film or a BPSG film can be used as the ILD layer 128.

An opening 114A is selectively formed through the ILD layer 128 to expose the source region 106 and the drain region 108.

The source electrode wiring 130 and the drain electrode wiring 132 are formed so as to fill the opening 114A.
Further, another opening 128A is provided to expose the electrically conductive hydrogen barrier layer 126 and the lower electrode 120, so that the IL
It is selectively formed through the D layer 128.

The upper electrode wiring 134 and the lower electrode wiring 136
Are formed so as to fill the opening 128A. The drain electrode wiring 132 is electrically connected to the upper electrode wiring 134. These wirings 130, 132, 134,
In addition, each of 136 includes Al-Si-Cu (1% Si,
0.5% Cu) and has a thickness of 3000 °.

If the hydrogen barrier layer 126 is non-conductive, at least a portion of the hydrogen barrier layer 126 needs to be removed so that the wiring layer 134 can make electrical contact with the upper electrode 124.

The composition of the ferroelectric thin film 122 is not particularly limited, but can be selected from a preferable group of ferroelectric materials. For example, ferroelectric materials include titanates (BaTiO ₃ , SrTiO ₃ , PbTiO _3)
3 (PT), PbZrTiO ₃ (PZT, etc.), and an ABO ₃ type metal oxide having a perovskite structure such as a niobate (KNbO _3, etc.), preferably a layered superlattice compound.

ABO ₃ type metal oxides are a group of known ferroelectrics and ferroelectric constants. This means that
co Jona and G. Shirane, Ferroelectric Crystal, Dover Publishing, N.M. Y. , P. 108.

US Pat. No. 5,519,234, issued May 21, 1996, states that layered superlattice compounds, such as strontium bismuth tantalate, are stronger than conventional best materials. It is disclosed that it has excellent properties in the dielectric field, and that it has a high dielectric constant and a low leakage current.

US Pat. No. 5,434,102 issued Jul. 18, 1995 and US Pat. No. 5,468,68 issued Nov. 21, 1995.
No. 4 discloses a process for integrating these materials into a real integrated circuit. This layered superlattice material is generally summarized under the following chemical formula (1).

[0069]

Embedded image Here, A1, A2. . . Aj represents an A-site element in the perovskite-like structure. The A-site element may be strontium, calcium, barium, bismuth, lead and other elements.

S1, S2. . . Sk represents a superlattice forming element. Here, the superlattice forming element is usually bismuth, but yttrium, scandium, lanthanum,
Materials such as antimony, chromium, thallium, and other elements having a valence of +3 may be used.

Here, B1, B2. . . Bl represents a B-site element in the perovskite-like structure. This B-site element includes titanium, tantalum, tungsten,
Niobium, zirconium, and other elements may be used.

Q represents an anion (anion).
The anion is generally oxygen, but may be another element, such as a complex of these elements, such as fluorine, chlorine, oxyfluoride, oxychloride. The superscript in the chemical formula (1) indicates the valence of each element, and the subscript indicates the number of moles of the material in 1 mole of the compound, and the unit cell as an average in relation to the unit cell. Shows the number of atoms in the element inside. Here, the subscript takes an integer or a fraction. That is, the chemical formula (1) indicates that the unit cell is composed of the material (on average, Sr. ₇₅ B
a. ₂₅ Bi ₂ Ta ₂ O ₉ ). In this example, 75% of the A-site is occupied by strontium atoms and 2% of the A-site
5% is occupied by barium atoms. If only one A-site is present in the compound,
It is equivalent to the A1 element and w2. . . wj
Can be represented by If, on the other hand, only one B-site element is present in the compound, it is y2. . . yl, and
It can be expressed similarly to the superlattice forming element.

Although formula (1) is described in a more general form, the usual case is that one A-site element, one superlattice-forming element, and one or two B-sites This is the case when the element is present. The description of formula (1) is intended to include the more general case where any of the above sites and the superlattice generator have a composite element.

The value of z is obtained from the following equation. (2) (a1w1 + a2w2 ... ajwj) + (s1
x1 + s2x2. . . + Skxk) + (b1yi + b2
y2. . . + Blyl) = 2z Formula (1) includes all three Smolenski-type compounds discussed in U.S. Pat. No. 5,519,234, issued May 21, 1996. Layered superlattice materials do not include all materials that meet chemical formula (1), but only include those that can naturally form a crystalline structure with clearly distinguishable alternating layers.

Here, the “substrate” means not only the base wafer 104 on which the integrated circuit is formed, but also the BPSG layer 114.
Means an object on which a thin film is deposited. As used herein, "substrate" means the object to which the relevant layer applies. For example, taking a lower electrode such as 120 as an example, the substrate may be a layer 116 on which the electrode 120 is formed.
And 114. The term "thin film" is also used herein in the sense as used in the integrated circuit field. It usually means a submicron film in thickness. The thin films disclosed herein are in all cases less than 0.5 microns in thickness. In the case of the ferroelectric thin film 122, the thickness is preferably from 1000 to 3000, and most preferably from 1200 to 2500. These thin films of integrated circuit technology should not be confused with multilayer capacitors, such as macroscopic capacitors, formed in a completely different process unrelated to integrated circuit technology.

As used herein, "stoichiometric" applies to both solid phase films of materials such as layered superlattice materials and precursors for forming the material. When it is applied to a solid phase film, it relates to a formula that indicates the actual relative amounts of each element of the last solid film. When applied to a precursor, it indicates the molar ratio of the metal in the precursor. A "balanced" stoichiometric formula states that at every site of the occupied crystal lattice, there are enough elements to occupy all sites so that each element forms the complete crystal structure of the material State. However, in reality, at room temperature, there will always be lattice defects. For example, SrBi ₂ TaNbO ₉ and SrBi ₂ Ta
_1.44 Nb _0.56 O ₉ is a balanced stoichiometric formula.
In contrast, the molar ratios of strontium, bismuth, tantalum, and niobium are 1, 2.18, 1.44,
Strontium-bismuth-tantalum-0.56
The niobate precursor has a heterogeneous stoichiometric formula SrBi
_2.18 represented by Ta _1.44 Nb _0.56 O ₉ . This is because it contains an excess of bismuth beyond that required to form a perfect crystalline material.

[0077] As used herein, an excess of a metal element is defined as binding to other metals that are present to form the desired material, with all atomic sites occupied and no metal remaining. Means more than required. But,
As is known, in fabricating the electronic devices of the present invention, the solid phase ferroelectric layer created by the process of the present invention because bismuth oxide is highly volatile and uses considerable heat The molar ratio of bismuth at 122,422 will generally be lower than that in the stoichiometric formula of the precursor. However, the molar ratios of strontium, tantalum, and niobium in the ferroelectric layers 122, 124 produced by the process of the present invention may be very close to or equal to the molar ratio given by the stoichiometric formula for the precursor. Conceivable. This is also described in US Pat. No. 5,434,102 (Watanabe).

The above US Patent (5,434,102)
Based on and related art, precursors for forming layered superlattice materials preferred by those skilled in the art have the stoichiometric formula Sr
It currently has Bi _2.18 Ta _1.44 Nb _0.56 O ₉ . The precursor of this formula has the homogenized stoichiometric formula SrBi
_It may be believed that a final solid phase strontium, tantalum, niobate with _2.18 Ta _1.44 Nb _0.56 O ₉ will be produced. That is, the final film does not contain excess bismuth. This is because excess bismuth in the precursor is eliminated as bismuth oxidizing gas in the manufacturing process.

The ferroelectric layer 422 exemplified below
Was made from a strontium bismuth tantalum niobate solution commercially available from Hughes Aircraft Company, product number HAC10475-47.

The precursor solution has a stoichiometric ratio SrBi
_2.18 Includes the content of chemical precursor corresponding to Ta _1.44 Nb _0.56 O ₉ . This stoichiometric formula is treated herein as a standard composition having a standard niobium to tantalum ratio. Precursors having this standard stoichiometric formula contain about 9% excess bismuth. That is, the standard stoichiometric formula states that all atomic sites in the crystal are occupied, and that bismuth exceeds the amount required to combine with strontium-tantalum-niobium to form a layered superlattice compound. Having a content of

One of the features of the present invention is that the final layered superlattice compound in which the content of at least one element of bismuth, niobium and the like is excessive as compared with that shown in the standard formula, It has greater resistance to performance degradation due to hydrogen than materials formed from precursors having the formula composition.

A related feature is that in layered superlattice materials, the excess content of B-site elements, such as niobium, is effective in preventing the degradation of electrical properties due to exposure to hydrogen. That is.

FIG. 2 shows a flow chart of the manufacturing process used in the present invention to make a ferroelectric memory.

In step 212, the semiconductor substrate 104 is prepared, and a switch is formed thereon in step 214. This switch is typically a MOSFET. At step 216, an insulating layer is formed to separate the switch from the ferroelectric to be formed. In step 218, the lower electrode 120 is formed. Preferably, the electrode is formed of platinum and has a thickness of about 200
Sputter deposited to form a layer having a thickness of 0 °.

In this step, an adhesive layer 116 of about 200 ° of titanium or titanium nitride is formed before depositing the electrodes.

In step 222, the ferroelectric thin film 1
22 is attached to the lower electrode 120. Preferably, the ferroelectric thin film 122 includes a layered superlattice compound. This ferroelectric thin film 122 is disclosed in US Pat. No. 5,546,9.
As described at 45, it is desirably applied using liquid deposition techniques such as spin coating or spray deposition methods. The most preferred method is spin
On technology is used to form thin films.

In step 220, a chemical precursor of the layered superlattice compound to form the desired ferroelectric thin film 122 is prepared. Usually, the final precursor solution is prepared from a commercially available solution containing the chemical precursor compound.

Preferably, the concentrations of the various precursors in the commercially available solutions are adjusted in step 220 to suit individual manufacturing or operating conditions. For example, the stoichiometric content of various elements in a typical commercially available solution for a layered superlattice thin film is
rBi _2.18 Ta _1.44 Nb _0.56 O ₉ .
However, in order to generate other oxides to protect the ferroelectric compound from performance degradation due to hydrogen annealing,
It is often preferable to add niobium or bismuth to this solution.

The deposition step 222 is preferably performed before the processing step 224, which is a crystallization step at high temperatures such as a dry step and a rapid thermal process. Attachment step 22
2 may include a treatment with ultraviolet radiation during or after the deposition process 222.

For example, in a typical spin-on process,
A layer of the precursor is deposited and dried. Then, the next precursor layer may be deposited and dried. The processed film is then annealed in step 226 in oxygen to form the resulting ferroelectric thin film.

The deposition and processing steps 222 and 224 may be repeated several times.

Following steps 222-226, upper electrode 124 is formed at step 228. Step 22
8 and other steps may include sub-steps such as ion etching and ashing.

Preferably, a hydrogen barrier layer 126 is formed at step 230 over at least the upper electrode 124 of the capacitor. Typically, the hydrogen barrier layer 126 is titanium nitride, which prevents diffusion of hydrogen into the ferroelectric and is also electrically conductive.

Further, it is desirable to add a small amount of oxygen to the barrier film by including a small amount of oxygen gas in the sputtering atmosphere at the time of sputter deposition of the hydrogen barrier layer 126. The resulting oxide formed in the hydrogen barrier layer 126 protects the ferroelectric compound in the memory device by reacting with hydrogen present in various manufacturing process steps.

In step 232, a hydrogen anneal of the ferroelectric memory was selected to sufficiently eliminate defects created in the silicon substrate by oxidation and to minimize performance degradation due to hydrogen in the ferroelectric compound. It is performed under temperature and annealing time. The hydrogen annealing step is preferably performed in a hydrogen gas atmosphere. Because other alternatives like hydrogen plasma anneal,
Because it is not so complicated.

At step 234, an oxygen recovery anneal is performed to restore the reduced ferroelectric electrical properties as a result of the hydrogen anneal and other processing steps that produce hydrogenation or reduction conditions.

The integrated circuit is completed in the next step 236. This step consists of a number of sub-steps, for example, I
Including deposition of LD layers, patterning and ion milling, and deposition of wiring layers.

Experiments have shown that hydrogen (H ₂ ) gas anneal at 200 ° C. for about 10 minutes, compared to the damage caused by hydrogen anneal at higher temperature and for a longer period of time,
It very effectively prevents the performance degradation of the electrical characteristics in the ferroelectric element. Nevertheless, the purpose of hydrogen heat treatment,
That is, conditions for achieving the recovery of the surface state of the transistor damaged by oxygen are not always possible.

Furthermore, such conditions alone may not be sufficient to adequately protect the ferroelectric compound from performance degradation due to hydrogen. For this reason, the present invention uses various processes to protect the memory device from hydrogen damage. These steps can be used in conjunction with or instead of low temperature, short time hydrogen heat treatment.

In a preferred method of the present invention, the heat treatment of hydrogen in the integrated circuit is performed at a temperature of 200 ° C. for 10 minutes at a atmospheric pressure using a mixed gas of H ₂ —N _{2 having} a H ₂ concentration of 1-5%. Done. The beneficial effect of low temperature, short duration hydrogen heat treatment is 350
Significant up to a temperature of ° C. and a period of 30 minutes. In the hydrogen heat treatment of the present invention, the volume percentage of hydrogen gas is 0.01-5%.
It can be performed in a hydrogen atmosphere in the range of 0%. This is because the diffusion of hydrogen in an integrated circuit is a step in which diffusion is rate-determining.

In the low-temperature, short-time hydrogen annealing according to the present invention, the ferroelectric thin film 122 is made of a general formula SrBi _2.18 Ta _2-x Nb _x
This is effective for protecting the electrical characteristics of a nonvolatile ferroelectric capacitor including a Bi-layered superlattice material formed from a precursor having a composition substantially corresponding to (0 ≦ X ≦ 2). Experiments show that low-temperature, short-term hydrotreatment has a composition that roughly corresponds to the general stoichiometric formula SrBi _2.18 Ta _1.44 Nb _0.56 O ₉ with a precursor molar ratio Nb / Ta of about 0.4. It is most effective in protecting the superlattice compound consisting of the precursor solution.

Further, according to experiments, it was found that the expression SrBi _2.18 T
The addition of excess bismuth or niobium to the precursor having a relative content corresponding to a _1.44 Nb _0.56 O ₉ is effective in protecting the desired electrical properties from performance degradation due to hydrogen.

In the ferroelectric capacitor of the present invention, the upper electrode 124 is covered with a hydrogen barrier layer 126, preferably, titanium nitride. The performance degradation due to hydrogen in the ferroelectric properties is partially or fully restored to regain excellent electrical properties by oxygen recovery annealing.

According to experiments, the lateral diffusion of hydrogen, ie, the diffusion in the direction parallel to the plane of the ferroelectric film,
Compared to diffusion in the direction normal to the plane of the ferroelectric film, it is not so important. A small portion of the ferroelectric material at the lateral ends of the ferroelectric layers 122, 422 acts as a getter for laterally invading hydrogen, protecting the remainder of the ferroelectric material from hydrogen.

In a typical manufacturing procedure, a hydrogen heat treatment is performed before circuit wiring is deposited and patterned. In addition, other process procedures and steps can be used. For example, the opening of the contact wiring of the MOSFET is
The opening that opens before the hydrogen treatment, while opening the ferroelectric electrode through the ILD layer can also be made after the hydrogen heat treatment step.

FIG. 3 shows a thin film capacitor 396, 398, 400 fabricated on a substrate 300 according to the present invention.
A top view of a representative wafer formed thereon is shown in a greatly enlarged manner. FIG. 4 shows a thin film capacitor element made in accordance with the present invention, and is a portion of a cross section taken along line 4-4 of FIG. A silicon oxide film 402 is formed on a silicon crystal substrate 404. A titanium adhesive layer 416 is formed on the silicon oxide layer 402. A lower electrode 420 of platinum is deposited on the adhesive layer 416 by sputtering. Layer 422 is a ferroelectric thin film, and layer 424 represents a platinum top electrode.

(Example 1) Strontium bismuth
The electrical characteristics of tantalum, niobate and capacitors are
200 ° C, 250 ° C, 300 ° C for 10 minutes, 30
And 60 minutes before and after annealing in hydrogen gas.

The condenser is a strontium bismuth tantalum niobate solution commercially available from Hughes Aircraft Company, product number HA
Manufactured from C10475-47. The solution contains a chemical precursor having a composition corresponding to the stoichiometric formula SrBi _2.18 Ta _1.44 Nb _0.56 O ₉ . This stoichiometric formula is regarded as the "standard" concentration in this or other examples. However, it should be understood that this formula merely represents the relative ratios of the various species in the commercially available precursor solution.

In this example, the 0.2 mol / l precursor solution was tantalum 2-ethylhexanoic acid, bismuth 2-ethylhexanoic acid, strontium 2-ethylhexanoic acid,
Niobium 2-ethylhexanoic acid, 2-ethylhexanoic acid,
It contains xylene. A ferroelectric capacitor containing a layered superlattice compound is disclosed in U.S. Pat.
102 (Watanabe) is formed from this precursor solution. Remanent polarization (2Pr), coercive electric field (Ec), and leakage current in the capacitor were measured before and after hydrogen treatment.

A series of p-type 100 silicon wafer substrates 4
04 was oxidized to form a layer of silicon oxide film 402. Titanium adhesive layer 416 having a thickness of 200 °
Was sputtered onto the substrate, and then a lower platinum electrode 420 having a thickness of 3000 ° was sputter deposited on the adhesive layer 416. These are annealed at 650 ° C. in oxygen for 30 minutes, and at 180 ° C. in a low vacuum for 3 minutes.
It was dehydrated for 0 minutes. Spin coating of a 0.2 molar solution of strontium bismuth niobate compound
Deposited on bottom electrode 420 at 1500 rpm for 0 seconds. This layer was pyrolyzed at 160 ° C. for 1 minute,
The temperature was raised to 0 ° C. and heat-treated for 4 minutes. This spin coating and pyrolysis procedure was repeated.

The ferroelectric film is formed by rapid thermal annealing (RTA: 725 ° C., 30 sec, 100 ° C./sec).
Crystallized using c).

By these steps, 2100 ± 150
A ferroelectric thin film 422 having a thickness of Å was formed. The wafer and the deposited layer underwent a first anneal at 800 ° C. for 60 minutes. Platinum was sputter deposited to form a 2000 ° thick top electrode layer 424, followed by patterning using photoresist (PR process). The platinum and strontium bismuth tantalum niobate layers are etched (milled) by ions to form a capacitor, and then ashed, followed by
A second oxygen anneal was performed at 800 ° C. for 30 minutes.

Before the capacitors were annealed with hydrogen gas, the electrical properties of five capacitors, each having an area of 7854 μm ² , were measured. The leakage current of the capacitor was about 10 ^-7 A / cm ² volt at 5V. The remanent polarization (2Pr) at 5 volts is about 23 μC
/ Cm ² . In a fatigue test performed on one of the capacitors, the 2Pr value decreased about 5 percent after 10 ¹⁰ cycles.

Then, hydrogen annealing is performed by using H ₂ -N ₂ (H
₂ 1%) at 200 ° C, 250 ° C,
Performed on the condenser at a temperature of 300 ° C. for 10, 30, 60 minutes. The surface area of the sample is typically 78
It was 54 μm ² . However, the effect of hydrogen heat treatment on remanent polarization was measured and compared on capacitors with different surface areas.

FIG. 5 shows a graph of the remanent polarization 2Pr at 5 volts as a function of annealing time for capacitors annealed at temperatures of 200 ° C., 250 ° C. and 300 ° C. FIG. 5 shows a minimum temperature of 200 ° C. and a minimum time of 10 ° C.
It is shown that the hydrogen heat treatment in 2 min results in the lowest decrease of the 2Pr value.

The remanent polarization is from 1963 to 196300 μm.
It was measured in capacitors with a surface area in the range of m ^2. This data is plotted in the graph of FIG. In FIG. 6, the vertical axis is 1963 μm
It has been standardized to ² Pr. This data is 2Pr
Shows that the performance degradation does not depend on the size of the capacitor. Therefore, diffusion of hydrogen from the end of the capacitor is not a dominant factor in performance degradation under experimental conditions. This does not mean that the lateral diffusion of hydrogen is insignificant or non-existent.
Rather, if the top surface of the ferroelectric in the integrated circuit is protected from hydrogen diffusion, the sides of the ferroelectric are not protected against lateral hydrogen diffusion in the ferroelectric thin film between the electrodes. Are also very effective in retaining the properties of ferroelectrics. The experiment in Example 6 below tested the effect of a titanium nitride layer deposited on a ferroelectric thin film in a capacitor without lateral protection against lateral hydrogen diffusion.

The current density of the sample annealed at 200 ° C. for 10 minutes is about 10 ⁻⁷ A / cm ² at 5 volts,
It is equal to the value before annealing, and is sufficiently satisfactory as a memory device. However, the leakage currents of the other samples were high and unsatisfactory. When the condenser heat-treated with hydrogen was optically observed, partial peeling of the upper electrode was found to be 20%.
Occurred in all samples except those annealed at 0 ° C. and 250 ° C. for 10 minutes.

Example 2 An oxygen anneal was performed on the capacitor samples that were exposed to the hydrogen heat treatment in Example 1.

The sample was prepared in O ₂ gas at a flow rate of 5 l / m.
At temperatures of 200 ° C, 300 ° C, 400 ° C and 800 ° C,
Annealed for 1 hour. Measurements were performed on three samples for each experimental condition. Remanent polarization and coercive field are 5
V, and the current density was measured between 0 and 10 volts. In the sample where the oxygen recovery anneal was performed at 800 ° C., the electrical properties of the strontium bismuth tantalum niobate capacitor actually recovered completely from the earlier performance degradation caused by the hydrogen treatment. Although the electrical properties of the samples annealed in oxygen at 200 ° C., 300 ° C. and 400 ° C. showed some recovery, they did not recover as much as would be desirable for use in integrated circuits.

Example 3 Strontium Bismuth
Nb / Ta in tantalum niobate precursor solution
The molar ratio was varied at a temperature of 200 ° C. for 10 minutes, 30 minutes and 60 minutes to investigate the effect on the electrical properties of the capacitor before and after hydrogen (H ₂ ) gas annealing.
Strontium, bismuth, tantalum, niobate precursor solutions produced by Kojundo Chemical Laboratory Co., Ltd. were mixed to make the final precursor. The respective product numbers were 34611F and 950234. This solution was prepared according to Table 1 in order to create the specific stoichiometry and Nb / Ta molar ratio in the final precursor solution.
Were mixed as shown in Table 1.

[0121]

[Table 1] Measurements were performed on three samples for each experimental condition. The condenser had an area of 7845 μm ² . The values of the electrical properties of the capacitors made from the precursors with the compositions in Table 1 were measured before hydrogen (H ₂ ) annealing and plotted in the graphs of FIGS.

FIG. 7 is a graph of the remanent polarization of strontium bismuth tantalum niobate capacitors when the Nb / Ta ratio of the precursor was changed. This graph shows that 2Pr is the maximum value near Nb = 1. Nevertheless, the value of 2Pr at Nb = 2 is problematic because the coercive field increases significantly at high Nb values, as shown in FIG.

FIG. 8 shows a graph of the coercive electric field E _C when the Nb / Ta ratio of the precursor was changed. Figure 8 shows that E _C along with Nb concentration is greatly increased.

FIG. 9 shows a graph of leakage current measured at 5 volts with varying precursor Nb / Ta ratios. FIG. 9 shows that the leakage current has a minimum value near Nb = 0.56. The leakage current for Nb concentrations ≥ 1.6 is too high for most circuit applications.

The effect of the hydrogen annealing is shown in FIGS.

The sample was placed in an atmosphere of H ₂ (5%)-N _{2 for 2} hours.
Annealed at 00 ° C. for 10, 30, 60 minutes.

FIG. 10 shows a plot of normalized remanent polarization, 2Pr / [2Pr (before annealing)], measured at 3 volts, as a function of hydrogen annealing time at a temperature of 200 ° C. Nb annealed for 10 minutes ≧
For the 0.56 sample, the 2Pr value was reduced by about 45%.
This reduction was greater in the samples with Nb = 0 or in the samples annealed for a longer time. For example, the decrease in remanent polarization was about 60% for the Nb = 0 sample annealed for 10 minutes. Nearly complete degradation occurred in all samples annealed for 30 or 60 minutes.

FIG. 11 shows a graph plotting the normalized coercive field, E _C / E _C (before annealing), measured at 3 volts as a function of hydrogen annealing time at a temperature of 200 ° C. This graph, the presence of niobium in the ferroelectric precursor have shown that to prevent the lowering of E _C value.

FIG. 12 is a graph plotting leakage current measured at 1 volt as a function of hydrogen anneal time in capacitors formed from precursors of different Nb / Ta ratios.

The leakage current when Nb = 0 and Nb = 0.56 was about 10 ^-7 A / cm ² . This value is fully applicable to many circuits. The leakage current of capacitors with Nb ≧ 1.0 is too high for most applications.

Comparing the various data, the best precursor Nb concentration for maximizing the electrical properties of the strontium bismuth tantalum niobate capacitor is Nb = 0.56, where Ta = 1.44.
This corresponds to a Nb / Ta molar ratio of about 0.4.

Example 4 The effect of adding excess bismuth to a standard strontium bismuth tantalum niobate ferroelectric precursor solution was investigated. Strontium bismuth tantalum niobate capacitors containing bismuth added in excess of the standard formula were prepared using the same strontium bismuth tantalum niobate solution and the procedure in Example 1. . Otherwise, a 0.5 mol / l solution of Bi-ethylhexanoic acid in ortho-xylene was prepared, and bismuth was added to a strontium-bismuth-tantalum-niobate-precursor solution and used. Table 2 shows the stoichiometry of each precursor solution.

[0133]

[Table 2] The condenser was placed in a hydrogen atmosphere of H ₂ -N ₂ (H ₂ 1%) at a temperature of 200 ° C. for 10 minutes, 30 minutes and 60 minutes.
Was exposed. The remanent polarization, coercive electric field, and IV measurement
For each experimental condition, three capacitors were run. FIG. 13 shows a plot of normalized remanent polarization at 5 volts, 2Pr / [2Pr (pre-anneal)] as a function of hydrogen anneal time at a temperature of 200 ° C. for each varied bismuth concentration. Show.

FIG. 14 plots the normalized coercive field Ec / [Ec (before annealing)] at 5 volts as a function of hydrogen annealing time at a temperature of 200 ° C. for each varied bismuth concentration. The graph is shown. Bi added
Prevents a decrease in performance of 2Pr. The added Bi is
In a relatively small range, the coercive electric field is increased.
Data annealed with hydrogen for 60 minutes are not shown. This is because they are very leaky and no hysteresis curve can be obtained.

The current-voltage (IV) characteristics, ie Bi = 2.18 and 2.58 annealed in hydrogen for 10 minutes
Graphs of applied voltage (volts) versus current density (amps per centimeter) for the samples of FIG.

A graph corresponding to the data for Bi = 2.18 annealed for 30 minutes is shown in FIG. Data for the capacitor sample with Bi = 2.58 annealed for 30 minutes is not plotted due to the short.

FIGS. 15 and 16 show that Bi added beyond the standard formula improves the leakage current of the sample for 10 minutes. In contrast, Bi annealed for 30 minutes
The high current measured in the sample with = 2.58 indicates that the added bismuth makes the leakage current increase due to hydrogen more severe.

This data shows two things.
First, it is advantageous to have an excess of bismuth in the precursor from which the ferroelectric was formed. However, if the integrated circuit requires a hydrogen anneal for a significant period of time, such as 10 minutes or more, excess bismuth may have a negative effect on leakage current. If long annealing times are required, other steps included in the present invention should be applied instead of using excess bismuth. For example, forming a hydrogen barrier layer, or
A step of performing an oxygen recovery anneal may be applied.

Second, the formula SrBi _2.58 Ta _1.44 Nb _0.56
It is clear that the final strontium bismuth tantalum niobate from the precursor having the element ratio represented by O ₉ must contain an excess of bismuth. This is because this excess amount of bismuth cannot be dispersed during the manufacturing process. This means
The same is almost true for precursors having an element ratio represented by the formula SrBi _2.38 Ta _1.44 Nb _0.56 O ₉ . Thus, these results indicate that excess metal in the final film (rather than just a precursor) is a desirable feature, depending on the particular conditions of the manufacturing process.

Example 5 The effect of adding excess niobium to a standard strontium / bismuth / tantalum / niobate / ferroelectric / precursor solution was investigated. The condenser was made from a strontium bismuth tantalum niobate solution commercially available from Hughes Aircraft Company. The standard solution contained the chemical precursor at the stoichiometric ratio expressed by the formula SrBi _2.18 Ta _1.44 Nb _0.56 O ₉ . In this example,
The 0.2 mol / l solution is tantalum 2-ethylhexanoic acid, bismuth 2-ethylhexanoic acid, strontium 2
-Ethylhexanoic acid, niobium 2-ethylhexanoic acid, 2
-Contains ethylhexanoic acid and xylene.

A strontium bismuth tantalum niobate capacitor was prepared according to the procedure of Example 1. Otherwise, a 0.04 mol / l solution of Nb-ethylhexanoic acid in ortho-xylene was prepared and used to add excess niobium to the ferroelectric precursor. Table 3 shows the composition of the precursor.

[0142]

[Table 3] The capacitor was annealed in hydrogen under the same conditions as in Example 4. Measurements were performed on the capacitors for each experimental condition. 5 for hydrogen annealing time
The remanent polarization (2Pr) and coercive electric field (Ec) at V are shown in FIG.
8 and FIG. 19, respectively.

FIG. 18 shows the normalized remanent polarization at 5 volts, 2Pr / [2Pr (prior to annealing)] of a capacitor formed from a precursor having varied niobium concentrations at a temperature of 200 ° C. 4 shows a graph plotted as a function of hydrogen anneal time.

FIG. 19 is a graph plotting normalized coercive field Ec / [Ec (before annealing)] at 5 volts as a function of hydrogen anneal time at a temperature of 200 ° C. at each varied niobium concentration. Is shown. The excess Nb is
Prevents a decrease in performance of 2Pr. That is, the greater the amount of Nb, the less the performance degradation indicated by remanent polarization. For Nb = 0.66, the remanent polarization is
During the short annealing time, it actually increases slightly.
Similarly, FIG. 19 shows that excess niobium prevents the coercive field value from decreasing. The final solid strontium bismuth tantalum niobate thin film must contain an excess of niobium, since niobium does not form non-volatile gases that escape during manufacturing. This indicates that it is desirable to include other metals in excess in addition to bismuth. In particular, it is clear that including an excessive amount of the B-site element is particularly effective in preventing a decrease in electrical characteristics in a layered superlattice material based on exposure of hydrogen.

The IV characteristics of the samples annealed for 10 minutes and 20 minutes when Nb = 0.56 and 0.66 are shown in FIGS. Three capacitors were measured for each experimental condition.

FIG. 20 shows that after a hydrogen annealing time of 10 minutes at a temperature of 200 ° C., a standard amount of niobium (precursor Nb
² shows a graph of applied voltage (volts) versus current density (A / cm ² ) for a strontium bismuth tantalum niobate capacitor having (= 0.56).
This graph shows that leakage currents in the range of 3-5 volts may be too high for many applications.

FIG. 21 shows that after a hydrogen annealing time of 10 minutes at a temperature of 200 ° C., the niobium content was reduced to the precursor Nb.
4 shows a graph of applied voltage (volts) versus current density (A / cm ² ) for a strontium bismuth tantalum niobate capacitor corresponding to = 0.56.
Leakage current in the range of 3-5 volts is about 10 ^-7 / cm ²
And is satisfactory for many applications. 20 and 21
The comparison of the graphs in Figure 2 shows that increasing the niobium concentration in the layered superlattice compound protects the layered superlattice compound with respect to current density during short hydrogen anneal times.

FIG. 22 shows the applied voltage (volts) versus current density (A) in a strontium bismuth tantalum niobate capacitor having a standard amount of niobium at a temperature of 200 ° C. and a hydrogen anneal time of 30 minutes. / C
m ² ) is shown.

FIG. 23 shows that after a hydrogen annealing time of 30 minutes at a temperature of 200 ° C., the niobium content of the precursor Nb =
4 shows a graph of applied voltage (volts) versus current density (A / cm ² ) for a strontium bismuth tantalum niobate capacitor corresponding to 0.66. FIG.
23 and FIG. 23 show that excess hydrogen does not protect the layered superlattice compound with respect to current density when the hydrogen anneal time is 30 minutes or longer. In short, leakage current is reduced in samples with added Nb annealed for 10 minutes. However, the annealing time is 3
At 0 minutes, the added Nb shows no substantial difference in leakage current compared to the standard formula.

Examples 4 and 5 show that added Bi or Nb protects strontium, bismuth, tantalum, niobate and capacitors against performance degradation due to hydrogen annealing. These additional elements prevent performance degradation due to hydrogen by forming excess oxide and instead consuming hydrogen to reduce active strontium bismuth tantalum niobate oxide.

High leakage of capacitors annealed for a long time appears to be caused by extra oxide consumed by hydrogen. Excess oxides form elemental metals in ferroelectric capacitors in response to reduction by hydrogen annealing. Then, the conductive metal leaks
Act as a path. This means that the preferred manufacturing method does not add metal elements to form excess metal oxides that consume large amounts of hydrogen and is not enough to provide a leak path when it is reduced by hydrogen. It suggests.

Alternatively, an oxygen recovery anneal may be performed to form the insulator, as shown in Example 2 to oxidize the metal again and form the insulator. Preliminary results with other B-site materials, such as titanium, tantalum, hafnium, tungsten, and zirconium, indicate that excess amounts of other B-site materials can prevent performance degradation from exposure to hydrogen. Is shown.

Example 6 The effect of covering a platinum upper electrode of strontium, bismuth, tantalum, niobate and a capacitor with a hydrogen barrier made of titanium nitride was investigated. Strontium bismuth tantalum niobate capacitors were again prepared according to the procedure used in Example 1 from the precursor solution obtained from Hughes Aircraft Company, HAC10709-30. Then, a thin film of titanium nitride was sputter deposited on the strontium bismuth tantalum niobate capacitor at a thickness of 1800 ° under various deposition conditions and H ₂ at a flow rate of 4 l / m.
-N ₂ (H ₂ 5%) mixed atmosphere at a temperature of 400 ° C.
Annealed for 10, 30, 60 minutes. The condenser had an area of 7854 μm ² . The titanium nitride film is
Removed by a solution of NH ₄ OH: H ₂ O ₂ : H ₂ O (1: 3: 1) at a temperature of 60 ° C. After drying the condenser in a vacuum oven, hysteresis measurements and IV tests over the range of 1 to 10 volts were performed.

Titanium nitride was produced using a titanium nitride sputter target at a power of 25, 50 and 100 W with argon gas at a gas pressure of 5, 8, and 12 mTorr.
Deposited on the top electrode of the capacitor at a base pressure of 5 × 10 ⁻⁷ Torr.

The most effective titanium nitride to protect strontium, bismuth, tantalum, niobate and capacitors against performance degradation due to hydrogen is a film having a high density. That is, the film is 100 W and 5 mTorr.
Made in. These membranes have 4.19 grams per
Cubic centimeter (g / cm ³ ) density and approximately 0.50 milliohm centimeter (mΩc
m). In this case, the sides of the capacitor were not covered with the barrier layer.

The hysteresis curves of the samples obtained by sputtering titanium nitride at 100 W and 5 mTorr were measured before, after, and after hydrogen annealing at 10, 30, and 60 minutes.
The curves were almost equal before annealing and 60 minutes after annealing.

In the case of titanium nitride sputtered at 100 W and 5 mTorr, the remanent polarization (2Pr) in the capacitor was 5 volts and was 1 volt before and after hydrogen annealing.
Measurements were taken at 0, 30, and 60 minutes. All hydrogen (H
₂ ) The value of 2Pr in the annealed sample was reduced by 10% from the value before hydrogen (H ₂ ) treatment.

The leakage current of a capacitor in which titanium nitride was sputtered at 100 W and 5 mTorr was measured at 10 minutes, 30 minutes, and 60 minutes before and after hydrogen annealing.
Leakage current measured at 3 volts was approximately equal for all samples that underwent hydrogen annealing. Its value was only about 10 ^-6 A / cm ² . These results show the advantages of providing a titanium hydrogen nitride barrier in the method of the present invention. Also, the desirable electrical characteristics of the ferroelectric thin film against the performance degradation due to hydrogen are
It has also been demonstrated that the bottom and sides of the ferroelectric, while unnecessarily protected, are protected by depositing a hydrogen barrier layer vertically on the ferroelectric thin film.

In Example 1, the results showed that the lateral diffusion of hydrogen was relatively less important than the vertical diffusion. In most cases, the most important hydrogen barrier is the barrier layer deposited directly on the ferroelectric thin film, since the underlying layer of the ferroelectric layer is often thick enough to prevent diffusion of hydrogen into the ferroelectric .

"Directly above" means that in FIGS. 1 and 4,
It means that the barrier layer is present vertically on the ferroelectric layer and extends the ferroelectric layer in the horizontal direction. This expression does not mean that the barrier layer is in direct contact with the ferroelectric layer. The barrier layer may or may not be in contact with the ferroelectric layer. As long as the barrier layer is present directly on a portion of the ferroelectric layer, the barrier layer protects that portion from hydrogen diffusion.

On the other hand, it is clearly shown as a result that the ferroelectric characteristics cannot be completely protected only by the upper barrier layer. One possible approach for more complete protection is to take measures to protect the sides of the ferroelectric thin film against lateral diffusion.

As mentioned above, a feature of the present invention is that exposure to hydrogen is kept small. This includes setting the hydrogen heat treatment conditions at a temperature of 350 ° C. and a time of 30 minutes or less. In some integrated circuits, low temperatures with hydrogen,
Short processing times will be sufficient to get excellent results. However, in other cases, MOs with excellent electrical properties
Exposure to greater hydrogen may be necessary to obtain SFETs or for other reasons. Because it is longer time or higher temperature. In such cases, the superior ferroelectric properties can be attributed to excess bismuth oxide,
Alternatively, it can be obtained by using a precursor having excess metal oxide such as excess niobium oxide.

Alternatively, in other cases, the use of a hydrogen barrier during hydroprocessing, alone or in combination with the measures described above, is effective. In the case of the use of a hydrogen barrier, a barrier covering only those parts of the integrated circuit that are directly on the ferroelectric material forming part of the integrated circuit is effective. this is,
This is because lateral diffusion is less important than vertical diffusion. Furthermore, the addition of oxygen to an integrated circuit layer, such as an underlying insulating layer, following the fabrication of the ferroelectric layer is also effective alone or in combination with one or more of the above measures. . Here, the oxygen acts as a getter for hydrogen during the subsequent hydrogen treatment.

Thus, the present invention provides a process capable of preventing degradation of ferroelectric performance in combination with exposure to hydrogen necessary to create and complete other portions of an integrated circuit. Or provide the structure.

Methods have been described for fabricating ferroelectric integrated circuits that allow exposure to hydrogen and have excellent electrical properties. The specific embodiments shown in the drawings and described herein are illustrative and should not be construed as limiting the invention described in the following claims. For example, in the present invention, the layer 1 in FIGS.
22 and 422 may be formed from a layered superlattice material or an ABO ₃ type metal oxide.

Further, it will be apparent to those skilled in the art that many uses and modifications can be made from the described embodiments without departing from the spirit of the invention. For example, while low-temperature, short-time hydrogenation of integrated circuits has been identified as an important part of the process for fabricating ferroelectric memory devices, this method, as a variation on the described method, It can also be combined with other processes. Also, the steps described are exemplary and may be performed in a different order.

In addition, equivalent structures or processes may replace the various structures and processes described. As a result, the invention should be construed to include each novel feature or novel combination of features that are processed by a manufacturing process, an electronic device, or an electronic device manufacturing method.

[0168]

According to the present invention, it is possible to reduce the harmful effects of the hydrogen heat treatment and to maintain the excellent electrical characteristics of the ferroelectric element.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a portion of an integrated circuit made by the method of the present invention, illustrating a non-volatile ferroelectric memory cell.

FIG. 2 is a flowchart illustrating a preferred embodiment of a process for manufacturing a nonvolatile ferroelectric memory device according to the present invention.

FIG. 3 is an enlarged top view of a typical wafer having a thin film capacitor fabricated in accordance with the present invention formed thereon.

FIG. 4 is a portion of a cross-sectional view taken along line 4-4 of FIG. 3, illustrating a thin film capacitor device made in accordance with the present invention.

FIG. 5 is a graph showing remanent polarization 2Pr at 5 volts as a function of annealing time for capacitors annealed at temperatures of 200 ° C., 250 ° C., and 300 ° C.

FIG. 6 is a graph plotting data obtained by measuring remanent polarization in a capacitor having a surface area ranging from 1963 to 196300 μm ² .

FIG. 7 is a graph of the remanent polarization of strontium bismuth tantalum niobate capacitors when the Nb / Ta ratio of the precursor is changed.

FIG. 8 shows the coercive electric field E when the Nb / Ta ratio of the precursor is changed.
It is a graph of _C.

FIG. 9 is a graph of leakage current measured at 5 volts with varying precursor Nb / Ta ratios.

FIG. 10: Normalized remanent polarization, 2 measured at 3 volts as a function of hydrogen anneal time at a temperature of 200 ° C.
It is the graph which plotted Pr / [2Pr (before annealing)].

FIG. 11: Normalized coercive field, E _C , measured at 3 volts as a function of hydrogen anneal time at a temperature of 200 ° _C.
5 is a graph plotting / E _C (before annealing).

FIG. 12 is a graph plotting leakage current measured at 1 volt as a function of hydrogen anneal time for capacitors formed from precursors of different Nb / Ta ratios.

FIG. 13: 200 ° C. for each varied bismuth concentration
5 is a graph plotting normalized remanent polarization at 5 volts, 2Pr / [2Pr (before annealing)] as a function of hydrogen anneal time at a temperature of.

FIG. 14: 200 ° C. for each varied bismuth concentration
5 is a graph plotting normalized coercive field Ec / [Ec (before annealing)] at 5 volts as a function of hydrogen anneal time at a temperature of.

FIG. 15 shows current-voltage (IV) characteristics, ie, applied voltage (volts) versus current density (amps per centimeter) for Bi = 2.18 and 2.58 samples annealed in hydrogen for 10 minutes. Meter).

FIG. 16: Current-voltage (IV) characteristics, ie, applied voltage (volts) versus current density (amps per centimeter) for Bi = 2.18 and 2.58 samples annealed in hydrogen for 10 minutes. Meter).

FIG. 17: Current density (A / cm ² ) versus applied voltage (volts) in a strontium bismuth tantalum niobate capacitor with a standard amount of bismuth after a hydrogen annealing time of 30 minutes at 200 ° C. It is a graph of.

FIG. 18 shows normalized remanent polarization at 5 volts, 2Pr / [2Pr (prior to annealing)] of a capacitor formed from a precursor having varied niobium concentrations at 200 ° C.
5 is a graph plotted as a function of hydrogen anneal time at a given temperature.

FIG. 19 is a graph plotting normalized coercive electric field Ec / [Ec (before annealing)] at 5 volts as a function of hydrogen anneal time at a temperature of 200 ° C. at each varied niobium concentration.

FIG. 20 shows a standard amount of niobium (precursor Nb = 0.56) after a hydrogen annealing time of 10 minutes at a temperature of 200 ° C.
4 is a graph of applied voltage (volts) versus current density (A / cm ² ) for a strontium bismuth tantalum niobate capacitor having

FIG. 21 shows that after a hydrogen annealing time of 10 minutes at a temperature of 200 ° C., the applied voltage (in volts) on a strontium bismuth tantalum niobate capacitor whose niobium content corresponds to the precursor Nb = 0.56 4) is a graph of current density (A / cm ² ).

FIG. 22. Applied voltage (volts) versus current density (A / cm ² ) in a strontium bismuth tantalum niobate capacitor with a standard amount of niobium after a hydrogen anneal time of 30 minutes at a temperature of 200 ° C. ) Is a graph.

FIG. 23: Applied voltage (volts) on a strontium bismuth tantalum niobate capacitor whose niobium content corresponds to the precursor Nb = 0.66 after a hydrogen annealing time of 30 minutes at a temperature of 200 ° C. 3 shows a graph of current density (A / cm ² ).

[Explanation of symbols]

 Reference Signs List 104 silicon substrate 102 field oxide region 106 source region 108 drain region 112 gate insulating film 113 MOSFET 114 first interlayer insulating film 116 adhesive layer 118 ferroelectric thin film capacitor 120 lower electrode 122 ferroelectric thin film 124 upper electrode 126 hydrogen barrier layer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 21/8242 (72) Inventor Akira Furuya 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Invention Author Joseph Cuciaro United States of America, Colorado 80918, Colorado Springs, Rossmere Street 2545 (72) Inventor Carlos Arrogio United States of America, Colorado 80919, Colorado Springs, W.W. Sambar de Cliffs Lane 317

Claims (32)

[Claims] 1. A method of manufacturing a ferroelectric integrated circuit, comprising: forming an integrated circuit portion including a thin film made of a metal oxide material;
A method for manufacturing a ferroelectric integrated circuit, comprising performing heat treatment at a temperature of 50 ° C. or less. 2. The method according to claim 1, wherein the heat treatment step comprises:
A method for manufacturing a ferroelectric integrated circuit, wherein the method is performed in less than 30 minutes. 3. The method for manufacturing a ferroelectric integrated circuit according to claim 2, wherein said hydrogen is contained in said atmosphere at a volume fraction of 0.01% to 50%. 4. The ferroelectric integrated circuit according to claim 2, further comprising a step of forming a hydrogen barrier layer directly on at least a part of the metal oxide material before the heat treatment. Manufacturing method. 5. The method according to claim 4, wherein the hydrogen barrier layer is made of titanium nitride or silicon nitride. 6. The heat treatment according to claim 5, wherein
The method for manufacturing a ferroelectric integrated circuit, wherein the method is performed for a period of time equal to or less than minutes, and wherein a volume percentage of hydrogen in the hydrogen atmosphere is 0.01 to 50%. 7. The metal oxide material according to claim 1, wherein the metal oxide material has an oxide containing at least two metal elements, and at least one of the metal elements is present in an excess amount in the material. A method for manufacturing a ferroelectric integrated circuit. 8. The method according to claim 7, wherein the metal oxide material comprises a layered superlattice compound. 9. The method for manufacturing a ferroelectric integrated circuit according to claim 8, wherein the metal element present in an excess amount is one of niobium and bismuth. 10. The method for manufacturing a ferroelectric integrated circuit according to claim 9, wherein said layered superlattice compound comprises strontium bismuth tantalum niobate. 11. The method for manufacturing a ferroelectric integrated circuit according to claim 10, wherein said metal element present in an excess amount is niobium. 12. The method of claim 1, further comprising providing a substrate and a precursor liquid for the metal oxide material, depositing the precursor on the substrate, and treating it to form the metal oxide material. And wherein the metal oxide material comprises an oxide containing at least two metal elements, wherein one of the metals is present in an excess amount in the precursor. Manufacturing method of body integrated circuit. 13. The method for manufacturing a ferroelectric integrated circuit according to claim 12, wherein the metal present in an excess amount is a metal that does not form a nonvolatile compound dispersed in the manufacturing process. 14. The method according to claim 1, wherein:
Comprising a substrate and a precursor liquid for the metal oxide material, depositing the precursor on the substrate, treating the precursor to form the metal oxide material, further comprising: Strontium, bismuth, tantalum, niobium, wherein the precursor has the stoichiometric formula SrBi _2.18 Ta _2-x Nb _x
Chemical elements strontium, bismuth, tantalum having a relative molar ratio substantially corresponding to O ₉ (0 ≦ X ≦ 2);
A method for manufacturing a ferroelectric integrated circuit, comprising niobium. 15. The method according to claim 14, wherein the precursor is:
Beyond the stoichiometric amount represented by the formula SrBi _2.18 Ta _2-x Nb _X O ₉ (0 ≦ X ≦ 2), zero percent and 40
% Of bismuth in an excess amount between 0.1% and 2.0%. 16. The method according to claim 14, wherein the precursor is
A method of manufacturing a ferroelectric integrated circuit, comprising strontium, bismuth, tantalum, and niobium, which are elements substantially corresponding to the formula SrBi _2.18 Ta _2-x Nb _x O ₉ . 17. The method according to claim 16, wherein the precursor is
Ferroelectric integration characterized in that it contains niobium in a loading of between 0% and 40% in excess of the stoichiometric amount represented by the formula SrBi _2.18 Ta _2-x Nb _x O ₉ . Circuit manufacturing method. 18. The method according to claim 2, further comprising a step of performing an oxygen recovery annealing after the heat treatment step in an atmosphere containing hydrogen, wherein the oxygen recovery annealing is performed in a temperature range of 300 ° C. to 1000 ° C. , For 20 minutes to 2 hours. 19. A method of manufacturing a ferroelectric integrated circuit, comprising: forming an integrated circuit portion including a thin film made of a metal oxide material, wherein the integrated circuit portion is placed in an atmosphere containing hydrogen for a time of 30 minutes or less. And a method of manufacturing a ferroelectric integrated circuit. 20. The method according to claim 19, further comprising a step of performing an oxygen recovery annealing after the heat treatment step in an atmosphere containing hydrogen, wherein the oxygen recovery annealing is performed in a temperature range of 300 ° C. to 1000 ° C. , For 20 minutes to 2 hours. 21. The ferroelectric integrated circuit according to claim 19, further comprising a step of forming a hydrogen barrier layer directly on at least a part of the metal oxide material before the heat treatment. Manufacturing method. 22. The method according to claim 19, wherein the metal oxide material has an oxide containing at least two metal elements, and at least one of the metal elements is present in an excess amount in the material. A method for manufacturing a ferroelectric integrated circuit. 23. A method of manufacturing a ferroelectric integrated circuit including a metal oxide material, wherein the integrated circuit includes a thin film of the metal oxide material having a layered superlattice compound having an excess amount of a B-site element. Forming a portion, exposing a part of the integrated circuit to hydrogen, and completing the integrated circuit so as to include a thin film of the metal oxide material in a component of the integrated circuit. An integrated circuit manufacturing method. 24. The method of claim 23, further comprising the step of heat treating the integrated circuit portion while the integrated circuit is exposed to hydrogen. 25. The method for manufacturing a ferroelectric integrated circuit according to claim 23, further comprising a step of performing an oxygen recovery annealing after the step of exposing the integrated circuit portion to hydrogen. 26. The oxygen recovery anneal according to claim 25, wherein the oxygen recovery anneal is performed in a temperature range of 300 ° C. to 1000 ° C.
A method for manufacturing a ferroelectric integrated circuit, wherein the method is performed for a period from minutes to two hours. 27. The ferroelectric device according to claim 23, further comprising a step of forming a hydrogen barrier layer directly on at least a part of the metal oxide material before the step of exposing to hydrogen. Manufacturing method of body integrated circuit. 28. The method according to claim 27, wherein the hydrogen barrier layer comprises titanium nitride or silicon nitride. 29. The method for manufacturing a ferroelectric integrated circuit according to claim 23, wherein the layered superlattice compound comprises strontium bismuth tantalum niobate. 30. The method of manufacturing a ferroelectric integrated circuit according to claim 29, wherein the excess amount of the metal element is niobium. 31. The method according to claim 30, wherein the superlattice compound has an excessive amount of bismuth. 32. The method according to claim 23, wherein, in the forming step, a precursor liquid for the substrate and the metal oxide material is prepared, the precursor is attached to the substrate, and the precursor is deposited on the thin film of the metal oxide material. A method of manufacturing a ferroelectric integrated circuit, comprising a step of performing processing to form a ferroelectric integrated circuit.