JPH11307600A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dispense with redundancy wirings on a probe card. SOLUTION: Tester pins of 256 pieces are divided into 16 blocks of BLK1 to BLK16. Furthermore, a tester-pin specifying circuit 40 is provided in correspondence with each of the 16 blocks BLK1-BLK16, respectively. In each tester- pin specifying circuit 40, a DUT number register 42 and a block ID resgister 44 are provided. These DUT number registers 42 and ID registers 44 can be made rewritten, when many DUTs are taken out and measured, and the numbers are assigned to the blocks BLK1-BLK16 in the arbitrary sequence for each DUT. Thus, redundancy wirings on a probe card are dispensed with.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, and more particularly, to a device under test (hereinafter, referred to as a DUT).
nder test). The present invention relates to a semiconductor test apparatus capable of eliminating redundant wiring on a probe card and a performance board when a large number of devices are taken.

[0002]

2. Description of the Related Art FIG. 5 shows a configuration of a conventional general semiconductor test apparatus. As can be seen from FIG. 5, the semiconductor test apparatus includes a tester main body 80 and a test head 82. When a wafer test is performed, a performance board 84 is used.
, A ring 86 and a probe card 88 are used. The test head 82 transmits a signal to the performance board 84 and receives a signal transmitted to the performance board by a plurality of tester pins provided on the upper side based on the data generated by the tester main body 80. For example, 256 tester pins are provided. FIG. 6 is a plan view of the performance board 84 as viewed from above. As can be seen from FIG.
The performance board 84 has a donut shape with an opening formed in the center, and has a 25
Six pins 85 are provided.

As can be seen from FIG. 5, a plurality of pins are provided above and below a ring 86 to electrically connect a performance board 84 and a probe card 88.
FIG. 7 shows a probe card 8 when two DUTs are taken.
FIG. 8 is a plan view of the device 8 as viewed from above. As can be seen from FIG. 7, the probe card 88 also has a donut shape with an opening formed at the center. This probe card 88
On the inner peripheral side of the DU, the probe 90 is located at the opening.
It extends toward T. That is, as can be seen from FIG. 5, the semiconductor wafer W is positioned at the tip of the probe 90. When four DUTs are taken, the DUTs are taken out in an arrangement as shown in FIGS. 8A to 8C, and when eight DUTs are taken, the DUT is taken out of FIG.
It is taken out in an arrangement as shown in (a) to (c).

When a plurality of DUTs are measured simultaneously by the semiconductor test apparatus as described above, one tester pin is connected to one DUT.
It is divided for each UT. The number of tester pins allocated to one DUT is calculated by the total number of tester pins / the same measurement number. The tester pins assigned to each DUT are continuous pins starting from (total number of tester pins / same number) * n + 1 (n = 0, 1,..., Same number-1). For example, as can be seen from FIG. 6, the total number of tester pins is 256 pins,
When simultaneously measuring two DUTs, the first DUT is connected to pins 85 (1), 85 (2),... 85 (127), 85 (1).
28) are assigned to pins 85 (129), 85 (130),... 85 (25) to the second DUT.
5), 85 (256) tester pins are assigned.
Such a method of dividing the tester pins is determined by the system of the semiconductor test apparatus and cannot be changed by the user.

[0005] In such a fixed tester pin dividing method, there is a case where it is necessary to perform equal-length wiring depending on the arrangement of the DUT. This is noticeable in a wafer test. This isometric wiring will be described in detail with reference to FIG.

FIG. 10 is a plan view of the probe card 88 as viewed from above. Then, the case where the first DUT1 and the second DUT2 are measured simultaneously is shown.
The probe card 88 includes a first DUT 1 and a second DU 1
A probe 90 for probing to the wafer pad of T2 is provided. The probes 90 are arranged so as to surround the outer circumferences of the first DUT 1 and the second DUT 2 so as not to contact each other. Accordingly, the arrangement of the probes 90 in the probe card 88 for simultaneous measurement of two probes is, for example, as shown in FIG.

[0007] There are two chips, a first DUT1 and a second DUT2, and the tester pin assigned to pin 1 of the first DUT1 and the tester pin assigned to pin 1 of the second DUT2 are measured simultaneously. Sometimes the same behavior is expected. This arrangement is different from the arrangement of the pins 85 of the performance board 84 shown in FIG. Therefore, as can be seen from FIG. 10, when the probe card 88 and the performance board 84 are connected, the first DUT 1 and the second DU are
In some cases, the pin correspondence of T2 does not match. For this reason,
Wiring 92 for associating the pins of the first DUT1 with the pins of the second DUT2 on the probe card 88
Is required. For example, when focusing on one pin of the second DUT 2, the pin 89 (129) on the probe card 88
And a probe 90 for one pin of the second DUT 2 (19
3) must be connected by the wiring 92 (129).
Further, in this case, since the wiring lengths of the signal lines need to be equal lengths, it is necessary to provide equal length wiring lines 92 to all the signal lines in accordance with the longest wiring line 92.

The problem in providing the wiring 92 is as follows.
This is to create extra impedance in the measurement system by extending the wiring length and increasing the number of connection points. This makes the DUT
1. It becomes difficult to evaluate the original characteristics of the DUT 2, and this causes uncorrelation between boards or between DUTs due to the wiring 92. Furthermore, when investigating the cause of the occurrence of the decorrelation or the characteristic deterioration, it takes much time to specify the cause point. From the point of view of board management and operation, it takes time / cost to manufacture the board and the maintenance is complicated.

Next, a specific configuration for generating a pin address in the above-described semiconductor test apparatus will be described with reference to FIG. This FIG. 11 has 256 tester pins similarly to the above-mentioned prior art, and it is assumed that up to eight DUTs can be measured simultaneously.

As can be seen from FIG. 11, the tester main body 80 of the semiconductor test apparatus includes a tester CPU 100, a multi-piece register 110, and a tester pin designating circuit 120.
And are provided. One tester pin designating circuit 120 can specify 16 tester pins. Therefore, in order to specify 256 tester pins, the semiconductor test apparatus is provided with a total of 16 tester pin designating circuits 120. FIG. 11 shows only one of them. The tester pin designating circuit 120 includes a pin ID register 130, a bit compare 132, and a decoder 134. Here, since the number of pins of the DUT is 256, all the pins can be expressed and specified with 8 bits. Therefore, the tester CPU 100 determines which pin is specified by the 8-bit data.

First, the tester CPU 100 issues a pin address (8 bits) to be specified, and the upper 4 bits are input to the bit compare 132. The inputted upper 4 bits are compared with the pin ID register 130 by the bit compare 132. The pin ID register 130 stores a unique pin ID of each tester pin designating circuit 120. This bit compare 13
Since the comparison of the pin addresses is performed only in the upper 4 bits in the pin ID 2, the pin ID register 130 has 4 bits. The bit compare 132 receives 2-bit data (four patterns of 1, 2, 4, and 8 DUTs) indicating the number of pieces to be taken from the multi-piece register 110.
Further, the bit compare 132 includes a CPU Write
The e signal is also input. The CPU Write signal indicates whether the pin address paid out by the tester CPU 100 is to be written or read.
This is a 1-bit control signal for designating.

The bit compare 132 is connected to the tester CPU 1
The upper 4 bits of the pin address issued from 00,
When the 4-bit pin ID of the pin ID register 130 matches, an enable signal is output. This enable signal is input to the decoder 134, which enables the decoder 134. The decoder 134 has the lower 4 bits of the pin address issued from the tester CPU 100.
Bits have also been entered. The decoder 134 has 16 channels 140. Therefore, the decoder 13
4, only one channel 140 corresponding to the decoded value of the lower 4 bits of the pin address is selected. As a result, it becomes possible to write into the register corresponding to the pin address specified by the tester CPU 100.

Next, referring to FIG. 12, a description will be given of a state of pin designation at the time of multi-cavity picking. FIG. 12 shows a bit compare 132
FIG. 2 is a diagram showing an internal circuit configuration in FIG.

First, in the case of single-cavity, even if the data representing the multi-cavity number from the multi-cavity number register 110 is decoded by the decoder 142, the output of the decoder 142 is not affected. Therefore, the OR circuits 144, 14
The outputs from 6 are all "0". Therefore, C
An AND circuit 148 to which a PU Write signal is input;
The outputs of 150 and 152 are all "0". Also, 4
The XNOR circuits 154, 156, 158, and 160 compare the pin ID of the bit with the upper four bits of the pin address issued from the tester CPU 100. AND14
8, 150, 152, and XNOR circuits 156, 158,
The output from the circuit 160 is input to the OR circuits 162, 164, and 166. As described above, the AND circuit 148,
Since the outputs of 150 and 152 are "0", ORing with the outputs of XNOR circuits 156, 158 and 160 means that the outputs of XNOR circuits 156, 158 and 160 are input to AND circuit 168 as they are. become. That is, the pin ID and the upper four bits of the pin address are
By comparison, when all the bits match, an enable signal is output to the decoder 134, and only one of the 256 tester pins can be accessed.

When writing is performed by taking two pieces, "2DUT" of the decoder 142 is selected, and only the output of the OR circuit 144 becomes "1". Now, because it is writing,
The CPU Write signal is also “1”. Therefore, AN
Only the output of the D circuit 152 becomes "1". This is input to the OR circuit 166, and the output of the XNOR circuit 160 and the OR
However, the fact that "1" is given to the input of the OR circuit means that the OR circuit 16 does not depend on the output of the XNOR circuit 160.
The output of No. 6 is always "1". Therefore, the XNOR circuit 1
Of the four bits 54, 156, 158, and 160, the enable signal is output if the other three bits match, regardless of whether the one bit compared by the XNOR circuit 160 matches. Is done. in this case,
An enable signal is output from two of the 16 bit compare 132s. That is, since one bit is ignored, the same data is written to two of the 256 tester pins. That is, the same pin numbers of the first DUT 1 and the second DUT 2 are accessed. Thereby, data writing at the time of taking two pieces is performed.

If two bits are ignored, four bits can be written, and if three bits are ignored, eight bits can be written. Note that when reading pin data, the CPU Write
Since the signal becomes "0" which is a disable signal, simultaneous access of a plurality of tester pins cannot be performed.
This is because when tester pin data is read, the evaluation cannot be performed unless one tester pin to be read is specified.

[0017]

As can be seen from the above description, in the conventional semiconductor test apparatus, when a plurality of DUTs are to be measured at the same time, the pins 89 provided on the probe card 88 and the probe card 8 are also used.
In this case, it is necessary to provide a wiring 92 between the probe 90 and the probe 90. Further, the wiring 92 must have the same length as the other wirings 92 in accordance with the longest of the wirings 92, so that an unnecessary impedance is created. By creating an unnecessary impedance, it becomes difficult to evaluate the original characteristics of the DUT, and the wiring 92 causes a correlation between the boards or between the DUTs. Furthermore, when investigating the cause of the occurrence of the decorrelation or the characteristic deterioration, it takes much time to specify the cause point. From the point of view of board management and operation, it takes time / cost to manufacture the board and the maintenance is complicated.

The present invention has been made in view of the above problems, and has as its object to provide a semiconductor test apparatus capable of eliminating or minimizing redundant wiring provided on a probe card. For this, multiple DUTs
It is an object of the present invention to provide a semiconductor test apparatus capable of programmably changing the assignment of the tester pins when measuring simultaneously.

[0019]

In order to solve the above-mentioned problems, a semiconductor test apparatus according to the present invention is a semiconductor test apparatus capable of simultaneously measuring a plurality of devices under test. When performing the measurement, a tester CPU that controls the semiconductor test apparatus, and a number register that stores the number of the devices to be measured simultaneously and that can be rewritten through the tester CPU. Dividing the plurality of tester pins into a plurality of blocks, and providing tester pin designating circuits provided by the number of the plurality of blocks in order to designate tester pins in this block, wherein each of the tester pin designating circuits is An identification number for identifying a plurality of devices to be measured is stored, and this number is stored in the tester CP.
U, a device number register to be measured, a block ID register for assigning a number to the block in an arbitrary order via the tester CPU, and a pin address issued from the tester CPU. One or more high-order bits, the value of the multi-piece count register, the value of the device under test number register, and the value of the block ID register are input, and the one or more high-order bits and When the value of the block ID register matches, a bit compare that outputs an enable signal and a lower bit of the pin address that is not input to the bit compare are input to the decoder. When input, one channel is selected by selecting the channel corresponding to the lower bits. To specify the Tapin, and a decoder,
It is characterized by having.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the concept of an embodiment of the present invention will be described with reference to FIG. This FIG.
FIG. 3 is a plan view showing the probe card 10 when two Ts are taken.

As can be seen from FIG. 3, each DUT formed on a semiconductor wafer generally has a square shape. That is, the first DUT1 has sides a1, b1, c1,
The second DUT 2 includes four sides d2, d2, and d2, and the second DUT 2 also includes four sides d2, b2, c2, and d2. The pad 12 of the first DUT 1 and the second DU
The pad arrangement in the pad 14 of T2 is the same. That is, focusing on the first pad, the first pad 12 (1) of the first DUT 1 is located at the upper end of the side a1, and the first pad 12 (1) of the second DUT 2
4 (1) is located at the upper end of the side a2. In other words, the arrangement of the pads 12 on the side a1 of the first DUT 1 and the arrangement of the pads 1 on the side a2 of the second DUT 2
The arrangement of 4 is substantially the same. Similarly,
The arrangement of the pads 12 on the side b1 of the first DUT 1 and the arrangement of the pads 14 on the side b2 of the second DUT 2 are substantially the same. Side c of the first DUT1
The arrangement of the pads 12 in one part and the arrangement of the pads 14 in the side c2 part of the second DUT 2 are substantially the same. The arrangement of the pads 12 on the side d1 of the first DUT 1 and the arrangement of the pads 14 on the side d2 of the second DUT 2 are substantially the same. Therefore, the same signal needs to be applied to the pin 16 (1) and the pin 16 (193) formed on the probe card 10. That is, from the pin 16 (1) to the probe 18
A signal supplied to the pad 12 (1) of the first DUT 1 via (1) and the probe 18 (1) from the pin 16 (193).
93) through the pad 12 (193) of the second DUT2
Must be the same signal. This is the same for the other pins. Eventually, the pins 16 arranged in the blocks BL1 and BL4 are expected to perform the same operation, and the blocks BL2 and B
The pin 16 located at L3 is expected to perform the same operation. Therefore, the same signal is applied to the bads 16 (1) to 16 (64) arranged in the block BL1 and the pins 16 (193) to 16 (256) arranged in the block BL4, and arranged in the block BL2. Bad 16
If the same signal is applied to (65) to 16 (128) and the pins 16 (129) to 16 (192) arranged in the block BL3, it is not necessary to provide redundant wiring as in the related art. In the above description, it is assumed that two DUTs are taken. However, this idea can be applied to four or eight DUTs.

Next, an embodiment of the present invention that specifically realizes the above-described concept will be described. The semiconductor test apparatus according to the present embodiment has 256 tester pins, and takes one, two, four, and eight DUTs.
It is a device that can be used by switching between individual pieces.

FIG. 1 is a block diagram for a pin address generation circuit according to an embodiment of the present invention, and FIG.
FIG. 2 is a diagram specifically illustrating an example of a circuit configuration inside a bit compare in FIG. 1.

As can be seen from FIG. 1, the tester main body of the semiconductor test apparatus is provided with a tester CPU 20, a multiple number register 30, and a tester pin designating circuit 40. With one tester pin designating circuit 40,
Sixteen tester pins can be specified. Therefore, in order to specify 256 tester pins, this semiconductor test apparatus is provided with a total of 16 tester pin designating circuits 40. Each of the 16 tester pin designating circuits 40 includes a block BLK1 shown in FIG.
It is provided corresponding to BLK16. That is, one tester pin designating circuit 40 is provided for one block. FIG. 1 shows only one of them. Multi-unit register 30 is a tester CPU
It is configured to be rewritable by a program through the interface 20.

The tester pin designating circuit 40 includes a DUT number register 42, a block ID register 44, a bit compare 46, and a decoder 48. Here, since the number of pins of the DUT is 256,
With 8 bits, all pins can be represented and specified. Therefore, the tester CPU 20 determines which pin is specified by the 8-bit data. The DUT number register 42 and the block ID register 44 are configured so that their stored values can be rewritten by a program via the tester CPU 20. In the present embodiment, it is assumed that eight DUTs are taken at the maximum, so that the DUT number register 42 needs only three bits. FIG.
As can be seen from the figure, the probe card 1
0 is divided into a total of 16 blocks BLK1 to BLK16. Therefore, in the present embodiment, it is necessary to prepare 16 blocks, and therefore, the block ID register 44 requires 4 bits. It should be noted that the blocks BLK1 to BLK16 in FIG. 4 are not divided into eight blocks but are fixed in 16 divisions. That is, for example, in the case of taking two blocks, the blocks BLK1 to BLK4 are continuously
May be assigned to the sides a1 and b1 of the DUT1 (see FIG. 3). Which DUT these blocks BLK1 to BLK16 are assigned to is assigned to the DUT number register 42 in advance, and the order in which the blocks are assigned to each DUT is programmed to the block ID register 44 in advance. .

Next, the operation of the block circuit shown in FIG. 1 will be described. First, the tester CPU 20 pays out the specified pin address (8 bits), and the upper 4 bits are input to the bit compare 46. The input upper 4 bits are compared with the values of the DUT number register 42 and the block ID register 44. Block ID register 44
Stores any one of the IDs of the blocks BLK1 to BLK16 shown in FIG. Further, the bit compare 46 receives 2-bit data (four patterns of 1, 2, 4, and 8 DUTs) indicating the number of pieces to be taken from the multi-piece register 30. Further, a CPU Write signal is also input to the bit compare 46. This C
The PU Write signal is a 1-bit write / read control signal for specifying whether to write or read the pin address issued by the tester CPU 20.

The bit compare 46 is connected to the tester CPU 20
When the pin address of the upper 4 bits paid out from the ID matches the contents of the 4 bits of the block ID register 44, an enable signal is output. This enable signal is input to the decoder 48, which enables the decoder 48. The decoder 48 includes a tester CPU 20
Also, the lower 4 bits of the pin address issued from are also input. The decoder 48 has 16 channels 49. Therefore, in the decoder 48, only one channel 49 corresponding to the decoded value of the lower 4 bits of the pin address is designated. As a result, it becomes possible to write into the register corresponding to the pin address specified by the tester CPU 20.

Next, with reference to FIG. 2, an example of a circuit configuration for programmably changing the pin assignment of the semiconductor test apparatus in a case where up to eight simultaneous measurements are considered with 256 tester pins will be described.

As can be seen from FIG. 2, the bit compare 46 in this embodiment is different from the bit compare 132 shown in FIG.
52 and 54 and a comparison register 56 are provided. These selector circuits 50, 52, 54 are provided with a decoder 5 according to the value of the multi-piece register 30.
The selection signal is input via the OR 8 and the OR circuits 60 and 62. The selector circuits 50, 52, and 54 have the lower 3 bits in the block ID register 44 and the DUT
Three bits of the number register 42 are input.
When the selection signal is "0", the selector circuits 50, 52, and 54 output the input from the block ID register 44 as it is, and when the selection signal is "1", the selector circuits 50, 52, and 54 output D.
The input from the UT number register 42 is output as it is. The outputs of these selector circuits 50, 52, 54 are 4
The data is input to a comparison register 56 for storing bit data. The output from the comparison register 56 is X
The signals are input to the NOR circuits 64, 66, 68, and 70. In addition, these XNOR circuits 64, 66, 68, 70 include:
A 4-bit signal from the DUT number register 42 is also input.

The outputs of the OR circuits 60 and 62 are also input to AND circuits 71 and 72,
The output of T is also input to the AND circuit 73. These A
The ND circuits 71, 72, and 73 also receive a CPU Write signal from the tester CPU 20. The outputs of the AND circuits 71, 72, and 73 are output to the OR circuit 7
4, 75 and 76 are input. The OR circuits 74, 7
Outputs from the XNOR circuits 64, 66, and 68 are also input to 5, 76, respectively. The outputs of the OR circuits 74, 75, and 76 and the output of the XNOR circuit 70 are input to an AND circuit 77. Then, an enable signal is output from the AND circuit 77 to the decoder 48.

In such a bit compare 46,
When one DUT is taken and writing is performed, the following operation is performed. Now, the multi-piece number register 30 is "00", and the outputs from the decoder 58 are all "0". Therefore, the selection signals of the selector circuits 50, 52, and 54 are all "0", and these selector circuits 5
Each of 0, 52 and 54 is in a state of selecting and outputting the signal of the block ID register 44. That is, the contents of the block ID register 44 are stored in the comparison register 56 as they are. It is also assumed that this is a write command, and therefore the CPU Write signal is "1". However, since the selection signals are all “0”, A
The outputs of the ND circuits 71, 72, 73 are all "0", and none of the bit masks of the OR circuits 74, 75, 76 function. Therefore, the XNOR circuits 64, 66,
68, 70, the comparison register 56 and the tester CP
The upper 4 bits of the pin address from U20 are compared. If the values of both bits match, these X
"1" is output from the NOR circuits 64, 66, 68, and 70. Therefore, if all four bits match, A
An enable signal is output from ND circuit 77. That is, the enable signal is output from the bit compare 46 assigned to any one of the blocks BLK1 to BLK16 in FIG. As for the block to which the enable signal has been output, the lower 4 bits are decoded by the decoder 48 as shown in FIG.
Any one of the channels 49 is selected.
That is, one of the 256 tester pins
A book is selected.

Next, a case where two DUTs are taken and writing is performed will be described. In this case, the multi-piece number register 30
Stores “01”. Therefore, the decoder 5
At 8, the output of the 2DUT becomes "1". Then, only the output of the OR circuit 62 becomes “1”, so that the selector circuit 5
The input of the selection signal to 0, 52, 54 is respectively "
0 "," 0 ", and" 1 ", that is, the selector circuit 5
0 and 52 are in a state of selecting and outputting the value from the block ID register 44, and the selector circuit 54 is in a state of selecting and outputting the value from the DUT number register 42. These outputs are stored in the comparison register 56.
Further, the output of the OR circuit 62 is “1”, and since writing is assumed, the CPU Write signal is also “1”.
It is. Therefore, the output of the AND circuit 71 becomes "1", and the output of the OR circuit 74 also becomes "1". This means
This means that the output of the OR circuit 74 is always "1" regardless of the value of the least significant bit 56 (1) of the comparison register 56. Therefore, from the AND circuit 77,
Upper 3 bits 56 (2) to 56 of comparison register 56
If (4) matches the upper 3 bits of the pin address from the tester CPU, an enable signal is output. Accordingly, the enable signal is output from two of the 16 bit compare 46 provided in the entire semiconductor test apparatus. This means that two blocks among the blocks BLK1 to BLK16 are selected in FIG. In other words, masking the DUT number means that pin data is simultaneously written to tester pins having the same block ID and the same number. Moreover, the selected block can be programmably changed by rewriting the contents of the block ID register shown in FIG. Then, the lower 4 bits of the pin address are decoded by the decoder 48 in FIG. 1, and one of the 16 channels 49 is selected. This means that 256
This means that two of the tester pins are selected.

The case of writing data into the DUT by taking four or eight pieces of data can be considered in the same manner as described above. That is, as can be seen from FIG. 2, in the case of four-cavity, "10" is stored in the multiple-cavity number register 30, and the output of the 4DUT in the decoder 58 becomes "1". Therefore, the OR circuits 74 and 75 are masked, and the outputs of the OR circuits 74 and 75 become "1" regardless of the values of the lower two bits 56 (1) and 56 (2) in the comparison register 56. Therefore, the upper 2 bits 56 of the comparison register 56
If (3), 56 (4) and the upper two bits of the pin address from the tester CPU 20 match, an enable signal is output. That is, the block BLK in FIG.
Four blocks are selected from 1 to BLK16, and thus four out of 256 tester pins are selected.

On the other hand, as can be seen from FIG. 2, in the case of eight pieces, "11" is stored in the multiple number register 30 and the output of the 8DUT in the decoder 58 becomes "1". Therefore, the OR circuits 74, 75, and 76 are masked, and the lower three bits 56 in the comparison register 56 are masked.
Regardless of the value of (1), 56 (2), 56 (3), OR
The outputs of the circuits 74, 75 and 76 are "1". Therefore, the most significant bit 56 (4) of the comparison register 56,
If the most significant bit of the pin address from the tester CPU 20 matches, an Enable signal is output. That is, eight blocks are selected from blocks BLK1 to BLK16 in FIG. 4, and thus, eight of the 256 tester pins are selected.

In either case of taking four or eight pieces, the block ID register 44 is programmable and rewritable. Therefore, block B in FIG.
Any order can be assigned to the LK1 to BLK16 in block units for each DUT.

Next, the operation in the case of reading will be described.
When reading data from a DUT, it is necessary to specify and access only one DUT, even if two, four, or eight pieces are taken when writing data to the DUT. is there. This is because when data of a plurality of DUTs is read, the data collides, and it is not possible to make an appropriate determination on the data. Therefore, FIG.
As you can see, when reading data, the CPU
By setting the Write signal to “0”, the OR circuit 7
All 4, 75, 76 bit masks are disabled. For example, in the case of two pieces, the comparison register 5
6, the DUT number is stored in the least significant bit 56 (1). If the 4 bits of the comparison register 56 do not match the upper 4 bits of the pin address, the decoder 4
8, no enable signal is output. That is, only one of the 16 blocks BLK1 to BLK16 shown in FIG. 4 is selected. Therefore, only one of the 256 tester pins is selected. This is the same in the case of taking four or eight pieces. In any case, only one tester pin is selected. As described above, when the pin data is read by combining the value of the DUT number register 42 and the value of the block ID register 44, the DUT can be specified.

As described above, in the present embodiment, the user operates the block B by dividing the 256 pins into 16 blocks.
DUT number register 42 for LK1 to BLK16
Specify the DUT number by using the block ID register 4
4 specifies the block ID. For example,
When taking two DUTs, the DUT number register 42
Specifies 1 or 2, and the block ID register 44
The block numbers from 1 to 8 are sequentially specified for both UT1 and UT2. Since this designation can be performed in a programmable manner, the user can assign DUT pins for each block of the blocks BLK1 to BLK16, and can realize the arrangement of the tester pins of the probe card 10 corresponding to the arrangement. For this reason, redundant wiring on the probe card 10 which was conventionally required can be eliminated.

By eliminating such redundant wiring,
By increasing the wiring length and increasing the number of connection points, it is possible to avoid creating an extra impedance in the measurement system, whereby the original characteristics of the DUT can be evaluated. In addition, it is possible to avoid the occurrence of uncorrelation between boards or DUTs due to the redundant wiring, and when investigating the cause of uncorrelation or the cause of characteristic deterioration, it is necessary to easily identify the cause of the cause. Can be. In addition, since there is no redundant wiring, maintenance becomes easy.

The present invention is not limited to the above embodiment, but can be variously modified. For example, 25 tester pins
It is not necessary that the number be six, but may be 512, 1024, or the like. Also, the number of multi-cavities is 2
The number is not limited to eight, but may be 16 or 32. However, for example, in the case of 16 pieces, the tester pin is divided into 32 blocks, so that the block ID register 44 requires 5 bits.
Bit is input. That is, the number of bits of the block ID register 44 and the number of bits of the pin address input to the bit compare 46 from the tester CPU 20 need to match.

[0040]

According to the semiconductor test apparatus of the present invention,
When measuring a large number of devices under test, a plurality of tester pins are divided into a plurality of blocks, and an arbitrary continuous number can be assigned to each of the plurality of blocks for each device under test. The pin arrangement of the tester of the semiconductor test apparatus and the pin arrangement of the device under test can be matched, and redundant wiring required on the probe card and the performance board can be eliminated or minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a pin address generation circuit of a semiconductor test device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a circuit configuration inside a bit compare in FIG. 1;

FIG. 3 is a diagram illustrating a method of dividing a plurality of tester pins into a plurality of blocks according to the present invention.

FIG. 4 is a diagram showing a case where a tester pin on a probe card is divided into 16 blocks.

FIG. 5 is a view for explaining the overall configuration of a wafer test by a general semiconductor test apparatus.

FIG. 6 is a plan view of the performance board as viewed from above.

FIG. 7 is a plan view of the probe card as viewed from above.

FIG. 8 is a diagram showing an arrangement of DUTs when four chips are taken.

FIG. 9 is a diagram showing an arrangement of DUTs when eight pieces are taken.

FIG. 10 is a plan view of a probe card provided with redundant wiring as viewed from above.

FIG. 11 is a block diagram of a pin address generation circuit in a conventional semiconductor test device.

FIG. 12 is a diagram showing an example of a circuit configuration inside a bit compare in FIG. 11;

[Explanation of symbols]

 Reference Signs List 10 probe card 20 tester CPU 30 multi-piece register 40 tester pin designating circuit 42 DUT number register 44 block ID register 46 bit compare 48 decoder 49 channel

Claims (3)

[Claims] 1. A semiconductor test apparatus capable of simultaneously measuring a plurality of devices under test, comprising: a tester CPU that controls the semiconductor test device when measuring the device under test; The number of devices to be measured is stored, and the number is rewritable via the tester CPU. A multi-count register and a plurality of tester pins are divided into a plurality of blocks, and the tester pins in this block are designated. And a tester pin designating circuit provided by the number of the plurality of blocks, wherein each of the tester pin designating circuits stores an identification number for identifying the plurality of devices to be measured, and this number is A device number register under test, which can be rewritten via the tester CPU; A block ID register for allocating numbers in an arbitrary order via the CPU, one or more upper bits of a pin address issued from the tester CPU, a value of the multi-piece register, and The value of the measurement device number register and the value of the block ID register are input, and if the one or more upper bits match the value of the block ID register, a bit compare that outputs an enable signal A decoder to which a lower bit of the pin address not input to the bit compare is input, and when the enable signal is input, a channel corresponding to the lower bit is selected, A semiconductor test apparatus comprising: a decoder that specifies a tester pin of a book; 2. A write / read control signal from the tester CPU is input to each of the tester pin designating circuits. If the write / read control signal is in a read mode, a device number to be measured is set arbitrarily. The semiconductor test apparatus according to claim 1, wherein a signal is read from only the tester pin of the one device under test for which the signal is specified. 3. The number of bits of the block ID register,
3. The semiconductor test apparatus according to claim 1, wherein the number of bits of the pin address input to the bit compare matches.