JPH11306791A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the product yield of a dynamic RAM or the like provided with many banks which can perform the selection operation of word lines independently of each other. SOLUTION: In a multibank-type dynamic RAM or the like which is provided with 16 banks BANKO to BANKF which can perform the selection operation of word lines independently of each other, one redundant bank BANKR, an X-system redundant circuit ARU and a Y-system redundant circuit TRU are installed, and power-supply routes which supply an operating power supply to the respective banks are installed independently in the respective banks. For example, when a DC characteristic defect (in a part A) is generated in the bank BANK1, the power-supply route of the bank BANK1 is cut so as to be changed over to the power-supply routes of the X-system redundant circuit XRU, the Y-system redundant circuit YRU and the redundant bank BANKR, and the access impossibility of all the banks is relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a dynamic memory device having a large number of banks.
The present invention relates to an AM (random access memory) or the like and a technique particularly effective for improving the product yield.

[0002]

2. Description of the Related Art A dynamic RAM or the like whose basic components are a memory array including word lines and bit lines arranged orthogonally and dynamic memory cells arranged in a grid at the intersections of these word lines and bit lines. Semiconductor storage device. Further, a predetermined number of redundant word lines and redundant bit lines are provided in a memory array such as a dynamic RAM, and these redundant word lines and redundant bit lines are selectively used as a word line or a bit line in which a failure is detected. A so-called defect remedy method that enhances the product yield of a dynamic RAM or the like by replacing it is known.

On the other hand, in recent years, the technology for miniaturization and high integration of semiconductor integrated circuits has been remarkably advanced, and dynamic RAMs and the like have also benefited from them, and are increasing in capacity and scale. Under such circumstances, a so-called multi-bank approach, in which a memory array and peripheral circuits are divided into a large number of banks and accessed in parallel, is becoming common as one means for promoting a high-speed dynamic RAM or the like. 1
A dynamic RAM having a relatively large number of banks such as six or more is being commercialized. In a multi-bank type dynamic RAM, each bank includes a row address decoder that holds a row address for selecting a word line and decodes and selectively sets a designated word line to a selected state. As a result, in each bank of the dynamic RAM, the word line selecting operation is performed independently, and the word lines to which different row addresses are assigned are simultaneously selected.

[0004]

Prior to the present invention, the present inventors engaged in the development of the above-described multi-bank type dynamic RAM, and noticed the following problems. That is, as shown in FIG. 8, the dynamic RAM includes, for example, 16 banks BANK0 to BANKF, each of which includes a memory array AR including a predetermined number of redundant word lines and a predetermined number of redundant bit lines.
YU0-ARYUF and ARYL0-ARYLF
And a pair of sense amplifiers SAU0 to SAUH and SAL0 to SALH provided on both sides of each memory array.

At the left end of the banks BANK0 to BANKF, common column address decoders CDU and CDL for bit line selection are provided, respectively, and memory arrays ARYU0 to ARYUF and ARYL0 to ARYL are provided.
Inside F, row address decoders RDU and RDL for selecting a word line are provided. The column address decoders CDU and CDL include Y-system redundant circuits YRU and YRL for selecting redundant bit lines, respectively.
Row address decoders RDU and RDL include X-system redundant circuits XRU and XRL for selecting a redundant word line, and
Row address decoder RBKD and column bank address decoder CBKD for bank selection
And respectively.

The row address decoders RBKD of the row address decoders RDU and RDL include a row bank cycle signal RCYCB which is selectively brought to a low level in a row cycle from the interface circuit IF, and a 4-bit row bank address signal RBKA0 to RBKA3.
And are commonly supplied. The column bank address decoder CBKD has a column bank cycle signal CCYC which is selectively set to a low level during a column cycle.
B and a 4-bit column bank address signal CB
KA0 to CBKA3 are commonly supplied.

As a result, the banks BANK0 to BANK
F is designated alternately according to the row bank address signals RBKA0 to RBKA3 when the dynamic RAM is set to the row cycle and the row bank cycle signal RCYCB is set to the low level, and the dynamic RAM is set to the column cycle and the column bank cycle signal is set. CCYCB
Is set to the low level, it is alternatively designated according to the column bank address signals CBKA0 to CBKA3. The word lines and bit lines in which an abnormality of the banks BANK0 to BANKF are detected are selectively connected to the redundant word lines or redundant bit lines in each bank by the X-system redundant circuit XRU or XRL or the Y-system redundant circuit YRU or YRL. Replaced and rescued.

[0008] However, the defect relief using the redundant word line and the redundant bit line can cope with a relatively small-scale failure using the word line or the bit line as a unit. However, it is not possible to cope with the poor DC characteristics and the like, and it cannot be remedied. This becomes a serious problem as the technology of miniaturization and high integration of the semiconductor integrated circuit advances and the number of banks of the dynamic RAM and the like advances, and the product yield of the dynamic RAM and the like decreases.

An object of the present invention is to increase the yield of products such as a dynamic RAM having a large number of banks capable of independently performing a word line selecting operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0011]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a predetermined number of redundant banks and a defective bank having a block failure due to a DC characteristic failure or the like are added to a redundant bank of a multi-bank type dynamic RAM or the like having a large number of banks capable of independently performing a word line selecting operation. A row cycle bank redundancy circuit and a column cycle bank redundancy circuit for selectively replacing any one of the above, and a power supply path for supplying operating power to each bank is provided independently for each bank. When the DC characteristics of the bank become poor, the corresponding power supply path is cut off. When banks arranged adjacent to each other, such as a dynamic RAM, share a sense amplifier arranged in the middle, for example, two redundant banks are provided as a pair, and are assigned to one of these redundant banks. The two redundant banks are selectively activated by comparing and comparing the rescue bank address and the address obtained by adding or subtracting 1 to a bank address supplied from the outside at the time of access.

According to the above-described means, it is possible to cope with block failures such as DC characteristic failures, which are likely to occur as the number of banks of a dynamic RAM or the like is increased with the advancement of the technology for miniaturization and high integration of semiconductor integrated circuits. It is possible to replace such a bank having a block defect with a redundant bank relatively easily and at high speed and to repair it, so that the product yield of a multi-bank type dynamic RAM or the like can be improved. Further, when banks arranged adjacent to each other such as a dynamic RAM share a sense amplifier arranged in the middle, banks on both sides sharing the sense amplifier become inaccessible at the same time due to, for example, poor DC characteristics of the sense amplifier. The case can be easily coped with, and the product yield of a dynamic RAM or the like can be further increased.

[0013]

FIG. 1 is a block diagram showing a dynamic RAM (semiconductor memory device) according to a first embodiment of the present invention. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. Although the circuit elements constituting each block in FIG. 1 are not particularly limited, a known MOSFET
(Metal oxide semiconductor type field effect transistor. In this specification, MOSFET is collectively referred to as insulated gate type field effect transistor). Formed. FIG. 1 shows a block configuration of a dynamic RAM having a layout form on a semiconductor substrate surface.
The positional relationship of each block will be described with reference to the top, bottom, left and right of the figure.

In FIG. 1, the dynamic RAM of this embodiment is not particularly limited, but includes 16 banks BA.
NK0 to BANKF (here, serial numbers of more than 9 banks and the like are indicated by alphabets, the same applies hereinafter), one redundant bank BANKR, and an interface circuit IF provided commonly to these banks. Among them, the interface circuit IF exchanges a start control signal, an address signal, input data, output data, etc. with an external access device, and sends and receives the bank BANK0 to BANK0.
BANKF and the redundant bank BANKR.

The banks BANK0 to BANKF and the redundant bank BAKR are connected to the banks BANK0 and BANK0.
F, a pair of memory arrays ARYU0 and ARYL0 to ARYL0 to AR
YUF and ARYLF and ARYUR and ARYL
R and sense amplifiers SAU0 to SAUH and SAL0 arranged at both ends or in the middle of these memory arrays.
SALH. The dynamic RAM is of a so-called "depending" type and has sense amplifiers SAU1 to SAUG and SAL1 to SAL2 except for two at both ends.
The ALG is shared by a pair of memory arrays arranged on both sides thereof. In addition, the memory array ARYU
0-ARYUF, ARYUR and ARYL0-AR
YLF and ARYLR include a predetermined number of redundant word lines and redundant bit lines, respectively, for relieving defects. Bank BA
NKBANK0-BANKF and redundant bank BAN
The specific configuration of the KR will be described later in detail with reference to FIG.

A pair of column address decoders CDU and CDL each including a Y-system redundancy circuit YRU or YRL are provided at the left end of the banks BANK0 to BANKF and the redundancy bank BANKR. A pair of row address decoders RDU and RDL each including a circuit XRU or XRL are provided. Among them, the column address decoders CDU and CD
L decodes a predetermined bit Y address signal supplied from the interface circuit IF when the dynamic RAM is set to a column cycle,
The corresponding bits of the bit line selection signals for AU0 to SAUH and SAL0 to SALH are alternatively set to the valid level. At this time, the Y-system redundancy circuits YRU and YRL of the column address decoders CDU and CDL apply the Y address signal and the memory arrays ARYU0 to ARYUF, A
RYUR and ARYL0 to ARYLF, ARYLR
Is compared with the rescue column address assigned to each redundant bit line for each bit, and the corresponding redundant bit line selection signal is selectively set to an effective level.

On the other hand, row address decoders RDU and RDU
DL decodes an X address signal of a predetermined bit supplied from the interface circuit IF when the dynamic RAM is set to a low cycle, so that the memory array A
RYU0 to ARYUF, ARYUR and ARYL0
ARYLF and ARYLR are set to the selected level alternatively. At this time, the X-system redundant circuits XRU and XRL of the row address decoders RDU and RDL are:
The X address signal and the memory arrays ARYU0 to ARY
UF, ARYUR and ARYL0 to ARYLF, A
The remedy row address assigned to each redundant word line of the RYLR is compared and collated bit by bit, and the corresponding redundant word line is selectively set to a selection level.

In this embodiment, the memory arrays ARYU0 to ARYUF, ARYUR, ARYUR and ARYL are used.
Word lines constituting 0 to ARYLF and ARYLR are hierarchized as a main word line and a sub word line. The row address decoders RDU and RDL are connected to the banks BANK0 to BANKF and the redundant bank BANKR.
And word lines can be independently selected. Further, the row address decoders RDU and RDL are provided with row bank address signals RBKA0 to RBKA supplied from the interface circuit IF.
A4 or column bank address signals CBKA0-CBKA
BKA4 is decoded, and the corresponding bank BANK0 to BANK0 is decoded.
A row bank address decoder and a column bank address decoder for selectively activating BANKF or redundant bank BANKR are included. This will be described later in detail.

FIG. 2 is a partial circuit diagram of one embodiment of the bank BANK1 (part A) included in the dynamic RAM of FIG. Based on the drawing, banks BANK0 to BANK B included in the dynamic RAM of this embodiment are shown.
The specific configuration and operation of the ANKF and the redundant bank BANKR will be described. In the following description of FIG. 2, bank BANK1 is referred to as bank BANK0.
ＢBANKF and the redundant bank BANKR will be described. Further, the memory array A constituting the bank BANK1
RYU1 and ARYL1 are divided into a predetermined number of sub-memory arrays in the direction in which the word lines extend, and the word lines forming each memory array are also hierarchized into main word lines and sub-word lines as described above. In FIG. 2, a portion closest to the row address decoder RDU of the memory array ARYU1 is illustrated together with a corresponding portion of the left sense amplifier SAU1. In the following circuit diagrams, MOSFETs whose channel (back gate) portions are marked with arrows are P-channel MOSFETs, and are distinguished from N-channel MOSFETs without arrows.

In FIG. 2, a memory array ARYU1 forming a bank BANK1 has a predetermined number of sub-word lines SW0 to SW3 arranged in parallel in the vertical direction in the figure and a predetermined number of redundant sub-word lines (not shown) for relieving defects. And a predetermined number of sets of complementary bit lines B0 * to B3 * arranged in parallel in the horizontal direction of the drawing (here, for example, the non-inverted bit line B0T and the inverted bit line B0B together with the complementary bit line B0 * In addition, a so-called non-inverted signal or the like which is selectively set to a high level when it is made valid is represented by adding a T to the end of its name, and it is indicated as valid. Inverted signals and the like which are selectively set to the low level when they are executed are denoted by suffixed with B. The same applies hereinafter) and a predetermined number of sets of redundant bit lines for defect relief. Including. At the intersections of these sub-word lines and redundant sub-word lines with the complementary bit lines and redundant bit lines, an information storage capacitor and an address selection MOSF
Dynamic memory cells MC made of ET are arranged in a lattice.

The memory array ARYU of the bank BANK1
The sub-word lines SW0 to SW3, etc. and redundant sub-word lines that constitute 1 are alternately coupled to the corresponding sub-word line drive circuits WD above or below them with a predetermined regularity. The sub-word line driving circuit WD receives a main word line driving signal MW from a corresponding unit circuit of the row address decoder RDU via a main word line MW0B or the like.
0B and the like are commonly supplied, and a 2-bit word line selection drive signal FX * is commonly supplied.

Here, the sub-word line drive circuit WD includes a predetermined number of unit circuits provided corresponding to the sub-word lines SW0 to SW3 of the memory array ARYU1 and redundant sub-word lines. Although not limited, as illustrated in the figure, it includes one P-channel MOSFET P3 or P4 and two N-channel MOSFETs N6 and N7 or N8 and N9. The sources of the MOSFETs P3 and P4 are respectively coupled to the corresponding non-inverted signal lines of the word line selection drive signal FX *, and the gates thereof are coupled to the corresponding main word line MW0B and the like. Also, MOSFET
The sources of N6 and N7 and N9 and N8 are coupled to the ground potential of the circuit, and their gates are coupled to the corresponding word line selection drive signal FX * inverted signal line or the corresponding main word line MW0B, respectively. MOSFETP3
And the drains of N6 and N7 are commonly coupled to the corresponding sub-word line SW0, etc., and the drains of MOSFET P4 and N8 and N9 are connected to the corresponding sub-word line S0.
Commonly connected to W3 and the like.

From these, for example, the sub word line S
W0 indicates a state in which the corresponding word line selection drive signal FX * is logic "1" (here, for example, the state in which the non-inversion signal of the word line selection drive signal FX * is at high level and the inverted signal is at low level). 1 "and the opposite state is referred to as logic" 0 ". The same applies hereinafter), and the corresponding main word line MW0B is set to low level to be selectively set to the high level, and the sub word line SW3 is selected.
Similarly, when the corresponding word line selection drive signal FX * is set to logic "1" and the corresponding main word line MW0B is set to low level, the selection level is selectively set to high level. For example, when the sub-word line SW0 is set to the selection level, the complementary bit line B of the memory array ARYU1 is
From 0 * to B3 *, etc., a minute read signal corresponding to the held data is output from a predetermined number of memory cells MC coupled to the sub-word line SW0.

In this embodiment, the row address decoders RDU and RDL are connected to the bank B as described above.
It is divided into 17 unit circuits corresponding to ANK0 to BANKF and the redundant bank BANKR. Further, these unit circuits decode the row address and execute the bank BA.
NK0-BANKF or the redundancy bank BANKR acts as a decoding means for selectively activating the word line selection drive signal FX as an output signal thereof.
* And has a function of holding the main word line MW0B and the like at an effective level, and also functions as a substantial row address holding means. As a result, the banks BANK0 to BANKB
The ANKF and the redundancy bank BANKR can independently perform a word line selection operation.

Next, the complementary bit lines B0 * -B3 *, etc. of the memory array ARYU1 and the redundant bit lines (not shown) are connected to the sense amplifier SAU on the left or right thereof.
1 or the corresponding unit circuits of SAU2 are alternately coupled. The sense amplifiers SAU1 and SAU2 include a predetermined number of unit circuits provided corresponding to the complementary bit lines B0 * to B3 * and the like and the redundant bit lines of the memory array ARYU1, and each of these unit circuits is illustrated in FIG. As shown, a unit sense amplifier UA in which a pair of CMOS (complementary MOS) is cross-coupled, and a pair of N-channel type switch MOSFETs NG and NH are included.

The complementary input / output node of the unit sense amplifier UA of each unit circuit of the sense amplifier SAU1 has N-channel type shared MOSFETs NB and N on its left side.
C, is coupled to a corresponding complementary bit line or redundant bit line of a memory array ARYU0 (not shown), and an N-channel type shared MOSFET ND on the right side thereof.
And NE, the corresponding complementary bit lines B0 * to B3 * of the memory array ARYU1 or redundant bit lines. The shared control signal SHL is commonly supplied to the gates of the shared MOSFETs NB and NC of each unit circuit from the corresponding unit circuit of the row address decoder RDU, and the shared control signal SHR is commonly supplied to the gates of the shared MOSFETs ND and NE. Is done.

Thus, the complementary input / output node of each unit sense amplifier UA of the sense amplifier SAU1 receives the shared control signal SHL at a high level and the shared MOSFET
When NB and NC are turned on, corresponding complementary bit lines B0 * to B3 of memory array ARYU0 are selectively provided.
* And a redundant bit line, the shared control signal SHR is set to the high level, and the shared MOSF
When ETND and NE are turned on, the corresponding complementary bit lines B0 * to B0 * to
B3 *, etc., and redundant bit lines.

P-channel MOSFET constituting unit sense amplifier UA of each unit circuit of sense amplifier SAU1
Are commonly coupled to a common source line CSP, and N
The source of the channel MOSFET is the common source line C
Commonly linked to SN. The common source line CSP is coupled to the power supply voltage of the circuit via two P-channel type driving MOSFETs P1 and P2 of the sense amplifier driving circuit SAD, and the common source line CSN is connected to the circuit via an N-channel type driving MOSFET N1. To the ground potential. Also, the driving MOSF of the sense amplifier driving circuit SAD
The gates of ETP1 and P2 are connected to the sense amplifier drive signal S from the corresponding unit circuit of the row address decoder RDU.
AP1 and SAP2 are supplied, respectively, and the driving MOSF
The sense amplifier drive signal SAN is supplied to the gate of ETN1.

As a result, the unit sense amplifier UA of each unit circuit of the sense amplifier SAU1 receives the low level of the sense amplifier drive signals SAP1 and SAP2 and drives the unit MO.
When the SFETs P1 and P2 are turned on and the sense amplifier drive signal SAN is at a high level, the drive MOSFET
When ETN1 is turned on, it selectively operates, and for example, a predetermined number of memory cells MC coupled to a sub-word line SW0 to SW3 or the like or a redundant sub-word line at a selected level of memory array ARYU1 have a corresponding complementary state. The small read signals output via the bit lines B0 * to B3 * or the like or the redundant bit lines are respectively amplified to obtain binary read signals in which the power supply voltage of the circuit is at a high level and the ground potential of the circuit is at a low level.

One of the switch MOSFETs NG and NH of each unit circuit of the sense amplifier SAU1 is respectively coupled to the non-inverting and inverting input / output nodes of the corresponding unit sense amplifier UA, and the other is connected to the corresponding local IO line L
It is coupled to a non-inverted or inverted signal line of IO *, respectively.
The gates of the switch MOSFETs NG and NH of the two adjacent unit circuits of the sense amplifier SAU1 are commonly coupled to the drains of the P-channel MOSFET P5 and the N-channel MOSFET NF, respectively. The gates of the MOSFETs P5 and NF which are commonly coupled have a column address decoder C (not shown).
A corresponding bit line selection signal YS0B or the like or a redundant bit line selection signal is supplied from the DU.

As a result, the switch MOSFETs NG and NH of each unit circuit of the sense amplifier SAU1 are selectively turned on by two sets when the corresponding bit line selection signal YS0B or the like or the redundant bit line selection signal is set to low level. , Complementary I / O nodes of unit sense amplifier UA of two corresponding unit circuits and two sets of local IO lines L
IO * is selectively connected.

The local IO line LIO * to which the complementary input / output node of the unit sense amplifier UA of the two specified unit circuits of the sense amplifier SAU1 is selectively connected is an N-channel type 2 of the sense amplifier drive circuit SAD. Coupled to corresponding two sets of global IO lines GIO * via sets of switch MOSFETs N2 and N3 and N4 and N5. Switch MOS of sense amplifier drive circuit SAD
The column bank selection signal CBK1 is supplied to the commonly coupled gates of the FETs N2 to N5 from the corresponding unit circuit of the row address decoder RDU.

Thus, the sense amplifier driving circuit SAD
The switch MOSFETs N2 to N5 are selectively and simultaneously turned on when the column bank selection signal CBK1 is set to the high level, and the corresponding two sets of local IOs
The line LIO * and the two sets of global IO lines GIO * are selectively connected.

Various operation powers are supplied to the row address decoder RDU from the interface circuit IF via a predetermined number of power supply lines POW. Further, the X address signal supply line XA and the row bank address signal supply line RBKA
X address signal XA, row bank address signal RBKA and column bank address signal C of predetermined bits via column bank address signal supply line CBKA.
BKA are supplied, respectively, and the row bank cycle signal R is supplied via a row bank cycle signal supply line RCYCB and a column bank cycle signal supply line CCYCB.
CYCB and a column bank cycle signal CCYCB are supplied, respectively.

The row address decoder RDU includes an X address signal XA, a row bank address signal RBKA, a column bank address signal CBKA, a row bank cycle signal RCYCB, and a column bank cycle signal CCY.
Based on CB, the main word line MW0B, etc., a word line selection drive signal FX *, shared control signals SHL and SHL
HR, sense amplifier drive signals SAP1 to SAP2 and S
The AN and the column bank selection signal CBK1 are selectively set to an effective level.

As described above, the memory array ARYU1
Includes a predetermined number of redundant sub-word lines and redundant bit lines, and the row address decoder RDU and the column address decoder CDU each include an X-system redundant circuit XRU and a Y-system redundant circuit YRU. For this reason, the sub-word line and the complementary bit line where the failure of the memory array ARYU1 is detected are selectively replaced with the redundant sub-word lines or redundant bit lines provided in the memory array ARYU1,
So-called defect relief is performed. However, for example, a defective sub-word line or a complementary bit line exceeding the number of redundant sub-word lines or redundant bit lines is detected in the memory array ARYU1, or some abnormality is found in the power supply path of the memory array ARYU1 or the sense amplifiers SAU1 and SAU2 on both sides thereof. In this case, when the DC characteristics are defective, the bank BANK1 including the DC characteristics is inaccessible as a block defect.

Therefore, in this embodiment, as described later, the inaccessible bank BANK1 and the like are redundantly provided by the bank redundancy circuits of the row address decoders RDU and RDL, that is, the row cycle bank redundancy circuit and the column cycle bank redundancy circuit. It is replaced with the bank BANKR and is relieved. At this time, the row address decoder R
The power supply line POW for DU and RDL is represented by × in FIG.
The portion indicated by the mark is cut off, whereby it is possible to prevent the entire dynamic RAM from having a DC characteristic defect especially due to the bank BANK1 having a DC characteristic defect.

FIG. 3 is a connection diagram of one embodiment for explaining a bank address signal transmission path of the dynamic RAM of FIG. 1, and FIG. 4 is a circuit diagram of the row cycle bank redundancy circuit RCBR of FIG. A circuit diagram of one embodiment is shown. Based on these figures, the transmission path of the row bank address signal and the column bank address signal of the dynamic RAM of this embodiment and the row cycle bank redundancy circuit R
The specific configuration and operation of the CBR and the column cycle bank redundancy circuit CCBR, the defect remedy method using the redundancy bank BANKR, its features, and the like will be described. In addition,
FIG. 3 illustrates a transmission path of a row bank address signal to row address decoder RDU, but it goes without saying that a transmission path of a similar row bank address signal for row address decoder RDL is similarly provided. The column cycle bank redundancy circuit C
CBR corresponds to the row cycle bank redundancy circuit RCBR of FIG.
Since the configuration is similar to that described above, a specific description thereof is omitted.

In FIG. 3, row address decoder RD
U is the row bank address decoder RB as described above.
The dynamic RAM includes a KD and a column bank address decoder CBKD. The dynamic RAM includes a row cycle bank redundancy circuit RCBR and a column cycle bank redundancy circuit CCBR provided corresponding to the row bank address decoder and the column bank address decoder. Of these, a 4-bit row bank address signal RB is supplied from the interface circuit IF to the row bank address decoder RBKD and the row cycle bank redundancy circuit RCBR.
KA0 to RBKA3 and a 1-bit row bank cycle signal RCYCB are commonly supplied, and a 4-bit column bank address signal C is supplied to a column bank address decoder CBKD and a column cycle bank redundancy circuit CCBR.
BKA0 to CBKA3 and a 1-bit column bank cycle signal CCYCB are commonly supplied.

The row cycle bank redundancy circuit RCBR is further supplied with a test redundancy bank selection signal TRRRBK and the most significant bit row bank address signal RBKA4 from the interface circuit IF, and receives a mode control signal MPDB from a mode register (not shown). Supplied. Of these, the row bank address signal RBKA4
Is supplied to the row bank address decoder RBKD of the row address decoder RDU after passing through the row cycle bank redundancy circuit RCBR.

Similarly, column cycle bank redundancy circuit C
To the CBR, the test redundant bank selection signal TCRBK and the most significant bit column bank address signal CBKA4 are supplied from the interface circuit IF, and the mode control signal MPDB is supplied from the mode register.
The column bank address signal CBKA4 is supplied to the column bank address decoder CBKD of the row address decoder RDU after passing through the column cycle bank redundancy circuit CCBR. The mode control signal MPDB
Although not particularly limited, when the dynamic RAM is set to the power down mode, the dynamic RAM is selectively set to a low level such as the ground potential of the circuit.

The row cycle bank redundancy circuit RCBR includes:
As will be described later, any of the banks BANK0 to BANKF becomes inaccessible due to some failure and the redundant bank B
A storage circuit for holding the address of the bank replaced by ANKR, that is, a rescue bank address, and a row bank address signal RBKA0 to RBKA3 supplied from the interface circuit IF for accessing the rescue bank address held by the storage circuit. And an address comparator circuit for comparing and collating, and selectively sets the most significant bit row bank address signal RBKA4 to the row bank address decoder RBKD to logic "1" or "0". When the dynamic RAM is set to a predetermined test mode and the test redundant bank selection signal TRRBK is set to a high level, the interface circuit IF
The row bank address signal RBKA4 for the row bank address decoder RBKD is selectively set to logic "1" or "0" in accordance with the row bank address signal RBKA4 supplied from.

Similarly, column cycle bank redundancy circuit C
The CBR includes a storage circuit for storing a rescue bank address of a bank which has become inaccessible among the banks BANK0 to BANKF and has been replaced with the redundant bank BANKF, and a rescue bank address held by the storage circuit for accessing the rescue bank address from the interface circuit IF. An address comparator for comparing the supplied column bank address signals CBKA0 to CBKA3 bit by bit,
A column bank address signal CBKA4 of the most significant bit for the column bank address decoder CBKD is selectively set to logic "1" or "0". When the dynamic RAM is set to the predetermined test mode and the test redundant bank selection signal TCRBK is set to the high level, the column bank address signal CBKA4 for the column bank address decoder CBKD is supplied according to the column bank address signal CBKA4 supplied from the interface circuit IF.
Is selectively set to logic “1” or “0”.

The row bank address decoder RBKD of the row address decoder RDU outputs a row bank cycle signal RCYCB when the dynamic RAM is in a row cycle.
Is at low level, the interface circuit IF
Row address signal RB of 4 bits supplied from
KA0 to RBKA3 are decoded and the bank BANK0 is decoded.
To BANKF are alternatively set to the active state, and the bank selection signals RBK0 to RBKF are alternatively set to the high level. Also, the row bank address signal R of the most significant bit supplied through the row cycle bank redundancy circuit RCBR.
When BKA4 is set to the high level, the decoding operation of the row bank address signals RBKA0 to RBKA3 is stopped, and the redundancy bank selection signal RBKR for activating the redundancy bank BANKR is alternatively set to the high level.

Similarly, a column bank address decoder C
BKD is a 4-bit column bank address signal CBKA0-CB supplied from the interface circuit IF when the dynamic RAM is set to the column cycle and the column bank cycle signal CCYCB is set to the low level.
KA3 is decoded, and banks BANK0 to BANKF are decoded.
Select signal CBK for selectively setting
0 to CBKF are alternatively set to the high level. When the most significant bit of the column bank address signal CBKA4 supplied via the column cycle bank redundancy circuit CCBR is set to the high level, the decoding operation of the column bank address signals CBKA0 to CBKA3 is stopped and the redundant bank BANKR is reset. The redundant bank selection signal CBKR for setting the active state is alternatively set to the high level.

Here, row cycle bank redundancy circuit RC
The BR and the column cycle bank redundancy circuit CCBR include five bank fuse circuits BFCE and BFC0 to BFC3 as shown by the row cycle bank redundancy circuit RCBR in FIG. 4, and each of these bank fuse circuits is , One fuse F2 or F1. Among them, the fuse F2 provided in the bank fuse circuit BFCE is connected to the banks BANK0 to BANK.
When any of the KFs becomes inaccessible due to some kind of failure and the defect is remedied by the redundant bank BAKR, it is selectively cut off. The fuse F1 provided in the bank fuse circuits BFC0 to BFC3 is
Bank BA which is replaced with the above-mentioned redundant bank BANKR
When the bank address signal of NK0 to BANKF, that is, the corresponding bit of the relief bank address is set to logic "1", each of them is selectively cut off.

The upper terminal of the fuse F2 constituting the bank fuse circuit BFCE of the row cycle bank redundancy circuit RCBR is connected to a pair of P-channel MOSFETs P8 and P8.
9 and to the input terminal of the inverter V2, the lower terminal of which is coupled to the input terminal of the inverter V2.
It is coupled to the ground potential of the circuit via a channel MOSFET NJ. The gate of MOSFET P8 is coupled to the ground potential of the circuit, and the gate of MOSFET P9 is coupled to the output terminal of inverter V2. The output signal of the inverter V2 is the NOR (NO
R) It is supplied to one input terminal of the gate NO1. MO
The mode control signal MPDB is supplied to the gate of the SFET NJ from a mode register (not shown). As described above, the mode control signal MPDB is selectively set to a low level such as the ground potential of the circuit when the dynamic RAM is set in the power down mode.

Thus, the bank fuse circuit BFCE
The redundancy enable signal REN, which is the output signal of the above, is selectively set to the low level when the defect is remedied by the redundancy bank BANKR and the fuse F2 is cut. When the dynamic RAM is in the power down mode and the mode control signal MPDB is at the low level, the MOSFET NJ of the bank fuse circuit BFCE is turned off, and the power consumption of the dynamic RAM in the power down mode is reduced.

On the other hand, row cycle bank redundancy circuit RCB
The upper terminal of the fuse F1 constituting the R bank fuse circuits BFC0 to BFC3 is coupled to the power supply voltage of the circuit through a corresponding pair of P-channel MOSFETs P6 and P7, and is coupled to the input terminal of the inverter V1. The terminal is coupled to the circuit ground via an N-channel MOSFET NI. The row bank cycle signal RCYCB is commonly supplied from the interface circuit IF to the gate of the MOSFET P6 of each bank fuse circuit, and the gate of the MOSFET P7 is coupled to the output terminal of the corresponding inverter V1. The output signal of the inverter V1 of each bank fuse circuit is applied to each bit of the rescue bank address allocated to the redundancy bank BANKR, that is, one input terminal of the exclusive OR circuits EO0 to EO3 corresponding to the rescue address signals RA0 to RA3, respectively. Supplied. The mode control signal MPDB is commonly supplied to the gate of the MOSFET NI.

Thus, the bank fuse circuit BFC0
BFC3 function as a storage circuit for holding the rescue address signal assigned to the redundant bank BANKR. The output signals of the rescue address signals RA0 to RA3 are such that the corresponding bit of the rescue address signal is set to logic "1" and When F1 is in the disconnected state, it is selectively set to the low level. When the dynamic RAM is in the power down mode and the mode control signal MPDB is at the low level, the bank fuse circuits BFC0 to BFC0
The MOSFET NI of the BFC 3 is turned off, thereby reducing the power consumption of the dynamic RAM in the power down mode.

The other input terminals of the exclusive OR circuits EO0 to EO3 of the row cycle bank redundancy circuit RCBR are
Corresponding row bank address signals RBKA0 to RBKA3 are supplied from the interface circuit IF, respectively.
The output signal is supplied to first to fourth input terminals of a NAND gate NA1. The output signal of the NAND gate NA1 is output from the NOR gate NO1.
Is supplied to the other input terminal. After passing through the transfer gate G2, the output signal of the NOR gate NO1 becomes a row bank address signal RBKA4 of the most significant bit for the row bank address decoder RBKD. The output terminal of the transfer gate G2 is commonly coupled to the output terminal of the transfer gate G1, and the input terminal of the transfer gate G1 is supplied with the most significant bit row bank address signal RBKA4 from the interface circuit IF. N-channel MOSFE of transfer gate G1
T and P-channel MOSF of transfer gate G2
The test redundancy bank selection signal TRRBK is applied to the gate of ET.
Are commonly supplied, and the inverter V3 is connected to the gates of the P-channel MOSFET of the transfer gate G1 and the N-channel MOSFET of the transfer gate G2.
Are commonly supplied.

Thus, exclusive OR circuits EO0 to EO3 of row cycle bank redundancy circuit RCBR provide relief address signal RA assigned to redundancy bank BANKR.
0 to RA3 and a row bank address signal RBKA0 supplied from the interface circuit IF at the time of access.
To RBKA3, and outputs an output signal of the relief address signal R
A0 to RA3 and row bank address signals RBKA0 to RBKA
When the corresponding bit of BKA3 is set to a different logic level, it is selectively set to the high level. As described above, each bit of the rescue address signals RA0 to RA3 is selectively set to a low level when the corresponding bit of the rescue address assigned to the redundant bank BANKR is set to logic "1", and the row bank address signal RBKA0 is set. ~ RBKA3
Indicates that the corresponding bit of the row bank address is logic "1"
Is selectively set to a high level.

For this reason, exclusive OR circuits EO0 to EO are used.
3 are output when the corresponding bits of the rescue address signals RA0 to RA3 and the row bank address signals RBKA0 to RBKA3 are both at a high level or a low level, in other words, the rescue address signals RA0 to RA3.
And the corresponding bits of the row bank address signals RBKA0 to RBKA3 coincide with each other, they are selectively set to the high level. The output signal of the NAND gate NA1 is output when the output signals of the exclusive OR circuits EO0 to EO3 are both at a high level, in other words, the relief address signals RA0 to RA3 and the row bank address signal RB.
When all bits of KA0 to RBKA3 match, the output signal of the NOR gate NO1 is selectively set to the low level. When both the redundancy enable signal REN and the output signal of the NAND gate NA1 are set to the low level, in other words, the defect relief by the redundant bank BANKR. Is performed and the relief address signals RA0 to RA3 and the row bank address signal R
When BKA0 to RBKA3 match all bits, they are selectively set to the high level.

On the other hand, the transfer gate G1 is selectively set to the transmission state when the dynamic RAM is set to a predetermined test mode and the test redundant bank selection signal TRRBK is set to the high level. The transfer gate G2 is connected to the dynamic RAM. When the normal operation mode is set and the test redundant bank selection signal TRRBK is set to the low level, the transmission state is selectively set. Therefore, the row bank address signal RBK for the row bank address decoder RBKD
A4 is selectively set to a high level or a low level in accordance with the output signal of the NOR gate NO1 when the dynamic RAM is set to the normal operation mode, and the dynamic RA
When M is set to the predetermined test mode, the row bank address signal RB supplied from the interface circuit IF
It is selectively set to a high level or a low level according to KA4.

As described above, when the row bank address signal RBKA4 of the most significant bit is set to the high level, the row bank address decoder RBKD stops the decoding operation of the row bank address signals RBKA0 to RBKA3 and resets the redundant bank BANKR. Activate. Therefore, when the dynamic RAM is set in the normal operation mode, the redundant bank BANKR is used.
And repair address signals RA0 to RA0
RA3 and row bank address signals RBKA0-RBKA
When all 3 bits match, the row bank address signal R
When the dynamic RAM is set to a predetermined test mode when the dynamic RAM is set to a predetermined test mode, a row bank address signal RBKA4 supplied from the interface circuit IF, that is, an external test device is provided. Is selectively activated in response to the high level.

As a result, the dynamic type R of this embodiment
In the AM, a defective sub-word line or a complementary bit line exceeding the number of redundant sub-word lines or redundant bit lines of the corresponding memory array is detected, or some abnormality is found in the power supply path of the corresponding memory array or the sense amplifiers on both sides thereof. It is possible to replace a bank that has become inaccessible due to defective DC characteristics by replacing it with a redundant bank BAKR.
Product yield can be increased. At this time,
Row cycle bank redundancy circuit R of dynamic RAM
CBR is a 4-bit relief address signal RA0-RA3.
And the row bank address signals RBKA0 to RBKA3 only need to be compared and collated. Therefore, the address comparison circuit has a relatively shallow logical configuration including a one-stage exclusive OR circuit EO0 to EO3, a NAND gate NA1 and a NOR gate NO1. And the dynamic RAM
Of the redundant bank BAKR is accelerated. Further, in the dynamic RAM of this embodiment, the redundant bank BANKR can be intentionally activated by setting the test redundant bank selection signal TRRBK to high level and the row bank address signal RBKA4 of the most significant bit to high level. Thus, the normality of the redundant bank BANKR can be confirmed even when the defect is not repaired.

In the above embodiment, the description has been made centering on the bank rescue at the time of the row cycle by the row cycle bank redundancy circuit RCBR. A redundant circuit CCBR is provided to support bank rescue during a column cycle.

FIG. 5 is a block diagram showing a second embodiment of the dynamic RAM to which the present invention is applied. FIG. 6 shows a row cycle included in the row address decoder of the dynamic RAM of FIG. Bank redundancy circuit RCBR
1 is a circuit diagram of the first embodiment. Since this embodiment basically follows the embodiment of FIGS. 1 to 4, only the different parts will be described.

Referring to FIG. 5, the dynamic RAM according to this embodiment includes, in addition to 16 banks BANK0 to BANKF, which are sequentially arranged adjacent to each other in the bit line extension direction.
Similarly, a pair of redundant banks BANKR0 and BANKR1 which are arranged adjacently and are paired is provided. These redundant banks BANKR0 and BANKR1 are not particularly limited, but when the row bank address signal RBKA4 of the most significant bit for the row address decoder RDU or the row bank address decoder RBKD of the RDL is set to the high level, the row bank of the least significant bit is set. Address signal R
It is selectively activated according to BKA0. That is, redundant bank BANKR0 is selectively activated under the condition that row bank address signal RBKA4 is at a high level and row bank address signal RBKA0 is at a low level, and redundant bank BANKR1 is provided with a row bank address signal RBKA4. And RBKA0 are selectively activated on condition that both are at a high level.

The row cycle bank redundancy circuit RCBR includes:
As shown in FIG. 6, the bank fuse circuits BFCE and BFC0 to BFC3, the exclusive OR circuits EO0 to EO3, the NAND gate NA1, and the inverter V shown in FIG.
3, plus one circuit ADD receiving relief address signals RA0-RA3 as output signals of bank fuse circuits BFC0-BFC3 in addition to transfer gates G1 and G2.
1 and a row bank address signal R
Four exclusive OR circuits E each receiving the corresponding bit of BKA0 to RBKA3 and receiving the corresponding output signal of the plus one circuit ADD11 at the other input terminal.
O4 to EO7.

In this embodiment, the NAND gate NA1
Is a five-input gate, the fifth input terminal of which is supplied with an inverted signal of the redundancy enable signal REN by the inverter V4. Further, the redundant banks BANKR0 and BAKR
NKR1 is paired as described above, and bank BAN1
K0 to BANKF are replaced by redundant banks BANKR0 and BANKR1 in units of two adjacently arranged units. Therefore, the bank fuse circuits BFC0 to BF
In C3, the row address of the youngest bank of the two banks replaced with the redundant banks BANKR0 and BFCR1 is written as the relief address signals RA0 to RA3, and the fuse F2 of the bank fuse circuit BFCE is written.
Is 2 by redundant banks BAKR0 and BANKR1.
When the defect is repaired in the unit of a bank, it is selectively cut.

The output signals of the exclusive OR circuits EO4 to EO7 are supplied to first to fourth input terminals of the NAND gate NA2, respectively. The fifth of this NAND gate NA2
Is supplied with an inverted signal of the redundancy enable signal REN, which is an output signal of the bank fuse circuit BFCE, by the inverter V4. The output signal is supplied to one input terminal of the NAND gate NA3 and, after passing through the inverter V6 and the transfer gate G4, becomes a row bank address signal RBKA0 of the least significant bit for the row address decoder RDU. The output terminal of the transfer gate G4 is connected to the transfer gate G.
3 output terminals are commonly coupled. The input terminal of the transfer gate G3 is supplied with the least significant bit row bank address signal RBKA0 from the interface circuit IF.

The output signal of the NAND gate NA1 is supplied to the other input terminal of the NAND gate NA3. After passing through the transfer gate G2, the output signal becomes the most significant bit row bank address signal RBKA4 for the row address decoder RDU. Transfer gate G3
The output signal of the NAND gate NA3 is commonly supplied to the gates of the P-channel MOSFET of the transfer gate G4 and the N-channel MOSFET of the transfer gate G4, and the inverters are connected to the gates of the N-channel MOSFET of the transfer gate G3 and the P-channel MOSFET of the transfer gate G4. An inverted signal by V5 is commonly supplied. Thereby, the transfer gate G3 becomes
When the output signal of the NAND gate NA3 is set to the low level, the transmission state is selectively set, and the transfer gate G4
Are selectively transmitted when the output signal of the NAND gate NA3 is at a high level.

The exclusive OR circuits EO0 to EO3 act as the first address comparison circuit, as in the embodiment of FIG. 4, and operate as bank fuse circuits BFC0 to BFC3.
Address signal RA0 of 4 bits held by
To access RA3 and interface circuit IF
Row address signal RB of 4 bits supplied from
KA0 to RBKA3 are compared and collated bit by bit, and when the logical values of both addresses match, their output signals are selectively set to a high level.

Therefore, the output signal of NAND gate NA1 is output when redundancy enable signal REN is at a low level and output signals of exclusive OR circuits EO0 to EO3 are both at a high level, in other words, by redundancy banks BANKR0 and BANKR1. When defect repair is performed and the repair address signals RA0 to RA3 stored by the bank fuse circuits BFC0 to BFC3 and the row bank address signals RBKA0 to RBKA3 supplied from the interface circuit IF at the time of access match all bits, that is, redundancy Of the two banks replaced with the banks BANKR0 and BANKR1, the lower bank is the row bank address signal RBKA0 to RBKA.
When designated by KA3, it is selectively set to low level, and in response, the output signal of NAND gate NA3 is set to high level.

On the other hand, the plus one circuit ADD1 adds 1 to the rescue address signals RA0 to RA3 output from the bank fuse circuits BFC0 to BFC3 to generate an output signal. The exclusive OR circuits EO4 to EO7 are connected to the second
Of the repair address signal R
The address obtained by adding 1 to A0 to RA3, that is, the next address of the rescue address signals RA0 to RA3 and the row bank address signals RBKA0 to RB supplied at the time of access.
KA3 is compared and collated bit by bit, and when the logical values of both addresses match, the output signal is selectively made high.

Therefore, the output signal of the NAND gate NA2 is output when the redundancy enable signal REN is at a low level and the output signals of the exclusive OR circuits EO4 to EO7 are both at a high level, that is, the redundancy bank BANK.
When the defect relief by R0 and BANKR1 is performed, and all the bits of the row bank address signals RBKA0 to RBKA3 supplied from the interface circuit IF at the time of accessing the output of the plus one circuit ADD1 match,
That is, when the oldest bank of the two banks replaced with the redundant banks BANKR0 and BANKR1 is designated by the row bank address signals RBKA0 to RBKA3, the bank is selectively set to the low level, and in response to this, the output signal of the NAND gate NA3 is received. Is set to a high level.

When the output signals of the NAND gates NA1 and NA2 are both at the high level and the output signal of the NAND gate NA3 is at the low level, in other words, other normal except for the two banks replaced with the redundant banks BANKR0 and BANKR1. When a proper bank is designated by row bank address signals RBKA0 to RBKA3, in row cycle bank redundancy circuit RCBR, transfer gate G3 is in a transmission state and transfer gate G4 is in a non-transmission state. Therefore, a low-level row bank address signal RBKA4 is supplied to the row bank address decoder RBKD of the row address decoder RDU via the transfer gate G2, and the row bank address signal RBKA0 supplied from the interface circuit IF is supplied to the transfer gate G3. Transmitted as is. As a result, the normally operating bank BAN
Row bank address signal RBK of K0-BANKF
One designated by A0 to RBKA3 is the row bank address decoder RBK of the row address decoder RDU.
D activates alternatively.

Next, when the output signal of the NAND gate NA1 is set to the low level and the output signals of the NAND gates NA2 and NA3 are set to the high level, in other words, of the two banks replaced with the redundant banks BANKR0 and BANKR1, When the number-side bank is specified by row bank address signals RBKA0 to RBKA3, in row cycle bank redundancy circuit RCBR, transfer gate G3 is in a non-transmission state, and transfer gate G4 is in a transmission state instead. Therefore, the row bank address decoder R of the row address decoder RDU
A high-level row bank address signal RBKA4 is supplied to BKD via a transfer gate G2, and a low-level row bank address signal RBKA0 is supplied via a transfer gate G4. As a result, the banks BANK0 to BANKF are deactivated, and the redundant bank BANKR0 is activated.

On the other hand, when the output signals of NAND gates NA1 and NA3 are at a high level and the output signal of NAND gate NA2 is at a low level, that is, when redundant bank BA
Of the two banks replaced with NKR0 and BANKR1, the oldest bank is the row bank address signal RB.
When designated by KA0 to RBKA3, in row cycle bank redundancy circuit RCBR, transfer gate G3 is also in a non-transmitting state, and transfer gate G
4 is in the transmission state. Therefore, a high-level row bank address signal RBKA4 is supplied to the row bank address decoder RBKD of the row address decoder RDU via the transfer gate G2, and a high-level row bank address signal RBKA0 is supplied via the transfer gate G4. Is supplied. As a result, the banks BANK0 to BANKF are also inactivated, and the redundant bank BANKR1 is activated.

As described above, the dynamic RAM of this embodiment has two redundant banks BAN which are paired.
KR0 and BANKR1 are provided, and the bank BANK0 is provided.
〜BANKF are replaced with redundant banks BANKR0 and BANKR1 in units of two adjacently arranged units. Also, the row cycle bank redundancy circuit RCBR includes:
2 which includes bank fuse circuits BFC0 to BFC3 and is replaced with redundant banks BANKR0 and BANKR1
One storage circuit is provided for holding the row address of the youngest bank among the plurality of banks, and the row address of the oldest bank is automatically generated by the plus one circuit ADD1. As a result, the circuit configuration of the row cycle bank redundancy circuit RCBR can be simplified, and the cost of the dynamic RAM can be reduced, while obtaining the same effects as those of the embodiment of FIGS.

The dynamic RAM of this embodiment
Is a so-called dependent type, and sense amplifiers SAU0 to SAU0
SAUI and SAL0-SALI are available in Bank BAN
K0 to BANKF are respectively shared by two adjacent ones. As is well known, a dependent dynamic RA
In the case of M, for example, when a short circuit in the power supply path occurs in any of the sense amplifiers, the DC characteristics of the two banks sharing the same become poor at the same time, making it inaccessible in many cases. As in this embodiment, two redundant banks BANKR0 and BANKR1 are provided as a pair, and are replaced simultaneously with two adjacent banks, so that two banks sharing a sense amplifier cannot be accessed simultaneously. In this case, the product yield of the dynamic RAM can be further increased.

FIG. 7 is a circuit diagram of a second embodiment of the row cycle bank redundancy circuit RCBR included in the row address decoder of the dynamic RAM of FIG. Since this embodiment basically follows the embodiment of FIG. 6, only the different parts will be described.

In FIG. 7, the row cycle bank redundancy circuit RCBR of this embodiment comprises the bank fuse circuits BFCE and BFC0 to BFC3, exclusive OR circuits EO0 to EO3 and EO4 to EO7, and NAND gates NA1 to NA3 of FIG. In addition to inverters V3 to V6 and transfer gates G1 to G4, four bank fuse circuits BFC4 to BFC7 are included. Exclusive OR circuit E
One of the input terminals of O0 to EO3 is supplied with relief address signals RA00 to RA03 as output signals of the bank fuse circuits BFC0 to BFC3, and the other input terminal is supplied with the row bank address signals RBKA0 to RBKA0 from the interface circuit IF. RBKA3 is supplied. One of the input terminals of the exclusive OR circuits EO4 to EO7 is connected to the bank fuse circuits BFC4 to BFC7.
And the other input terminals are supplied with row bank address signals RBKA0-RBKA3, respectively.

In this embodiment, the dynamic RA
M is a so-called independent type, and the bank BAN
K0 to BANKF and redundant banks BANKR0 and BANKR1 individually occupy sense amplifiers. Also, the redundant banks BANKR0 and BANKR1
Are allocated to one or two of the banks BANK0 to BANKF, which are inaccessible, in an arbitrary combination. The two storage circuits including the bank fuse circuits BFC0 to BFC3 and BFC4 to BFC7 respectively have individual storage circuits. A relief address signal is provided.

Upon access, interface circuit I
Row bank address signals RBKA0 supplied from F.
RBKA3 and relief address signals RA00 to RA03 held by bank fuse circuits BFC0 to BFC3
And all bits match, and the output signal of NAND gate NA1 attains a low level, row address decoder RDU
The row bank address signal RBKA4 of the most significant bit for the row bank address decoder RBKD is set to the high level, and the row bank address signal RB of the least significant bit is set.
Since KA0 is at the low level, the redundant bank BANK
R0 is activated. The row bank address signals RBKA0 to RBKA3 and the bank fuse circuit BFC
4 to the relief address signal RA held by the BFC 7
10 to RA13 match all bits, and NAND gate NA
When the output signal of No. 2 is at the low level, the row bank address signals RBKA4 and RBKA0 are both at the high level, so that the redundant bank BANKR1 is activated.

As described above, in the dynamic RAM according to this embodiment, two redundant banks BANKR0 and BANKR1 are provided as in the embodiment of FIG. 6, but these redundant banks are not paired, and BANK0
Independently assigned to one or two banks of the BANKF that have become inaccessible, thereby further increasing the product yield of the dynamic RAM. Needless to say, the row addresses of two adjacent banks can be written in the two storage circuits including the bank fuse circuits BFC0 to BFC3 and BFC4 to BFC5, and the dependent dynamic RA shown in FIG.
M can be handled.

The operation and effect obtained from the above embodiment are as follows. That is, (1) a multi-bank dynamic RAM having a large number of banks capable of independently performing a word line selecting operation.
And so on, by providing a predetermined number of redundant banks and a row cycle bank redundant circuit and a column cycle bank redundant circuit for selectively replacing a defective bank which has become a block failure due to a DC characteristic failure or the like with one of the redundant banks. As a result, it is possible to cope with a block failure such as a DC characteristic failure, which is likely to occur as the number of banks of a dynamic RAM or the like advances and the technology of miniaturization and high integration of a semiconductor integrated circuit advances. . (2) According to the above item (1), it is possible to relatively easily and quickly replace a bank having a defective block with a redundant bank and to repair the redundant bank. (3) According to the above items (1) and (2), the effect of increasing the product yield of a multi-bank type dynamic RAM or the like can be obtained.

(4) In the above items (1) to (3), a power supply path for supplying operating power to each bank is provided independently for each bank, and one of the banks has a poor DC characteristic. In this case, by setting the corresponding power supply path to the disconnected state, it is possible to obtain an effect that it is possible to prevent the whole of the dynamic RAM or the like from becoming defective due to the bank having the DC characteristic defect.

(5) In the above items (1) to (4), when adjacent banks such as a dynamic RAM share a sense amplifier arranged in the middle, for example, two banks are paired. By providing redundant banks of
For example, it is possible to easily cope with a case where banks on both sides sharing the same become inaccessible at the same time due to a DC characteristic failure of the sense amplifier or the like. (6) According to the above item (5), an effect is obtained that the product yield of a dynamic RAM or the like can be further increased. (7) In the above items (5) and (6), a rescue bank address assigned to one of the paired redundant banks and an address obtained by adding or subtracting 1 thereto and a bank supplied from the outside upon access. By comparing the address with the address and selectively activating the paired redundant banks, the circuit configuration of the row cycle bank redundant circuit is simplified, and the cost of a dynamic RAM or the like including this is reduced. The effect that it can be achieved is obtained.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIGS. 1 and 5, the dynamic RAM is
Any number of banks may be provided, and any number of redundant banks may be provided. Dynamic type R
As described above, the AM can be a so-called independent type in which the sense amplifier is exclusively used by each bank. The memory arrays ARYU0 to ARYUF and ARYL0 to ARYLF do not necessarily have to include redundant word lines and redundant bit lines, and the reason why the banks BANK0 to BANKF are inaccessible is not limited to this embodiment. Absent. Dynamic RA
The block configuration of M can take various embodiments, and its chip layout is not limited.

In FIG. 2, the word lines constituting each memory array do not necessarily have to be hierarchized, and the hierarchization of common IO lines is not an essential condition. The specific configuration of the sub-word line drive circuit WD, the sense amplifier SAU1, and the sense amplifier drive circuit SAD, the polarity of the power supply voltage, the conductivity type of the MOSFET, and the like can take various embodiments. In FIG. 3, the number of bits of the row bank address signal and the column bank address signal can be arbitrarily set according to the number of banks and redundant banks. In FIG. 6, a row cycle bank redundancy circuit RCBR writes a relief bank address of an oldest bank among two banks replaced with the redundancy banks BANKR0 and BANKR1 into a storage circuit composed of bank fuse circuits BFC0 to BFC3, and By providing a minus one circuit in place of the one circuit ADD1, the rescue bank address of the youngest bank may be automatically generated. 4, 6 and 7, the specific configuration of the row cycle bank redundancy circuit RCBR can take various embodiments as long as its logical condition does not change, and the effective levels of each address signal and internal control signal are also different. The same is true.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM, which is the field of application as the background, has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuit devices having a dynamic RAM as a basic configuration, and logic integrated circuit devices including such a memory integrated circuit device. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor memory device having at least a plurality of banks and a device or system including the same.

[0084]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a predetermined number of redundant banks and a defective bank having a block failure due to a DC characteristic failure or the like are added to a redundant bank of a multi-bank type dynamic RAM or the like having a large number of banks capable of independently performing a word line selecting operation. A row cycle bank redundancy circuit and a column cycle bank redundancy circuit for selectively replacing any one of the above, and a power supply path for supplying operating power to each bank is provided independently for each bank. When the DC characteristics of the bank become poor, the corresponding power supply path is cut off. When banks arranged adjacent to each other, such as a dynamic RAM, share a sense amplifier arranged in the middle, for example, two redundant banks are provided as a pair, and are assigned to one of these redundant banks. Relief bank address and 1
Is compared with an address obtained by adding or subtracting the address and a bank address supplied from the outside at the time of access.
The redundant banks are selectively activated.

As a result, it is possible to cope with block failures such as DC characteristic failures, which are likely to occur as the number of banks of a dynamic RAM and the like increases and the technology of miniaturization and high integration of semiconductor integrated circuits advances. Since a bank having a bad block can be replaced with a redundant bank relatively easily and at a high speed and repaired, the yield of products such as a multi-bank dynamic RAM can be improved. Further, when banks arranged adjacent to each other such as a dynamic RAM share a sense amplifier arranged in the middle, banks on both sides sharing the sense amplifier become inaccessible at the same time due to, for example, poor DC characteristics of the sense amplifier. Dynamic type R that can easily respond to the case
The yield of products such as AM can be further increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a diagram showing a dynamic RAM bank BANK of FIG. 1;
FIG. 1 is a partial circuit diagram showing an example of a part (A).

FIG. 3 is a connection diagram showing one embodiment of a bank address signal transmission path of the dynamic RAM of FIG. 1;

FIG. 4 is a circuit diagram showing one embodiment of a row cycle bank redundancy circuit included in the dynamic RAM of FIG. 1;

FIG. 5 is a block diagram illustrating a dynamic RAM according to a second embodiment of the present invention;

FIG. 6 is a circuit diagram showing a first embodiment of a row cycle bank redundancy circuit included in the dynamic RAM of FIG. 5;

FIG. 7 is a circuit diagram showing a second embodiment of the row cycle bank redundancy circuit included in the dynamic RAM of FIG. 5;

FIG. 8 is a block diagram showing an example of a dynamic RAM developed by the present inventors prior to the present invention.

9 is a connection diagram showing an example of a bank address signal transmission path of the dynamic RAM of FIG.

[Explanation of symbols]

IF: Interface circuit, BANK0-BANK
F: Bank, BANKR, BANKR0-BANKR
1 ... redundant bank, ARYU0 to ARYUF, ARYL
0 to ARYLF: memory array, ARYUR, ARY
LR, ARYUR0 to ARYUR1, ARYLR0 to A
RYLR1 ... redundant memory array, SAU0 to SAU
H, SAL0 to SALH Sense amplifier, RDU, R
DL: Row address decoder, XRU, XRL ... X
, A column address decoder, YRU, YRL,... A Y-system redundant circuit. SW0-SW3
…… Sub word line, B0 * to B3 * …… Complementary bit line
MC: dynamic memory cell, WD: sub-word line drive circuit, UA: unit sense amplifier, CSP, C
SN: common source line, YS0B: bit line selection signal, SAD: sense amplifier drive circuit, LIO *: local IO line, GIO *: global IO line, SH
L, SHR: Shared control signal, SAP1 to SAP
2, SAN: sense amplifier drive signal, CBK: column bank select signal, FX *: word line select drive signal,
MW0B: Main word line, POW: Power supply line,
XA: X address signal, RBKA: Row bank address signal, CBKA: Column bank address signal, R
CYC... Row bank cycle signal, CCYC... Column bank cycle signal. RCBR: Row cycle bank redundancy circuit, CCBR: Column cycle bank redundancy circuit, RBKD: Row bank address decoder, CBK
D: Column bank address decoder, RBKA0-RB
BKA4: Row bank address signal, CBKA0 to CBKA
BKA4 ... column bank address signal, TRRBK,
TCRBK: Test redundancy bank selection signal, RBK0 to RBK
BKF ... Row bank selection signal, CBK0 to CBKF ...
... column bank selection signal, RBKR, CBKR ... redundant bank selection signal, MPDB ... power down mode signal. BFC0 to BFC7, BFCE ... bank fuse circuit, REN ... redundancy enable signal, RA0 to RA
3, RA00 to RA03, RA10 to RA13 ... relief address signals. ADD1 ... Plus one circuit. P1 to P9
... P-channel MOSFET, N1 to NJ N-channel MOSFET, F1 to F2, fuse, V1
V6: an inverter, EO0 to EO7, an exclusive OR circuit, NA1 to NA3, a NAND gate,
NO1 NOR gates, G1 to G4 transfer gates.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI // H01L 21/82

Claims (6)

[Claims] 1. A plurality of banks each including a substantial row address holding unit and a decoding unit, and capable of independently performing a word line selecting operation, and one of the banks inaccessible due to a fault. And a redundant bank that is replaced with a redundant bank. 2. The bank according to claim 1, wherein the bank includes a redundant word line and a redundant bit line, respectively, and when a defect cannot be remedied by the redundant word line or the redundant bit line, or A semiconductor memory device which is selectively made inaccessible when the DC characteristics become poor. 3. The bank according to claim 1, wherein a predetermined operation power is supplied to each of the banks via a corresponding power supply line. A semiconductor memory device which is selectively cut off when the DC bank has the above-mentioned poor DC characteristics. 4. The bank according to claim 1, wherein the bank is alternately designated according to a predetermined bit of a bank address signal, and the redundant bank is a bank other than the bank address signal. When the predetermined bit of the bank address signal is set to a valid level, the semiconductor memory device decodes a predetermined bit of the bank address signal to selectively activate the designated bank. And a rescue bank address assigned to the redundant bank, and compares and compares the rescue bank address with a predetermined bit of the bank address signal. And a bank redundancy circuit for setting another predetermined bit of the bank address signal to the effective level. The semiconductor memory device. 5. The semiconductor memory device according to claim 1, wherein the plurality of banks are sequentially arranged adjacent to each other in a bit line extending direction. Comprises a predetermined set of the above-mentioned redundant banks similarly arranged adjacently and in a pair configuration. 6. The bank redundancy circuit according to claim 5, wherein the bank redundancy circuit stores a relief bank address assigned to one of the pair of redundancy banks, and one of the relief bank addresses output from the storage circuit. Plus one circuit or minus one circuit for adding or subtracting, a first address comparison circuit that compares and matches a predetermined bit of the bank address with the relief bank address output from the storage circuit bit by bit, And a second address comparing circuit for comparing and checking the predetermined bit with the output of the plus one circuit or the minus one circuit for each bit.