JPH11305723A - Track interpolation type scroll display device characterized by overcurrent protection of display lamp - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an overcurrent from flowing to a lamp and to prevent it from breaking when an abnormal signal which is not a pulse signal is inputted to the enable terminal of a lamp driving circuit. SOLUTION: A blinking pulse signal BCK inputted to the enable terminal Enb of a lamp driving IC 68 drives and blinks an LED lamp in a short cycle to make the lamp synchronize with this. An integration circuit 70 inverts and outputs a level signal generated by integrating the blinking pulse signal BCK and averaging its pulse level with time, to the output terminal 74c of an operational amplifier 74. Through a current value setting terminal 70, the current value of the driving current of the lamp is increased or decreased and set according to the signal level at the output terminal 74c and the driving current is made smaller as the lamp ON period of the blinking pulse signal BCK is longer. Here, even if a signal which turns ON the lamp continuously is inputted to the enable terminal Enb by mistake, an overcurrent of the LED can be prevented to protect the lamp against breakage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tracking interpolation type scroll display device in which a large number of lamp units having a large number of display lamps are arranged to form a two-dimensional display screen. Regarding current protection.

[0002]

2. Description of the Related Art Applicants have previously disclosed in Japanese Patent Application Laid-Open No. 8-179.
717, JP-A-9-134141, JP-A-9-134142, JP-A-9-134143, JP-A-9-281922 and JP-A-9-311
A scroll display system as disclosed in detail in, for example, Japanese Patent No. 659 has been developed and put to practical use. This system is a scroll display technology in which a large-sized and fine image can be visually recognized with a small number of light-emitting elements (eg, an LED lamp). A very characteristic feature is that a fine image interpolated by the afterimage effect can be visually recognized only by tracking the scrolling image with the line of sight. We named this mechanism a tracking interpolation scroll display.

[0003] This tracking interpolation type scroll display system comprises one or more control units and a number of lamp units connected to the control units via a transmission system. The lamp unit has a lamp row in which a large number of LED lamps are linearly arranged at small intervals, and are arranged at intervals from each other. Each LED lamp is one pixel, and the entire lamp unit forms one display screen. The display data is individually sent from the control unit to each lamp unit, and the lamp drive circuit of the lamp unit individually controls the light emission of each LED lamp based on the display data to perform tracking interpolation scroll display.

On the other hand, the luminance control of each LED lamp is performed by a so-called duty control method. A flashing pulse signal of a sufficiently high frequency is sent from the control unit to each lamp unit. The lamp drive circuit of each lamp unit drives each LED lamp to blink in a sufficiently short cycle in synchronization with the blink pulse signal. The control unit changes the light emission luminance of the LED lamp by variably controlling the duty ratio of the blinking pulse signal to be sent.

The structure of the lamp driving circuit includes a simple and convenient lamp driving IC called "16-bit shift register latch constant current driver" [for example, TB62706AN.
(Manufactured by Toshiba) and TB62701N (manufactured by Toshiba)]. When the display data for 16 dots sent from the control unit is input from the serial-in terminal, the lamp drive IC sequentially shifts the display data to the shift register according to the clock signal from the clock input terminal. . Then, the display data stored in the shift register is latched in accordance with the latch signal from the latch terminal and output to the driver output terminal. In addition, the lamp drive I
C is an enable terminal for receiving the blinking pulse signal and changing the light emission luminance of the LED lamp;
A current value setting terminal for variably setting a current value of a drive current flowing through the lamp. When this current value setting terminal is grounded via a resistor, a drive current proportional to the value of the current flowing through the resistor flows through the LED lamp. That is, by changing the resistance value of the resistor, a desired drive current can be supplied to the LED lamp.

[0006]

However, the blinking pulse signal sent from the control line may not be normally input to the enable terminal of the lamp driving circuit due to disconnection or short circuit of the line during transmission. In this case, the signal level is continuously in the “Lo” state or “H”.
When the signal in the “i” state is input to the enable terminal, LE
The D lamp is continuously turned on, and the drive current flows excessively, which may eventually result in damage.

SUMMARY OF THE INVENTION It is an object of the present invention to perform tracking interpolation so that an excessive drive current does not flow through an LED lamp and no damage is caused when a normal blinking pulse signal is not input to an enable terminal of a lamp drive circuit. An object of the present invention is to provide a scroll display device.

[0008]

SUMMARY OF THE INVENTION A tracking interpolation type scroll display device characterized by overcurrent protection of a display lamp according to the present invention has the following requirements (1) to (5). (1) One or more control units and a number of lamp units connected to the control units via a transmission system are provided. (2) A large number of lamp units are arranged in a predetermined layout at intervals from each other. Many lamps are arranged in each lamp unit in a predetermined layout. Each lamp is configured as one pixel, and one display screen is formed by the entire lamp unit. (3) Each lamp unit has a lamp drive circuit that individually controls light emission of each lamp of the lamp unit based on display data transmitted from the control unit. (4) A sufficiently high-frequency blinking pulse signal transmitted from the control unit is input to the enable terminal of each lamp drive circuit, and each lamp is driven to blink in a sufficiently short cycle in synchronization with the blinking pulse signal. . The control unit changes the light emission luminance of each lamp by variably controlling the duty ratio of the blinking pulse signal. (5) Each lamp drive circuit has a current value setting terminal for variably setting a drive current value input to each lamp. An output terminal of an integration circuit that integrates the blinking pulse signal and outputs a level signal corresponding to the duty ratio is connected to the current value setting terminal. The output of the integrating circuit acts to reduce the drive current value as the lamp ON period of the blinking pulse signal is longer.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS === Lamp Unit and Display Screen === As shown in FIG. 1A, 16 high-brightness LED lamps L1 to L16 are arranged at a close interval along an elongated pole type housing. One pole-type lamp unit Bi is arranged in a straight line. In the illustrated example, 32 lamp units B1 to B32 are prepared, and these are arranged almost in parallel at sparse intervals. The discrete columns of 32 lamp units B1 to B32 are arranged in a horizontal strip, and are arranged in a dense 16-dot vertical arrangement and a sparse 32-dot horizontal arrangement (1).
A physical screen of an intermittent dot row of (6 × 32) dot configuration is formed. 32 lamp units B in this embodiment
The arrangement interval of 1 to B32 is about four times the vertical interval of each LED lamp in one lamp unit Bi.

[0010] As shown in FIG. 1B, the sparse 32 dots of the physical screen of the intermittent dot row shown in FIG.
Each of the three dot rows is virtually arranged also in the row interval part of the row arrangement, and the (16 × 125) dot configuration is uniform with a dot density substantially equal to the dense 16-dot vertical arrangement. Assume a virtual screen with a dot distribution. That is, a screen assuming that three lamp units are arranged at equal intervals in a space between two adjacent lamp units is referred to as a virtual screen.

=== Principle Operation of Scroll Display === Physical Screen of Intermittent Dot Array of (16 × 32) Dots, Virtual Screen of Uniform Dot Distribution of (16 × 125) Dots, FIG. 1C shows the relationship between bitmap image data to be scroll-displayed on this screen. In the example of FIG.
An attempt is being made to scroll and display character images horizontally with an appropriate space. The character font in this example is (1
6 × 16) dot configuration.

Assume that image data for five characters to be displayed is bitmap data of 16 dots in one column and 125 dots in one line, including spaces between characters. This (16 × 125) dot image data is developed and displayed on a virtual screen having a uniform (16 × 125) dot distribution as shown in FIG. 1C. In actual display control, image data for 32 columns, which are selected from among image data for 125 columns, are distributed to 32 lamp units B1 to B32, and each lamp unit is distributed according to the data of 16 dots for each column. 16 in Bi
The control lamps L1 to L16 are driven.

In the control in which image data of 32 columns is selected from among the image data of 125 columns and distributed to the 32 lamp units B1 to B32, the column interval of the intermittent selection is set on the virtual screen. It is determined corresponding to the arrangement interval of each of the lamp units B1 to B32 arranged in a distributed manner. In other words, in the example of FIG. 1, one for every four columns in the image data.
A row is extracted and distributed to each of the lamp units B1 to B32.

Data for controlling and driving each of the lamps L1 to L16 of each of the lamp units B1 to B32 in accordance with the image data selected as described above while moving the bitmap image data developed on the virtual screen in the row direction. By repeating the process, as shown in FIG. 1C, a scrolling image having a density of 16 dots in one column and 125 dots in one line is visually recognized by a visual afterimage effect of a person who observes a virtual screen.

=== Overview of Display Control System === FIG. 2 shows an overall overview of the data processing system of the system of the present invention. Computer 1 at the center of the system
As a general computer can be used. A dedicated data transfer circuit 2 is connected to an expansion bus of the computer 1. This data transfer circuit 2 and 32 lamp units B
1 to B32 are daisy-chain connected by the transmission cable 3. Image memory 11 and transfer buffer 12 for scroll display processing on main memory of computer 1
Is set. The hard disk device 13 of the computer 1 stores a large number of image data to be scroll-displayed. The computer 1 and the data transfer circuit 2 correspond to the control unit described above. Also,
In FIG. 2, the expression of the power supply unit described above is omitted.

The lamp unit Bi drives the lamps L1 to L16 for 16 dots. The lamp unit Bi relays image data from the computer 1 and fetches image data addressed to itself, and supplies it to the lamp driving circuit 4. And a data processing circuit 5 that performs the processing. The data processing circuit 5 has an input terminal connector IN and an output terminal connector OUT,
The plug of the transmission cable 3 is fitted into this connector, and each element is daisy chained.

=== Signal sent from the data transfer circuit 2 === The details of the lamp drive circuit 4 and the data processing circuit 5 in the lamp unit Bi are shown in FIG. 3, and the data transfer circuit 2 of the computer 1 is connected to the daisy chain. FIG. 4 shows the relationship between the timing of the image data and the synchronizing signal flowing through the respective lamp units B1 to B32. 16 lamps L1 to L16 included in one lamp unit Bi
Are capable of emitting multicolor light composed of RGB collective lamps. In this embodiment, it is assumed that one lamp is driven by a total of three bits of data of one bit each of RGB. A set of three RGB bits is image data for one dot.

The data transfer circuit 2 sends a blinking pulse signal BCK, image data, a dot synchronization signal DCK, a unit synchronization signal UCK, and a frame synchronization signal FCK. Synchronous with each clock of the dot synchronization signal DCK, 3-bit parallel image data for one dot is serially output. The blinking pulse signal BCK is, for example, 100K
It is a square wave pulse signal of a sufficiently high frequency of about Hz, and the duty ratio of the blinking pulse signal BCK is variably controlled by the program processing of the computer 1 to adjust the light emission luminance of each lamp of the display device.

Image data for 16 dots to be distributed to the lamp unit Bi is continuously output. The image data for the first 16 dots is data addressed to the first lamp unit B1, the image data for the next 16 dots is data addressed to the second lamp unit B2, and the next 1
The image data and the dot synchronization signal DCK are sequentially output in such a manner that the image data for six dots is data addressed to the third lamp unit B3.

One clock of the unit synchronization signal UCK is output every 16 clocks of the dot synchronization signal DCK.
That is, the unit synchronization signal UCK is a clock synchronized with a break of one unit = 16 dots of serially output image data. In this embodiment, a physical screen is composed of 32 lamp units B1 to B32. From the data transfer circuit 2, 32 lamp units B1 to B3
When starting to output image data for one screen = 32 units to be distributed to 2, one clock of the frame synchronization signal FCK is output. That is, the frame synchronization signal FCK
Is a clock synchronized with a break of one screen = 32 units of serially output image data.

=== Control System in Lamp Unit Bi === As shown in FIG. 3, as the lamp driving circuit 4 of the lamp unit Bi, each of the 16 lamps L1 to L16 is represented by RGB 3-bit data. Driver 41 to drive
And a latch circuit 42 that supplies 16 dots of image data to the driver 41, and a shift register 43 that takes in the 16 dots of image data serially transferred and supplies the data in parallel to the latch circuit 42.

With the circuit configuration shown in detail in FIG. 3, the data processing circuit 5 of the lamp unit Bi relays image data from the computer 1 and fetches image data addressed to itself. The image data input from the preceding stage is slightly delayed by the delay circuit 51, and is sampled by the latch circuit 52 at the timing of the dot synchronization signal DCK to perform waveform shaping and timing adjustment. As well as data input,
Output to the subsequent stage. The dot synchronization signal DCK and the frame synchronization signal FCK input from the preceding stage are output toward the subsequent stage via the buffers 58 and 59, respectively. The unit synchronizing signal UCK input from the preceding stage is slightly delayed by the delay circuit 61, and is sampled by the latch circuit 62 at the timing of the dot synchronizing signal DCK to perform waveform shaping and timing adjustment.
Is output through the AND gate 55 to the subsequent stage.

The two flip-flops 53 and 54 are reset at the rise of the frame synchronization signal FCK from the preceding stage. At the rise of the unit synchronization signal UCK from the preceding stage, 2
Two flip-flops 53 and 54 read their respective D inputs. The D input of the first-stage flip-flop 53 is always “1”, and the Q output thereof is the D input of the second-stage flip-flop 54. Therefore, when the first unit synchronization signal UCK is input after the reset by the frame synchronization signal FCK, the flip-flop 53 is set (the Q output becomes "1"), and the flip-flop 54 remains reset. is there. Subsequently, when the second unit synchronization signal UCK is input, the flip-flop 54 is also set, and its Q output becomes “1”.
Once set, the flip-flops 53 and 54 remain set until the next frame synchronization signal FCK is input.

The unit synchronization signal UCK from the preceding stage is output to the subsequent stage via the AND gate 55. The Q output of the flip-flop 54 is applied to the AND gate 55 as a gate signal. As described above, the flip-flop 54 remains reset when the first unit synchronization signal UCK is input after the frame synchronization signal FCK is input, and is set at the rising edge of the second unit synchronization signal UCK. . Therefore, the first unit synchronization signal UCK does not pass through the AND gate 55, and the second and subsequent unit synchronization signals UCK pass through the AND gate 55 and are output to the subsequent stage.

The Q output of the flip-flop 53 and the inverted Q output of the flip-flop 54 are
Is ANDed with Therefore, the frame synchronization signal F
The output of the AND gate 56 becomes "1" only during the period from the rising point of the first unit synchronization signal UCK after the input of CK to the second rising point. When the output of the AND gate 56 becomes "1", the dot synchronization signal DCK
Is applied to the clock input terminal of the shift register 43 through the AND gate 57. The image data having passed through the latch circuit 52 is shifted and input to the shift register 43 in synchronization with the clock input at this time.

The description will be made once again. After the frame synchronization signal FCK is input from the previous stage, the dot synchronization signal DCK from the previous stage is supplied to the shift register 43 for a period from the rising time of the first unit synchronization signal UCK input from the previous stage to the second rising time. The image data from the preceding stage is shifted and input to the shift register 43 in synchronization with the clock. During this period, image data for 16 dots = 1 unit is input from the preceding stage in synchronization with the 16 clocks of the dot synchronization signal DCK. The image data for one unit is read into the shift register 43.

Here, the interval period of the frame synchronization signal FCK generated by the computer 1 is called a frame cycle.
32 issued by the computer 1 in the frame cycle
For the unit synchronization signal UCK issued, UCK
1, UCK2, UCK3,... UCK32. The first-stage lamp unit B1 closest to the computer 1 has 32 unit synchronization signals UCK1, UCK2, U
CK3,..., UCK32 are all input, and UCK1
The image data for one unit input during the period of UCK2 is taken into the shift register 43 of the lamp unit B1. For the second-stage lamp unit B2, UCK
1 is not transmitted, and UCK2, UCK3, UCK4, ...
UCK32 is input, and one unit of image data input during the period of UCK2 to UCK3 is the lamp unit B.
2 shift register 43. UCK2 is not transmitted to the third-stage lamp unit B3.
CK3, UCK4, UCK5,... UCK32 are input, and the image data of one unit input during the period from UCK3 to UCK4 is taken into the shift register 43 of the lamp unit B3. And the last stage lamp unit B
32, only UCK32 is input, and UCK3
The image data for one unit input during a period from the input point of No. 2 to the input point of the frame synchronization signal FCK at the beginning of the next frame cycle is taken into the shift register 43 of the lamp unit 32.

As described above, the image data for one screen = 32 units serially output from the computer 1 during one frame cycle is converted into 32 lamp units B1.
To B32 in that order, and taken into the respective shift registers 43. When the computer 1 outputs a frame synchronization signal FCK indicating the start of the next frame cycle, all the lamp units B1 to B32
, The frame synchronization signal FCK is
2, and the image data of the shift register 43 is read into the latch circuit 42. At the same time, the lamps L1 to L16 are driven to emit light in accordance with the image data read into the latch circuit 42. By repeating the above-described data processing of the frame cycle at a high speed, a scrolling display of a tracking interpolation type is realized on the screen of the intermittent dot row composed of the 32 lamp units B1 to B32.

In the embodiment of FIG. 3, the waveform shaping and the timing adjustment are performed by slightly delaying the image data from the preceding stage by the delay circuit 51 and sampling by the latch circuit 52 in accordance with the dot synchronization signal DCK. Thus, even when a system is configured by connecting a large number of lamp units in a daisy chain, data can be correctly relayed and transferred by each unit, and each unit can correctly receive data intended for itself.

=== Light Emission Brightness Control System === As shown in FIGS. 2 and 3, the blinking pulse signal BCK sent from the data transfer circuit 2 is first supplied to the lamp unit B1.
And is sent out after being delayed by an appropriate phase angle of one cycle or less by the delay circuit 65 in the unit B1 and is then introduced into the next lamp unit B2 and similarly delayed by the delay circuit 65 in the unit B2. It is sent out and introduced into the next lamp unit B3. As described above, the system configuration is such that the blinking pulse signal BCK is serially transferred while delaying the phase angle little by little for all the lamp units.

In each lamp unit Bi, the blinking pulse signal BCK before being delayed by the delay circuit 65 is input to the enable terminal Enb of the driver 41. In this embodiment,
As a driver for driving the LED lamp of each lamp unit Bi, a lamp driving IC 68 called “16-bit shift register latch constant current driver [model number: TB62706AN (manufactured by Toshiba)]” is used. FIG. 5 shows this lamp drive I.
It shows C68 and its peripheral circuits. Each lamp driving IC 68 includes the driver 41, the latch circuit 4
2 and the shift register 43, and the LED lamp L
1 to L16 are individually controlled to emit light, and the sixteen lamps L1 to L16 of each unit Bi are sufficiently synchronized with the blinking pulse signal BCK (for example, a square wave pulse of about 100 KHz) input to the enable terminal Enb. Is driven to blink in a short cycle. Blinking pulse signal BCK of this embodiment
Indicates that the “Lo” level period is the lamp ON period and the “H” level period
The “i” level period indicates the lamp OFF period. The computer 1 can appropriately adjust the light emission luminance of each lamp unit Bi by changing the duty ratio of the blinking pulse signal BCK. For example, an operation to change the display brightness between night and day is performed.

=== Overcurrent Protection of LED Lamp === In this embodiment, the enable terminal En of the lamp driving IC 68 is used.
Even if an abnormal blinking pulse signal is input to b, LE
A configuration is provided to prevent the LED lamp from being damaged by an excessive current flowing through the D lamp. This configuration will be described in detail below.

In order to prevent damage to the LED lamp, the lamp drive I
The current value setting terminal 70 of C68 is used. As shown in FIG. 5, an integrating circuit 72 is connected to the current value setting terminal 70 via a setting resistor R1. The integration circuit 72 integrates the blinking pulse signal BCK and outputs a level signal corresponding to the duty ratio. The integrating circuit 72 of this embodiment is configured using an operational amplifier (op-amp) 74 as an inverting amplifier. The inverting amplifier connects the non-inverting input terminal 74a of the operational amplifier 74 to ground, connects the input resistor R2 to the inverting input terminal 74b, and connects the inverting input terminal 74b to its output terminal 74c to connect a feedback resistor. R3 and feedback capacitor C are connected in parallel. The blinking pulse signal BCK is input to the inverting amplifier via the input resistor R2, and its pulse level is time-averaged and inverted and output to the output terminal 74c of the operational amplifier 74. Here, the inverted signal is a level signal whose level fluctuates according to the duty ratio of the blinking pulse signal BCK. The signal level decreases as the duty ratio of the blinking pulse signal BCK increases, while the duty ratio of the blinking pulse signal BCK decreases. The smaller the ratio, the higher the signal level. By outputting such a signal to the output terminal 74c of the operational amplifier 74,
The current value of the current flowing through the setting resistor R1 is increased or decreased according to the duty ratio of the blinking pulse signal BCK.
The amount of the drive current flowing through 1 to L16 is increased or decreased. The minimum value of the drive current is the resistance value of the setting resistor R1, while the increase / decrease width of the drive current is set by the amplification factor of the integration circuit.

In this embodiment, the lamp is turned on when the blinking pulse signal BCK is at the level "Lo" and the lamp is turned off when the level is "Lo". Therefore, the lamp ON period of the blinking pulse signal BCK, that is, the "Lo" level The longer the period, the higher the signal level at the output terminal of the operational amplifier, the smaller the driving current of the LED lamp, and the more the LED lamp is not damaged. On the other hand, when a signal that continuously turns off the LED lamp, that is, a signal whose pulse level is continuously “Hi” is input, the current value of the driving current of the LED lamp is set to the maximum value. However, since the LED lamp is turned off by the enable terminal Enb, there is no need to damage the LED lamp.

Another excellent effect of the present embodiment is that power consumption can be reduced during low-luminance light emission as compared with the case where the LED lamp is driven at a constant current. That is, the light emission luminance of the lamp is usually determined by the relationship between the drive current and the ON period. You can adjust the amount of drive current,
Also, by adjusting the length of the ON period, a desired light emission luminance is set. Even if the ON time of the LED lamp is shortened, the same emission luminance can be obtained by increasing the drive current.

However, in a device utilizing the afterimage effect of the human eye, such as the tracking interpolation type scroll display device of the present invention, when the LED lamp is caused to emit light with low luminance, the driving time is longer than when the lamp ON period is lengthened. It has been empirically confirmed that the larger the current value, the brighter the external appearance even with the same power consumption. That is, if the same visual brightness is to be ensured, the power consumption can be reduced by increasing the drive current rather than by increasing the lamp ON period.

FIG. 6 is a graph showing the results of a test performed to confirm this. In this test, LE
The apparent brightness of the tracking interpolation scroll display device when the duty ratio was increased or decreased while the power consumption of the D lamp was kept constant, that is, the visual brightness was examined. Since the visual brightness cannot be measured by the measuring device, in addition to the test display device, a comparative display device of the same type and the same type in which the LED lamp operates at a duty ratio of 100% and the driving current thereof can be variably set is prepared. The power consumption of the display device for comparison when the drive current is adjusted so that the brightness of the display device for comparison is approximately the same as that of the display device for test by comparing the display device for test with the display device for comparison. The power consumption of the display device was set to 1 and the comparison was made. From this figure, it can be seen that as the duty ratio of the LED lamp of the display device for test decreases, the power consumption of the LED lamp of the display device for comparison increases, and the LED lamp of the display device for test becomes brighter. Therefore, when the LED lamp is made to emit light with low luminance by reducing the duty ratio, it is understood that increasing the driving current requires less power consumption and is economical. In the tracking interpolation type scroll display device according to the present embodiment, the driving current increases as the LED lamp emits light with low luminance, so that the power consumption is reduced as compared with the conventional method in which the LED lamp is driven at a constant current. Can be.

=== Other Embodiments === When the blinking pulse signal BCK is at the level “Lo” and the lamp O
If the signal is a signal for turning on the lamp at the FF or at the level “Hi”, an integration circuit is configured to output the integrated output of the blinking pulse signal without inverting it.

As another lamp driving IC used in the lamp driving circuit, "16-bit shift register latch constant current driver" [TB62701N (manufactured by Toshiba)]
Is mentioned.

[0040]

According to the present invention, the current value of the lamp driving current is increased or decreased according to the duty ratio of the blinking pulse signal, and the longer the lamp ON period of the blinking pulse signal, the smaller the driving current. Therefore, even if a signal for continuously turning on the lamp is input to the enable terminal of the lamp drive circuit and the lamp is continuously turned on, the drive current flowing through the lamp can be limited to a small value, and the lamp can be controlled to be small. No need to break.

Further, since the driving current is increased as the lamp emits light with low luminance, less power consumption is required as compared with the case where the lamp is driven at a constant current.

[Brief description of the drawings]

FIG. 1 shows a physical screen (a) according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of a virtual screen (b) and a scroll display screen (c).

FIG. 2 is a diagram showing an overall outline of a data processing system of an embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of one lamp unit according to the system of one embodiment of the present invention.

FIG. 4 is a timing chart of signals output from the data transfer circuit to the daisy chain connected lamp units in the embodiment.

FIG. 5 is a circuit diagram showing a lamp driving circuit of the present invention and a circuit configuration around the lamp driving circuit.

FIG. 6 shows a tracking interpolation type scroll display device according to the present invention.
FIG. 9 is a graph showing that when the drive current is increased as the duty ratio of the LED lamp is reduced and light emission with low luminance is performed, power consumption is reduced even with the apparently same brightness.

[Explanation of symbols]

 L1 to L16 LED collective lamp Bi, B1 to B32 Pole type lamp unit 68 Lamp drive IC 70 Current setting terminal 72 Integrating circuit

Claims (1)

[Claims] 1. A tracking interpolation type scroll display device characterized by overcurrent protection of a display lamp, and has the following requirements (1) to (5). (1) One or more control units and a number of lamp units connected to the control units via a transmission system are provided. (2) A large number of lamp units are arranged in a predetermined layout at intervals from each other. Many lamps are arranged in each lamp unit in a predetermined layout. Each lamp is configured as one pixel, and one display screen is formed by the entire lamp unit. (3) Each lamp unit has a lamp drive circuit that individually controls light emission of each lamp of the lamp unit based on display data transmitted from the control unit. (4) A sufficiently high-frequency blinking pulse signal transmitted from the control unit is input to the enable terminal of each lamp drive circuit, and each lamp is driven to blink in a sufficiently short cycle in synchronization with the blinking pulse signal. . The control unit changes the light emission luminance of each lamp by variably controlling the duty ratio of the blinking pulse signal. (5) Each lamp drive circuit has a current value setting terminal for variably setting a drive current value input to each lamp. An output terminal of an integration circuit that integrates the blinking pulse signal and outputs a level signal corresponding to the duty ratio is connected to the current value setting terminal. The output of the integrating circuit acts to reduce the drive current value as the lamp ON period of the blinking pulse signal is longer.