JPH11305416A - Method for producing semiconductor device and method for producing photomask - Google Patents

Abstract

PROBLEM TO BE SOLVED: To produce a photomask which has no defect, where the distortion of a transfer pattern is reduced and whose superposing accuracy is high by distorting the stage coordinate systems of a plotting device and an inspecting device by a specified amount and comparing and inspecting patterns respectively formed in a pair of areas on the same photomask base plate. SOLUTION: By performing the correction of an optical proximate effect to the design data of a semiconductor device (100), the data are converted into pattern data for electron beam plotting 101), and an integrated circuit pattern and a correction pattern are plotted on the mask base plate. In such a case, after the pattern data of a pair of rectangular areas are stored in a buffer memory (102), the pattern data are read out and shot-resolved, and each pattern data are plotted in a pair of rectangular areas (103 and 104), so that the photomask is produced (105). Thus, the patterns actually formed are compared to inspect the outside appearance of the pattern (106). The quality of the outside appearance of the integrated circuit pattern is surely and easily inspected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which an integrated circuit pattern is formed by using light reduction projection exposure, and more particularly to a modified (oblique) illumination and optical proximity effect correction pattern for a photomask. The present invention relates to a technique that is effective when applied to the manufacture of a semiconductor device that forms a fine resist pattern equal to or less than the exposure wavelength by adding a phase shifter for giving a phase difference to the exposure light.

[0002]

2. Description of the Related Art As the miniaturization of semiconductor devices progresses and circuit element and wiring design rules become on the order of submicrons, i.
In a photolithography process in which an integrated circuit pattern on a photomask is transferred to a semiconductor wafer using light such as a line (wavelength: 365 nm), a decrease in pattern transfer accuracy has become a serious problem. As a means for remedying such a problem, a light proximity effect is obtained by adding a fine pattern to a portion where the light intensity is reduced by projection exposure to a mask pattern or by deleting a fine pattern at a portion to be emphasized. There are a correction technique and a phase shift technique for providing a phase difference to light transmitted through a mask.

[0003] Regarding the optical proximity effect correction technique, for example, Ito et al., "Correction of projection distortion of photomask pattern for 1 μm process", Transactions of the Institute of Electronics, Communication Engineers, Japan, May 1985, Vo.
l. J68-CNo5, pages P325 to 332, discloses an optical proximity effect correction technique in which a small rectangle is added to a corner of a rectangular hole and transferred. In the inspection of a photomask using the above-described optical proximity correction technique, there is a problem that the dimensions of the correction pattern become finer and it is difficult to inspect and correct the mask pattern.

With respect to the phase shift technology, for example, Japanese Patent Publication No. 62-59296 discloses a transparent film (phase shifter) provided on one of a pair of light transmitting regions sandwiching a light shielding region on a mask, and the pair of light transmitting regions. There has been disclosed a phase shift technique in which the phases of two lights transmitted through each other are inverted with each other to reduce the light intensity at the boundary between the two lights on the wafer.

In the inspection of the photomask used in the above-described phase shift technique, it has been pointed out that finer mask defects are transferred, and it is difficult to inspect and correct the pattern of the phase shifter. Regarding the above inspection, for example, Japanese Patent Application Laid-Open No. 4-31047 discloses a technique for efficiently performing a step of extracting a mask defect and a step of judging pass / fail in the same apparatus. In addition, it has been pointed out that a shift in a transfer pattern position occurs due to a curvature of field or distortion of a projection lens during exposure by a light reduction projection exposure apparatus, and it has been proposed to reduce aberration distortion of the lens. ing. On the other hand, in order to solve this problem, for example, Japanese Patent Publication No. 62-58621 discloses that a plurality of exposure distortion measurement marks are formed on a sample by a light reduction projection exposure apparatus, and the exposure distortion measurement marks are formed by an electron beam exposure apparatus. A technique has been disclosed in which the amount of exposure distortion is determined in advance by measuring the position of, and electron beam exposure is performed in accordance with the exposure distortion. Further, Japanese Patent Publication No. 61-24231 proposes a technique for inversely correcting exposure distortion of an optical reduction projection exposure apparatus on a mask to reduce transfer pattern distortion.

[0006] Further, during exposure by the light reduction projection exposure apparatus, a phenomenon occurs in which the dimensions and shape of the transfer pattern are distorted due to spherical aberration, coma aberration, astigmatism, etc. of the lens. These changes in dimensions and shapes have pattern dependence, and become remarkable at the end of a repetitive pattern such as line and space. As a countermeasure for eliminating the influence of such aberration, for example, Japanese Patent Application Laid-Open No. 4-60547 discloses that a dummy pattern is added to a line and space end. Japanese Patent Application Laid-Open No. 6-29180 describes a technique for correcting distortion by using a pattern dimension error amount as a correction amount of mask data.

[0007]

In the inspection of a photomask (including a reticle) used in the above-described optical proximity correction technology, the size of the correction pattern is reduced to about one-third or less of the size of the circuit pattern. It is difficult to inspect and correct the mask pattern. Also, with respect to inspection of a phase shift mask in which a phase difference is provided to transmitted light of a photomask, it is difficult to inspect and correct a mask pattern of a phase shifter. Transfer defects occur on the wafer, which is an important problem that lowers the production yield of semiconductor devices.

In the technique disclosed in Japanese Patent Application Laid-Open No. 4-31047, it is difficult to inspect the appearance of an optical proximity correction mask or a mask having a phase shifter edge in a transmission area.
Japanese Patent Application Laid-Open No. 4-345163 discloses a method for inspecting a phase shift mask using three types of resized data. Although it can be applied to a matched phase shift mask, it cannot be applied to a mask having a phase shifter edge in a transmission region not adjacent to a light-shielding pattern. In addition, the dimension and shape errors of the pattern due to lens distortion and aberration have different values depending on the exposure apparatus and exposure conditions used.
It is not realistic to perform reverse correction on a mask by correcting pattern data.

Further, at present, in the manufacture of a semiconductor device, exposure is performed by combining the above-described phase shift mask and proximity effect correction mask by processes. FIG. 32 schematically shows a comparison between the phase shift exposure method and the oblique illumination exposure method. This shows that it is necessary to optimally adjust the illumination conditions of the exposure light on the photomask surface during projection exposure according to each integrated circuit pattern formed on the photomask. By changing the illumination conditions in accordance with the integrated circuit pattern, a difference occurs in the optical path from the photomask surface to the semiconductor wafer, which causes positional distortion in the transferred pattern. Even if the same light reduction projection exposure is used, a difference in transfer pattern position becomes a problem due to a change in reduction magnification and a difference in exposure method between the stepper and the scanner.

With respect to the above-described pattern position distortion, when a method of reversely correcting and distorting a circuit pattern formed on the mask substrate as described in JP-B-61-24231 is applied to an actual integrated circuit pattern, It has been found that the external inspection of the mask pattern becomes substantially impossible. In a semiconductor device mask manufacturing technique, an integrated circuit pattern data formed on a mask defines a basic circuit element pattern as a primary cell, a two-dimensional array of the primary cell, and a secondary array including other secondary cells. It has a hierarchical data structure with a tertiary cell and the like. FIG. 33 shows an example of the configuration of integrated circuit data having a hierarchical structure. When converted to mask data, the basic circuit element pattern becomes
This is a collection of data in which beam shot conditions at the time of mask drawing are added to graphic data such as a rectangle determined by the width, length, and coordinates. When the data has a hierarchical structure, the data amount can be significantly reduced even for a large-scale integrated circuit pattern.

When a mask on which a correction pattern for optical proximity effect correction is formed or a mask on which a phase shifter is formed is manufactured using the above-described mask manufacturing technology, the exposure distortion is inversely corrected using a pattern on the mask. Then, it is necessary to distort the position coordinates of the pattern data in accordance with the position coordinates on the photomask substrate, and the processing for that becomes extremely complicated. Even if the process of distorting the position coordinates of the pattern data is performed, the conversion process to the drawing data takes an enormous amount of time and is not feasible unless the above hierarchical structure is maintained. Further, it becomes impossible to perform a visual inspection by comparing the pattern formed on the photomask with the design data of the integrated circuit pattern. If a photomask that cannot be visually inspected is applied to projection exposure, it is not possible to prevent defect transfer during exposure.

Further, in a mask using a correction pattern for optical proximity effect correction, a minute rectangular pattern is formed as a part of the correction pattern. As a circuit pattern formed on a photomask is miniaturized, there arises a problem that it becomes difficult to extract an abnormal portion such as a pattern defect or an attached foreign matter. The mask pattern defects to be considered here include:
Drawing pattern error, occurred during process processing,
The light-shielding film is missing or remaining, and the attached foreign matter is the remaining residue after removal of the resist. 2. Description of the Related Art A semiconductor device is manufactured by transferring a circuit pattern to each layer formed on a semiconductor wafer by patterning using a plurality of photomasks by reduction projection exposure. Conventionally, when transferring a pattern formed on a photomask to a wafer, a method has been proposed that can efficiently correct the dimensional distortion, shape distortion, and positional distortion of the pattern formed on the wafer and inspect the appearance of the mask pattern. Had not been.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to use a mask to which a correction pattern for correcting the optical proximity effect is added, a mask to which a phase shift technique is applied, and the like. In the manufacturing process of a semiconductor device that forms a circuit pattern by performing light reduction projection exposure, a transfer technology that reduces projection distortion of a transfer pattern, improves the accuracy of a circuit pattern formed on a semiconductor wafer, and eliminates defect transfer. To provide. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION A pattern forming method according to the present invention is a method of manufacturing a semiconductor device which corrects projection distortion of a reduction projection exposure apparatus and transfers an integrated circuit pattern on a photomask substrate onto a semiconductor wafer. In the process, in order to correct dimensional distortion or pattern shape distortion of the transfer pattern, pattern data forming a circuit pattern and correction pattern data in which a fine pattern is added or deleted from each pattern are created, and the mask drawing apparatus By drawing each pattern data, forming a distorted pattern on the mask, the first projection distortion correction to reduce dimensional distortion or pattern shape distortion of the transfer pattern, and the field curvature distortion of the projection exposure optical system In order to correct the distortion of the projection position coordinates of the transfer pattern, each position may be And performs a predetermined a distorted pattern formed in a state of being a vector quantity shift, the second projection distortion correction to reduce the distortion of the projection position coordinates of the transfer pattern corresponding to the.

When inspecting a mask that has been corrected for the distortion of the position coordinates, the inspection is also performed on the stage coordinates of the mask inspection apparatus with a predetermined vector shift corresponding to each position. Things. If the mask substrate holding method in the mask drawing apparatus and the mask substrate holding method are the same, the shift amount of each position coordinate can be the same, but in practice, each correction amount is given.

The area to be corrected is a rectangular area of an integrated circuit pattern formed on a photomask, and another area where the same correction is repeated in the X-axis direction or the Y-axis direction on the substrate. Limit to the area where the rectangular area exists. When drawing the corrected integrated circuit pattern on the mask, the stage position coordinate system on which a photomask substrate is mounted is corrected so as to correct the pattern position distortion, and then the pattern of the rectangular area is corrected. The data is stored in the buffer memory of the electronic beam drawing apparatus, and the shot is decomposed into exposure data that can be filled and exposed by combining an electron beam having a sectional shape of one of a graphic shape, a rectangular shape, and a spot shape. Then, drawing is performed on a part of the area on the photomask substrate, the shot data is again decomposed into exposure data based on the pattern data, and drawn on another area on the photomask substrate. An auxiliary pattern such as a pattern and an alignment mark is formed.

When inspecting the appearance of the mask on which the pattern is formed, after correcting the stage position coordinate system on which the photomask is mounted so as to correct the pattern position distortion, the same correction as that for the rectangular area is performed. A pattern appearance inspection is performed on the other rectangular area by comparing the formed patterns. A part of the pattern on the photomask other than the pair of rectangular areas subjected to the same correction is patterned on the photomask.
A pattern appearance inspection is performed by a comparison inspection with design data on which a pattern is formed.

The difference between the two methods of the comparative inspection is that the mask pattern is corrected or the attached foreign matter is removed so that the mask pattern is substantially the same, and the appearance quality is confirmed. In the above, the integrated circuit pattern of the mask is exposed on a semiconductor wafer by using a reduction projection exposure apparatus to form an integrated circuit pattern. Thereby, the appearance inspection of the photomask can be realized. Also, with respect to the pattern formed on the wafer, the positional accuracy is improved, so that the appearance inspection of the wafer becomes easy.

When a pattern is formed by exposing an integrated circuit pattern formed on a photomask on a semiconductor wafer by light reduction projection exposure, a phase shift is provided to give a phase difference to light transmitted through the photomask. The means may include forming a phase shift boundary in the transmissive area or forming a finely sized auxiliary opening in the light-shielded area that does not itself form a bright image by the integrated circuit pattern on the mask. When performing on a rectangular unit area and a unit area having a similar pattern existing in the X-axis direction or the Y-axis direction on the substrate,
The pattern data of the pair of rectangular unit areas is stored in a buffer memory of an electron beam exposure apparatus, and an electron beam having a sectional shape of one of a graphic shape, a rectangular shape, and a spot shape is combined. If a pattern is formed on the photomask substrate by decomposing shots into exposure data that can be filled and exposed and drawing on a partial area on the photomask substrate, the mask inspection allows the pair of rectangular areas to be formed. The pattern comparison inspection described above makes it possible to perform a pattern appearance inspection. For the circuit patterns in the regions other than the pair of regions, a pattern appearance inspection is performed by a comparison inspection with design pattern data on which a mask pattern is formed.

The difference in the above-mentioned comparative inspection is obtained by irradiating the photomask with light after correcting the pattern or removing the adhered foreign matter, and using the interference of transmitted light to form an integrated circuit pattern on the semiconductor wafer. It forms an image on the top to form a pattern. The patterns formed on the photomask are compared and collated, and an abnormal part is extracted, so that a mask having a fine optical proximity effect correction pattern and a mask having a fine phase shifter pattern have high efficiency in appearance quality. Inspection becomes possible. Thereby, the resolution and depth of focus of the projection exposure can be increased, and the manufacturing yield of the semiconductor device can be improved.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions in all drawings for describing the embodiments are denoted by the same reference numerals.) , And the repeated explanation is omitted).

(Embodiment 1) FIG. 1 is a flow chart for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is an overall plan view of a photomask used in the method of manufacturing the semiconductor device of FIG. FIG. 3 is a plan view of a principal part of the photomask for explaining the optical proximity effect correction pattern formed on the photomask of FIG. 2, and FIG. FIG. 5 is a diagram illustrating an example of a position coordinate error in which the position error of the mark pattern is transferred and enlarged, and FIG. 5 is an explanatory diagram of a correction vector of a pattern formed by correcting the position coordinate error of FIG. 6 is an explanatory diagram of a map correction method for correcting the position coordinate error of FIG. 5, FIG. 7 is an explanatory diagram of a mask drawing apparatus used in the method of manufacturing the semiconductor device of FIG. 1, and FIG. 8 is a diagram of the semiconductor device of FIG. By manufacturing method Illustration of a mask inspection apparatus are, 9
Is an explanatory view of the electron beam exposure apparatus of FIG. 1, and FIGS.
Is an explanatory view of a main part of the electron beam exposure apparatus of FIG. 9, and FIGS.
FIG. 19 is a cross-sectional view of a main part of a specific semiconductor device during the manufacturing process of the semiconductor device of FIG. 1, and FIG. 20 is a flowchart illustrating a photolithography process extracted from the manufacturing process of the semiconductor device of FIGS.

First, the structure of a photomask used in the exposure step of the method of manufacturing a semiconductor device according to the first embodiment will be described with reference to FIG. The photomask 1 is, for example, a DRAM (Dynamic
This is used when exposing an integrated circuit pattern of a random access memory onto a semiconductor wafer (a photoresist film on the semiconductor wafer; the same applies to the following description), and is an integrated circuit pattern having a size five times the size of an actual integrated circuit pattern. This is a reticle on which an original image is formed. The integrated circuit pattern formed on the photomask 1 is transferred to a semiconductor wafer through a reduction projection optical system described later.

The mask substrate 2 constituting the photomask 1 is made of, for example, a square transparent synthetic quartz glass or the like. Are arranged side by side in parallel. Each of the chip transfer areas A and B is one DRAM
It corresponds to the amount of chip transfer. Chip transfer area A, B
The reason for disposing the two is to improve the throughput and to inspect the photomask 1 with a die-to-die.
This is because even if one of them is damaged, the other may remain.

The chip transfer areas A and B are formed by being partitioned by a frame-shaped light-shielding band 3 (shown by relatively dark hatching). The light-shielding band 3 is made of, for example, chrome (C
r) and the like. The chip transfer area A includes the memory circuit areas A11, A12, A21, A
22 (indicated by relatively thin hatching) and a peripheral circuit area A00 (indicated by hatching) surrounding them, and the chip transfer area B includes memory circuit areas B11, B12, B21, and B22 (relative hatching). ) And peripheral circuit area B surrounding them.
00 (shown by hatching). The memory circuit areas A11, A12, A21, A22, B11, B12,
In B21 and B22, patterns for transferring a pattern for forming a memory circuit on a semiconductor wafer are arranged. The peripheral circuit areas A00 and B00 have D
A pattern for transferring a pattern for forming a peripheral circuit of the RAM is arranged.

In the first embodiment, it is assumed that an optical proximity effect correction pattern (hereinafter, simply referred to as a correction pattern) is arranged in, for example, the memory circuit area A11 of the photomask 1. That is, the memory circuit area (first area) A
Reference numeral 11 denotes a rectangular unit area where correction for adding a correction pattern other than the actual integrated circuit pattern has been performed. An area having the same pattern as the pattern of the memory circuit area A11 (including the integrated circuit pattern and the correction pattern) is provided on the same photomask 1. That is, the photomask 1 includes a pair of rectangular regions having the same pattern. The pattern of the memory circuit area A11 (including the integrated circuit pattern and the correction pattern) and, for example, one of the memory circuit areas (second areas) A12 and A21, or the pattern of B11 in another chip transfer area B (the integrated circuit pattern) And the correction pattern) are the same, and each proximity effect correction is limited to be performed at the same position coordinates.

The reason why a pair of rectangular regions having the same pattern (including the integrated circuit pattern and the correction pattern) are provided in the same photomask 1 as described below is as follows.
By comparing actual patterns (including an integrated circuit pattern and a correction pattern) of each of a pair of rectangular regions,
This is to ensure that the quality of each pattern (including the integrated circuit pattern and the correction pattern) can be inspected reliably and easily.

However, the peripheral circuit area B00 of one chip transfer area B and all of the memory circuit areas B11, B12, B21 and B22 are respectively the peripheral circuit area A00 and the memory circuit areas A11 and A12 of the other chip transfer area A. A21 and A22 need not be the same. The condition may be any pattern as long as the pattern (including the integrated circuit pattern and the correction pattern) is the same for each rectangular area subjected to the optical proximity effect correction.

One of the pair of rectangular regions (for example, the memory circuit region B11) is
The image may be prevented from being transferred onto the semiconductor wafer by arranging it in a non-transfer area or devising it not to be transferred during exposure. In this case, only at least one of the pair of rectangular regions need not be transferred to the semiconductor wafer. Of course, the entire chip transfer area B may not be transferred to the semiconductor wafer.

Next, a specific example of the optical proximity effect correction pattern will be described with reference to the drawings. Optical proximity effect correction technology is used in places where the light intensity of the transferred pattern is partially reduced or emphasized due to exposure optical system distortion or exposure light interference.
A fine pattern that does not form a bright image on a semiconductor wafer by exposure by itself is arranged at a necessary portion of the integrated circuit pattern of the photomask 1 or a part of the integrated circuit pattern is deleted. This is a technique for correcting distortion of an image transferred to a semiconductor wafer. The pattern exposed on the semiconductor wafer is corrected so as to be substantially similar to the design data of the integrated circuit pattern before the optical proximity correction is performed.

FIG. 3 shows a pattern for transferring a connection hole pattern in a photomask, for example.
FIG. 3A corresponds to the design data of the integrated circuit pattern, which is a connection hole pattern TH before the proximity effect correction is performed, and is a pattern to be formed on a semiconductor wafer. FIG. 3B shows a pattern (connection hole pattern TH and correction pattern H1) on which optical proximity correction has been performed. FIG. 3C shows a pattern (connection hole pattern TH, correction pattern H1, and phase shifter pattern H2) after the addition of a phase shifter for inverting the phase of transmitted light as a second-stage correction.

The connection hole pattern TH is formed, for example, in a planar square shape. The dimension of the connection hole pattern is about the exposure wavelength or less, for example, about 1.5 μm × 1.5 μm. The correction pattern H1 is arranged so that a part thereof overlaps or touches four corners of each connection hole pattern TH. This is because when the connection hole pattern TH is to be transferred onto a semiconductor wafer, the light intensity is reduced at the corners of the transfer pattern, and the shortage of the light intensity is compensated for. The correction pattern H1 is formed, for example, in a plane quadrangular shape, and its size is about 1/3 or less of the size of the connection hole pattern TH.

The second phase shifter patterns are arranged to face four sides of each connection hole pattern TH. The addition of the phase shifter will be described in detail in another embodiment. By adding the phase shifter, the size of the correction pattern H1 can be increased to about 1/2.

The correction of the size and shape distortion of the transfer pattern can be performed by creating pattern data for correction on the pattern data corresponding to the circuit pattern by computer processing.

FIG. 4 shows an example in which 10 mm
An example of a position coordinate error in which a reference mark pattern two-dimensionally arranged at approximately equal intervals is transferred by reduced projection exposure and the position error of the mark pattern is enlarged and displayed. The position coordinate error in FIG. 4 is a distortion obtained by combining the field curvature distortion of the optical reduction projection lens, the top aberration distortion, the deflection of the mask substrate, and the like. The deflection of the mask substrate occurs when drawing a pattern on a mask, when measuring the position coordinates of the pattern, and when exposing, but it is theoretically analyzed according to the thickness and material of the mask substrate, It has been optimized and reduced.

FIG. 4 may be considered as a positional error with respect to a base pattern already formed on a semiconductor wafer. In some cases, the difference between the optical reduction magnification and the difference between the scanner and the stepper is combined. This is performed to measure misregistration due to various causes in order to improve the overlay accuracy with the underlying pattern generated when performing the reduced projection exposure.

The value of the top aberration distortion changes depending on the size and arrangement of the pattern formed on the photomask. In this case, the reference pattern formed on the wafer has a pattern width dimension about the wavelength of the exposure light and a pattern length dimension. It has a cross shape with a size of about 100 m. The reference pattern of the above dimensions is 1
By setting the cross-girder shape shifted by about 2 m, the measurement error of the pattern position coordinates can be reduced somewhat.

FIG. 5 is an explanatory diagram of a correction vector of a pattern formed by correcting the position coordinate error of FIG. 4 on a photomask by distortion correction. As compared with FIG. 4, when the reduction magnification is multiplied, the position correction vector becomes opposite at each lattice point on the wafer. By performing the reverse correction on the photomask as shown in FIG. 5, the position error on the wafer can be greatly reduced, and the overlay accuracy of the integrated circuit pattern can be improved. That is, by distorting the circuit pattern formed on the mask, it is possible to alleviate the positional deviation of the pattern generated on the wafer.

FIG. 6 is an explanatory diagram of a map correction method for correcting the position coordinates in order to correct the position shift in FIG. FIG. 4 shows a correlation between an uncorrected linear coordinate system and a map corrected coordinate system. The position coordinate shift amount is given to the pattern on the photomask in units of mesh at equal intervals. The position coordinate shift amount is set independently of each other depending on the reduction projection exposure apparatus to be used and exposure conditions.

FIG. 7 shows the position coordinate map of FIG.
1 schematically shows a method of drawing a circuit pattern on a photomask. The position coordinates of the stage on which the photomask is mounted are measured by laser interference, and the measured values are
The coordinates are converted by the method shown in FIG. The stage position and the beam position are controlled by the coordinate conversion values.

In FIG. 6, the shift amount at each lattice point is given. In the mask drawing apparatus, the correction value is approximated by a curve. Although an electron beam is used here, the drawing area is divided into a main field, a subfield, and a sub-subfield, and a correction value is distributed to each field. The sub-subfield is about 80 m or less, and by correcting the sub-subfield center value, the correction difference between the grid points in the correction map of FIG. 6 becomes 1/10 or less.
In accordance with this, drawing can be performed without distorting the shot position of the circuit pattern in the sub-subfield. The shot position may be distorted in the sub-subfield, but in this case, it is difficult to calibrate the beam deflection width. According to this method, it is possible to perform drawing while distorting the pattern position coordinates. The method of drawing a circuit pattern by correcting the pattern data itself will be described later in detail.

A specific pattern inspection method for the photomask 1 will be described with reference to FIG. FIG. 8 schematically shows a mask appearance inspection method when a circuit pattern is formed on the photomask with distortion. The photomask is mounted on a stage capable of measuring position coordinates by laser interference. The laser measurement value performs the inverse conversion of the position coordinate map correction of FIG. The photomask surface is irradiated with a laser beam. In this case, the scanning range of the laser beam is about 100 m. Within the scanning range of the laser beam, the distortion of the beam position may or may not be corrected. By this inverse conversion correction, the appearance inspection can be performed even if the pattern is drawn while being distorted on the mask. Next, this mask inspection method will be described in detail.

The photomask is mounted on an XY stage of a mask inspection device. It should be noted that the pattern formation surface (principal surface) is turned upside down as shown in the figure, so that it is possible to prevent the attachment of foreign substances falling on the pattern surface during inspection. The XY stage is provided so as to be movable in a plane by a stage drive system. The operation of the stage drive system is controlled by a control signal from a stage control unit. The position coordinates of the photomask 1 are XY
It can be measured from the position coordinates of the stage. The position coordinates of this XY stage 4A are, for example, 0.01 μm by a laser interferometer.
It is possible to measure in m units. The measured values can be image data detected by the inverse transformation of the position coordinate map correction in FIG. 6 so that the circuit pattern whose position coordinates on the photomask are distorted does not distort the position coordinates.

In the inspection of the photomask, for example, inspection light emitted from an inspection light source arranged on the upper surface side of the photomask is applied to the photomask via a beam deflecting unit and a lens, and is further transmitted through the photomask. Light is detected by an image sensor via a lens. And
The position coordinate data of the photomask and the image data obtained by data conversion after being detected by the image sensor are temporarily stored in the storage unit. Although not shown, one set of image data detection optical system (lens, image sensor) is provided,
The beam from the light source may be split, and the image data may be compared based on the split beams.

The extraction of an abnormality in the photomask is performed by comparing image data at different locations in the photomask.
For example, the whole or a part of the image of the memory circuit area A11 in FIG. 2 is detected as described above and stored as image data in the storage unit, and the XY stage is moved in parallel to move all or one of the memory circuit area B11. (The memory circuit area A)
(Corresponding to a part of the image data coordinates of the image data 11) is detected as described above and stored in the storage unit as image data, and the image data of both areas are compared by the image data comparison logic circuit.

For the peripheral circuit area A00 of FIG. 2, the image data of the peripheral circuit area A00 obtained by the above detection is compared with the image data of the peripheral circuit area B00 of the adjacent chip transfer area B. Perform a visual inspection. Or
The appearance inspection is performed by comparing the design data of the integrated circuit pattern in the peripheral circuit area A00 with the image data in the peripheral circuit area A00.

Subsequently, classification is performed on the basis of the size and the light detection intensity of the difference portion of the pattern found by the comparison, and the data and the position coordinate data of the location where the difference occurs in the photomask are stored together with the data. Observe the appearance of the photomask in accordance with the position coordinate data for the location where the difference occurs, and classify the abnormal content of the abnormal location into, for example, a missing light-shielding portion, a remaining pattern defect, an attached foreign matter defect, and the like, to determine whether the defect is good or bad. Do.

In such an inspection, the above-described optical proximity effect correction processing is not performed on at least a part of the pattern on the photomask in a region other than the pair of rectangular regions. Does not include a fine correction pattern of about 1/3 or less of the size of the integrated circuit pattern. Therefore, the pattern inspection at that location is performed by using the image data obtained as described above of the pattern and the photomask. An appearance inspection of the pattern can be performed by a comparison inspection with the design data of the integrated circuit pattern used in forming the pattern.

Next, after such an inspection process, the mask is corrected based on the inspection result. At the time of correction, correction or removal of adhered foreign matter is performed so that the size, shape, and the like of both compared patterns are substantially equal at a portion where the pattern is different in the comparative inspection.

Next, a method of manufacturing the photomask 1 and the method of manufacturing the semiconductor device according to the first embodiment will be described with reference to the process chart of FIG. First, the optical proximity effect correction is performed on the design data of the semiconductor device (step 100). The design data of a semiconductor device is data corresponding to a design drawing having a graphic pattern such as an element and a wiring constituting the semiconductor device, and the pattern shape on this data is substantially similar to the pattern to be formed on the semiconductor substrate. Has become. Subsequently, the corrected pattern data (including the data of the correction pattern) is converted into electron beam drawing pattern data (step 101). Thereafter, based on the electron beam drawing pattern data, the mask substrate 2
Patterns (integrated circuit patterns and correction patterns) are drawn on (see FIG. 2). At this time, the pair of rectangular areas (for example, the memory circuit area A11 and the memory circuit area B11)
After storing the pattern data (integrated circuit pattern and correction pattern) in the buffer memory of the electron beam exposure apparatus (step 102), one of the pattern data of the pair of rectangular areas is read out of the data and shot-decomposed, An electron beam is exposed based on the data obtained thereby to draw a pattern in one rectangular area of the mask substrate 2 (step 103).

Thereafter, the pattern data of the other rectangular area is shot-decomposed again, and the pattern is drawn in the other rectangular area of the mask substrate 2 by exposing the electron beam based on the obtained data (step). 104).
When writing the electron beam, the photomask 1
A light-shielding film such as Cr is applied on the entire surface of the mask substrate 2, and a resist film for electron beam lithography is applied thereon. The format change of the deflection field division of the electron beam is performed on the pattern data (the integrated circuit pattern and the correction pattern data) of the one rectangular area described above, and is stored in a buffer memory of an electron beam exposure apparatus described later. In the process of changing the format, transferring, and storing the pattern data during this time, an abnormality can be detected in the process of each data processing by computer processing, and occurrence of an abnormality on a practical level can be eliminated.

On the other hand, in the process of reading pattern data from the buffer memory at a very high speed, decomposing shots, and drawing a circuit pattern by an electron beam, occurrence of pattern abnormalities cannot be ignored. This will be described later in detail with respect to the exposure method of the electron beam exposure apparatus used in the first embodiment. Since it fluctuates due to charge up of the electron beam in a high vacuum, beam fluctuation due to the life of the electron beam source, noise from an external power supply, etc., it is necessary to ensure that the electron beam is irradiated to a predetermined position in a predetermined shape. Is caused by what is not practically possible.

Therefore, in the first embodiment, when a pattern (integrated circuit pattern and correction pattern) is formed on the photomask 1, the above-described series of processes of data reading, shot decomposition, and pattern drawing are performed for each rectangular area. Try to do it repeatedly. That is, the pattern data of the rectangular area is read from the buffer memory at high speed,
The processing of drawing a pattern by decomposing shots is performed for each pair of rectangular regions described above. As a result, in the pattern drawing of the electron beam exposure apparatus, unless there is an abnormality in the pattern data itself, it is practically not possible for an abnormality to occur at the same position in each of the pair of rectangular regions. By comparing the actual pattern in the rectangular area, it is possible to detect the occurrence of an abnormality.

Next, after the above-described electron beam exposure processing, the mask substrate 2 is subjected to development processing to form an electron beam resist pattern, and using this as an etching mask, etching processing is performed to pattern the light shielding film. Thereby, a pattern (integrated circuit pattern and correction pattern) is formed on the mask substrate 2 and the photomask 1 is formed.
Is manufactured (step 105).

Subsequently, the appearance inspection of the photomask 1 is performed (step 106). At this time, in the first embodiment,
At least for the pair of rectangular regions described above, patterns of both regions (integrated circuit pattern and correction pattern)
Compare each other. That is, the appearance of the pattern is inspected by comparing the actually formed patterns on the photomask 1. Thereby, one of the integrated circuit patterns
Even when a fine correction pattern having a dimension of about ３ is added and the positional coordinate distortion correction is added to the integrated circuit pattern, it is possible to reliably and easily inspect the external appearance of the integrated circuit pattern.

Subsequently, classification is performed on the basis of the size and the light detection intensity of the difference portion of the pattern found by the comparison, and the data and the position coordinate data of the location where the difference occurs in the photomask 1 are stored together with the data. The appearance of the photomask 1 is observed in accordance with the position coordinate data of the location where the difference occurs, and the abnormal content of the abnormal location is classified into, for example, a lack of a light-shielding portion, a remaining pattern defect, an attached foreign matter defect, and the like, to determine the quality of the defect. I do.

In such an inspection, at least a part of the pattern on the photomask 1 other than the pair of rectangular areas is not subjected to the above-described optical proximity effect correction processing. Does not include a fine correction pattern of about 1/3 or less of the size of the integrated circuit pattern. Therefore, the inspection of the pattern at that location includes the image data obtained as
The pattern appearance can be inspected by comparison inspection with the design data of the integrated circuit pattern used when forming the pattern on the photomask 1. Next, after such an inspection process, correction is made based on the inspection result. At the time of correction, correction or removal of adhered foreign matter is performed so that the size, shape, and the like of both compared patterns are substantially equal at a portion where the pattern is different in the comparative inspection.

Subsequently, after the photomask 1 thus obtained is set in a reduction exposure apparatus, the pattern of the photomask 1 is transferred to a semiconductor wafer by the reduction projection exposure apparatus (step 107). At this time, it is possible to perform the exposure in a state where the distortion of the image of the pattern transferred to the semiconductor wafer is reduced at the position where the correction pattern is arranged.

After the exposure, a predetermined integrated circuit pattern is formed on the semiconductor wafer through a series of wafer processing such as development and etching (Step 108). Thereafter, in the first embodiment, the quality of the pattern on the photomask 1 can be determined by comparing the integrated circuit patterns actually transferred onto the semiconductor wafer (step 109).

That is, pass / fail can be determined by comparing the integrated circuit pattern formed by transferring the memory circuit area A11 of the photomask 1 on the semiconductor wafer with the design data of the semiconductor device pattern. The pass / fail can be determined by comparing the integrated circuit pattern formed by transferring the memory circuit area A11 of the mask 1 with the integrated circuit pattern formed by transferring the memory circuit area B11 of the photomask 1. This makes it possible to find random defects and attached foreign substances generated during the photoresist process for forming the integrated circuit pattern. That is, according to the first embodiment,
A highly reliable pattern inspection can be performed without comparing with design data of a semiconductor device pattern.

Next, an example of an electron beam exposure apparatus used for manufacturing the photomask 1 of Embodiment 1 will be described with reference to FIG. The electron beam exposure device 5 has a data storage unit, a drawing control unit, a control I / O unit, and an EB drawing unit.
The EB drawing unit has an electron beam optical system and a sample stage system. Photomask 1 as a sample in the EB drawing section
Are mounted on a stage 5A including an XY stage movable in a horizontal plane. As described above, the main surface of the photomask 1 is covered with a light-shielding film such as Cr, for example, and an electron beam resist or the like is applied thereon. The electron beam optics is stage 5
A plurality of electron lenses for controlling and irradiating the electron beam source 5B and the electron beam EB and control electrodes are provided above A, and the electron beam EB is emitted toward the photomask 1. . In the path of the electron beam EB from the electron beam source 5B to the stage 5A, for example, a first aperture 5C1 having a rectangular opening pattern described later is formed.
A blanking electrode 5D for controlling the emission of the electron beam EB, convergence of the electron beam EB, correction of the rotation of the electron beam EB around the optical axis, reduction of the cross-sectional shape of the electron beam EB, and focusing on the photomask 1. An electron lens 5E for performing alignment and the like, a first deflector 5F1, a second deflector 5F2, a second aperture 5C2 in which a plurality of desired opening patterns described later are formed, and an irradiation position of the electron beam EB on the photomask 1 are controlled. An electron optical system including a third deflector 5F3 and the like is provided.

The sample stage system is configured such that a stage 5A on which the photomask 1 is mounted can be freely moved in the XY directions in a horizontal plane in a vacuum chamber.
The position of the stage 5A is measured by the laser interferometer 5G and fed back to the electron beam system. At this time, a position vector correction value is added corresponding to the position on the stage. This correction value is a value measured by another measuring means, and within the photomask plane,
For example, in the case of a 6-inch substrate, 12 × 1
Two correction values are given. The correction difference between the correction values is usually 0.05 m or less. However, a linear approximation, a quadratic or a cubic curve approximation can be performed between the corrections, and the pattern can be drawn so that no step occurs in the pattern.

On the other hand, a control computer 5H for controlling the entire operation of the electron beam exposure apparatus 5 has a large storage capacity for storing drawing data of mask patterns (integrated circuit patterns and correction patterns) to be drawn on the photomask 1. The drawing data storage unit 5I is provided, drawing data necessary for an actual drawing operation is transferred to the buffer memory 5J, and the electron beam optical system is controlled by the calculation unit 5K. The arithmetic unit 5K includes a blanking electrode 5D for ON / OFF control of the electron beam EB based on the drawing data and the mark position signal from the buffer memory 5J, the height detection (referred to as Z detection) signal data, and the stage position data. A first deflection for selecting a part of a plurality of graphic apertures of the two aperture 5C2, a second deflection for irradiating a part of a rectangular aperture of the second aperture and changing a cross-sectional dimension of the transmitted electron beam EB, and a movement of the second aperture Aperture control, electron beam EB to perform
In this case, direct control data such as third deflection for defining an irradiation area and an irradiation position for the photomask 1 is created.

The on / off control of the electron beam EB is performed by extracting the beam irradiation parameter data from the arithmetic unit 5K, and performing a blanking signal generation unit 5L and a blanking control 5LC.
This is performed by controlling the blanking electrode 5D via.
To select a part of the plurality of figure openings of the second aperture, the figure selection parameter data is extracted from the arithmetic unit 5K, and the first deflector is supplied via the first deflection control signal generator 5M and the first deflection controller 5MC. This is performed by controlling 5F1. Similarly, in order to change the cross-sectional dimension of the electron beam EB, the beam dimension parameter data is taken out, the second deflector 5F2 is controlled via the second deflection control signal generator 5N and the second deflection controller 5NC, and the second aperture is controlled. Irradiation is performed so as to cut out a part of the rectangular opening of FIG. The movement of the second aperture 5C2 is performed by extracting the movement control parameter data of the second aperture 5C2 from the operation unit 5K, and through the movement control signal generation unit 5P and the movement control unit 5PC of the second aperture. One of the apertures enters the deflection area of the electron beam EB.

The third deflector 5F3 takes out the parameter data of the irradiation area and the irradiation position of the electron beam EB on the photomask 1 from the arithmetic unit 5K, and outputs the data to the third deflection signal generator 5Q and the third deflector controller 5QC. An operation of determining the irradiation position of the electron beam EB on the photomask 1 via the EB is performed. The third deflector 5F3 comprises an electromagnetic deflection for large-angle deflection and a two-stage electrostatic deflection for small-angle high-speed deflection.
That is, the irradiation position of the electron beam EB with respect to the photomask 1 overlaps the amount of deflection caused by the electromagnetic deflection for large-angle soil deflection of, for example, about 5 mm square and the electrostatic deflection for two-stage high-speed deflection of about 500 μm and about 80 μm. Is controlled by Thereby, large-angle, high-speed electron beam deflection can be realized.

The stage 5A is controlled by a control computer 5H via a stage controller 5R. The stage control unit 5R moves the stage 5A to a position instructed by the control computer 5H based on a measurement value from the laser interferometer 5G that precisely measures the amount of displacement of the stage 5A.
In the vicinity of the upper side of the stage 5A, an electron detector 5S is provided.
Are arranged, and secondary electrons and the like generated when the electron beam EB is irradiated on the alignment mark formed at a desired portion of the photomask 1 are detected in synchronization with the operation of the electron beam EB. Thus, the operation of detecting and specifying the position of the alignment mark is performed. An electron beam detection detector is mounted on the stage 5A, and detects the current value of the electron beam EB and the like. Based on the position data of the alignment mark, the drawing area of the photomask 1 is coordinate-transformed via the signal processing unit 5T and converted into a value in a predetermined reference coordinate system. Are used for controlling the third deflector 5F3. In addition, a Z detector meter is arranged near the electronic detector 5S. In other words, the surface of the photomask 1 is irradiated with a light beam at a predetermined inclination angle, and the height of the photomask 1 at the irradiated portion of the light beam reflected on the surface of the photomask 1 is precisely measured. .

For the sake of illustration, optical systems such as a light beam light source, a projection lens and a light receiving lens are omitted. Then, the height above the irradiation area of the electron beam EB on the photomask 1 detected via the Z detection sensor is converted into a predetermined reference coordinate system via the signal processing unit 5T and transmitted to the calculation unit 5K. . The focusing operation of the electron beam EB on the photomask 1 by the electron lens 5E is controlled by referring to the height information.

FIG. 10 shows the first aperture 5C1 and the second aperture 5C1.
FIG. 4 is an explanatory diagram showing an example of the configuration of an aperture 5C2. The first aperture 5C1 has a plurality of rectangular openings arranged in a lattice pattern, and is provided with an electron beam source or the first aperture 5C1.
When one rectangular opening of the first aperture 5C1 is deteriorated by providing a moving mechanism for the first aperture 5C1 in combination with the above aperture, it can be replaced with another rectangular opening without changing the high vacuum to atmospheric pressure. Can be. The deterioration of the rectangular opening is caused by contamination due to electron beam irradiation. Although it depends on the current position of the electron beam, it is effective when operating for a long period of several months or more.

The first aperture 5C1 and the second aperture 5
A plurality of opening patterns 5C1a having a size within the range in which the electron beam EB can be deflected by the first deflector 5F1 located between the opening patterns 5C1 and C2 are arranged in a lattice pattern. Batch transfer patterns 6a1-6a5 of a plurality of types of graphic openings and rectangular opening patterns 6a0
And These batch transfer patterns 6a1 to 6a5
Is composed of a plurality of figure openings and corresponds to a repetition pattern of a plurality of figure information such as a semiconductor device. In this case, the collective transfer pattern patterns 6a1-6
In a part of a5, a pair of isolated patterns which can be simultaneously selected by the electron beam EB passing through the first aperture 5C1 are formed at, for example, both corners in a diagonal direction. Then, at the time of collective transfer of each of the collective transfer patterns 6a1 to 6a5, the misalignment of the second aperture 5C2 is corrected by appropriately using these isolated patterns. That is, the second aperture 5C2 is formed by using two isolated patterns which can be simultaneously selected by the electron beam EB.
Correction is possible by measuring in advance the relationship between the exciting current and the magnification of the electron lens 5E constituting the electron optical system and the relationship between the rotation correction lens and the rotation angle.

However, in the case of an isolated pattern provided in a region that can be selected at a time by the electron beam EB,
Since the distance between them is small, it is necessary to increase the detection accuracy of the beam position. Therefore, in the present embodiment, the Faraday cup (not shown) having a knife edge provided on the moving stage 5A on which the photomask 1 is mounted is scanned a plurality of times in both the X-axis and the Y-axis to detect the beam position. The conditions are better. It is also conceivable that an isolated pattern having a larger distance between the two corners of the opening pattern 5C1a than the above isolated pattern is formed. In this case, the individual isolated patterns cannot be selected at once, so that beam deflection for individually selecting the two and adjustment of the beam swingback after the selection are required, and the correction work becomes slightly complicated.

The above-described second aperture 5C2 is combined with the above-mentioned first aperture 5C1 to form the second aperture 5C.
2 comprises at least one rectangular aperture and a plurality of graphic apertures in the first beam deflection area where the second aperture 5C2 is moved to form a plurality of batch transfer beams and a variable rectangular beam different from the above. It is made possible. When the second aperture 5C2 is moved by using the movement control means of the second aperture 5C2, the electron beam EB passing through the first aperture 5C1 is deflection-controlled so that the transmitted beam of the second aperture 5C2 is photomasked. Deflection control to one desired position, and using the reference marks on the stage 5A to form a reference for the first and third beam deflection control positions or a reference for the second and third beam deflection control positions. Is required. Thereafter, the photomask 1 is moved to a desired position to irradiate an electron beam.

Next, FIG. 11 is an explanatory view showing a main part of the electron beam exposure apparatus 5 taken out. A first aperture 5C1 having a moving mechanism such as a stage 5U1, and a second aperture 5C2 similarly having a moving mechanism such as a stage 5U2.
A first deflector 5F1 for selecting a part of the plurality of figures, a second deflector 5F2 for varying the size of the transmitted beam, and the like are provided. An example of such a batch transfer exposure method of the electron beam exposure apparatus 5 will be described. First, the target aperture pattern 5 in the second aperture 5C2 is moved by the stage 5U2.
C2a is positioned on the optical axis of the electronics system. Subsequently, the electron beam EB transmitted through the first aperture 5C1 is guided by a deflector to an isolated pattern formed on one of the collective transfer patterns 6a1 to 6a5 included in the opening pattern 5C1a, and passed through the isolated pattern. Irradiation is performed on the stage 5A side as two electron beams EB. And
By scanning a not-shown Faraday cup or the like provided on the stage 5A, a transfer error such as a rotational deviation around the optical axis of the isolated pattern and a magnification error is measured and stored.

Thereafter, the electron beam EB transmitted through the opening pattern 5C1a of the first aperture 5C1 is applied to the first deflector 5F.
1 guides the opening pattern 5C1a to the target batch transfer patterns 6a1 to 6a5 to shape the cross-sectional shape of the electron beam EB, and corrects the operation of the formed electron beam EB by the correction device obtained by the above-described measurement. By controlling the electronic lens 5E, the third deflector 5F3, and the like, the batch transfer pattern 6 is formed at a desired position on the photomask 1 mounted on the moving stage 5A in a desired size.
Irradiation is applied to the shapes of a1 to 6a5 to expose the electron beam resist on the surface of the photomask 1.

Next, the flow of drawing data of the electron beam exposure apparatus 5 will be described. The mask drawing pattern data is stored in a storage device 5I such as a magnetic disk in a data storage unit. The drawing data of the target pattern is transferred to the buffer memory 5J via the control computer 5H according to an instruction from the control computer 5H, and the drawing position of the pattern on the photomask 1 is positioned below the optical axis of the electron optical system. . Then, by scanning an alignment mark or the like on the photomask 1 with the electron beam EB or the like, coordinate information and height information of a target drawing portion in the plane of the photomask 1 are transferred to the buffer memory 5 via the signal processing unit 5T.
Transferred to J. Thereafter, based on the coordinates and the correction information described above, the target irradiation unit is positioned with respect to the electron optical system, and the focal position of the electronic lens 5E with respect to the photomask 1 is changed based on the height information of the area. Is set. Thereafter, the arithmetic unit 5K calculates a control signal related to the shape and the deflection amount of the electron beam EB based on the mask drawing pattern data stored in the buffer memory 5J, and writes the drawing data and the mark position signal from the buffer memory 5J. A blanking electrode 5D for controlling on / off of the electron beam EB, a first deflector 5F1 for selecting a part of a plurality of graphic openings of the second aperture 5C2, and a second aperture 5C2 based on height detection signal data and stage position data. A second deflector 5F2, which irradiates a part of the rectangular opening of FIG.
Direct control signal data such as a second aperture control for moving the aperture 5C2 and a third deflection for determining an irradiation area and an irradiation position of the electron beam EB with respect to the photomask 1 are generated.

When exposing a pattern including a repetition of a plurality of figures such as a semiconductor device, a first aperture 5C1 having a rectangular opening and a second aperture 5C2 having at least one rectangular opening and a plurality of figures are connected to a beam source. 5
B, a beam is sequentially interposed in the path of the focused beam from the photomask 1 to the photomask 1. The deflection control of the focused beam is performed by deflecting the beam passing through the first aperture 5C1 to form a rectangular aperture of the second aperture 5C2 and a plurality of graphics. A first deflector 5F1 for selecting a part of the aperture, a second means for deflecting the size of the beam passing through the rectangular aperture, and a deflection control for deflecting the transmitted beam of the second aperture 5C2 to a desired position on the photomask 1. And a third deflection deflector 5F3 for performing the above-mentioned repetition pattern of the figure, by using the first deflection control, selecting a part of the plurality of figure openings of the second aperture, and then performing the third deflection. Using the control, a process of irradiating a desired position of the photomask 1 with an electron beam is repeated to form a combined pattern. In the above exposure, a combined pattern is formed on the photomask 1 within the range of the corresponding third beam deflection control while moving the moving stage 5A.

In the above exposure, the second aperture has a plurality of beam deflecting regions, and the corner region has a plurality of figure openings and rectangular openings, and the deflection control of the focused beam passes through the first aperture. First deflecting means for deflecting a beam to select a rectangular opening of the second aperture and a part of the plurality of figure openings, and deflecting a transmitted beam of the second aperture to a desired position on the photomask 1 After the movement of the second aperture, using the reference mark on the photomask 1 or the photomask base,
At least one of the first beam deflection control and the second beam deflection control and the reference position of the third beam deflection control are calibrated, the photomask 1 is moved to a desired position, and then the beam is irradiated to form a combined pattern. .

Thus, an integrated circuit pattern is drawn on one rectangular area of the photomask 1. afterwards,
Buffer memory 5 for the other rectangular area
Based on the mask drawing pattern data stored in J, the above processing is repeated to draw an integrated circuit pattern. For this reason, it is possible to easily compare and match the corrected mask exposure pattern with the mask inspection data. In the above description, the graphic aperture of the second aperture is used. However, the drawing may be performed using only the rectangular aperture without using the graphic aperture. In order to realize the above pattern exposure method, the mask exposure pattern data corresponding to the pattern exposure method is stored in the buffer memory 5J of the electron beam exposure apparatus 5.
Must be reliably transferred to The electron beam exposure apparatus 5 has a data sum check function and the like for processing until data is stored in the buffer memory 5J, and has a structure capable of detecting an abnormality such as a data transfer error and data conversion. .

The drawing data for realizing the above-mentioned pattern exposure is stored in a buffer memory because the electron beam is controlled at a high speed by the above-described first and second beam deflection control and beam blanking control to perform on-off irradiation. After the data is read from 5J, the electron beam having a sectional shape of one of a graphic shape, a rectangular shape, and a spot shape is combined to be decomposed into exposure data that can be filled and exposed, and converted into various control data. It is very difficult to perform an error check in all of them, but it is possible to detect an abnormal drawing pattern by a method of comparing and collating patterns drawn by repeating reading from the buffer memory 5J, and making it possible to detect the drawing pattern. The reliability can be greatly improved.

Next, the method of manufacturing the semiconductor device according to the first embodiment will be described by using, for example, a twin-well CMOS (Compliment
aryMOS) is shown in FIGS.
9 will be described.

FIG. 19 is a cross-sectional view of a main part of a semiconductor substrate 7s constituting the semiconductor wafer 7 during the manufacturing process.
The semiconductor substrate 7s is made of, for example, n-type Si single crystal, and has, for example, an n-well 8n and a p-well 8p formed thereon. For example, phosphorus or As, which is an n-type impurity, is introduced into the n-well 8n. Further, for example, boron as a p-type impurity is introduced into the p well 8p.

Then, as shown in FIG. 13, a field insulating film 9 made of, for example, SiO2 is formed on the main surface of the semiconductor substrate 7s by LOCOS (Local Oxidization).
After being formed by the silicon (Si) method or the like, the device forming region surrounded by the field insulating film 9
Is formed by a thermal oxidation method or the like. Thereafter, a gate forming film made of, for example, low-resistance polysilicon is deposited on the semiconductor substrate 7s by a CVD method or the like, and then the film is patterned by a photolithography technique and an etching technique.
A gate electrode 10g is formed. Next, for example, an n-type impurity such as phosphorus or As is introduced into the n-channel MOS / FET formation region by an ion implantation method or the like. On this occasion,
Using the gate electrode 10g as a mask, an n-type impurity is introduced into the semiconductor substrate 7s in a self-aligned manner.

Subsequently, for example, a p-type impurity such as boron is introduced into the p-channel MOS / FET formation region by an ion implantation method or the like. At this time, a p-type impurity is introduced into the semiconductor substrate 7s in a self-aligned manner using the gate electrode 10g as a mask. Thereafter, a heat treatment is performed on the semiconductor substrate 7s to thereby form an n-type semiconductor region 10n constituting a source region and a drain region of the n-channel type MOS.FET.
d and p-channel type MOS-FET
Is formed to form a p-type semiconductor region 10pd constituting the source region and the drain region of FIG. Next, as shown in FIG. 14, after an interlayer insulating film 11a made of, for example, SiO2 is deposited on the semiconductor substrate 7s by the CVD method or the like, a polysilicon film is deposited on the upper surface thereof by the CVD method or the like.

Subsequently, the polysilicon film is patterned by a photolithography technique and an etching technique, and impurities are introduced into predetermined regions of the patterned polysilicon film to thereby form a wiring 12L and a resistor 12R made of the polysilicon film. To form

Thereafter, as shown in FIG. 15, an interlayer insulating film 11b made of, for example, SiO2 is formed on the semiconductor substrate 7s.
Is deposited by SOG (Spin On Glass) method etc.
The semiconductor regions 10pd and 10nd are formed on the interlayer insulating film 11b.
And a connection hole 13a such that a part of the wiring 12L is exposed.
Is formed by photolithography and etching. At this time, although not shown, the above-described alignment mark pattern is formed in a scribe area in a peripheral portion of the circuit pattern chip or in the vicinity thereof. That is, a groove having the above-described mark pattern is formed on the insulating film.

Next, after a metal film made of, for example, tungsten is deposited on the semiconductor substrate 7s by a sputtering method or the like, the metal film is removed by chemical polishing etching until the metal film other than the connection holes is removed. Perform planarization etching. Thereby, as shown in FIG.
The metal film 14a is embedded in the connection hole 13a.

Subsequently, as shown in FIG.
Alternatively, after depositing a metal film made of an Al alloy or the like by a sputtering method or the like, the metal film is patterned by a photolithography technique and an etching technique to form the second layer wiring 14L.

Thereafter, as shown in FIG. 18, an interlayer insulating film 11c made of, for example, SiO2 is formed on the semiconductor substrate 7s.
Is deposited by a CVD method or the like, and a connection hole 13b is formed in a part thereof so that a part of the second layer wiring 14L is exposed.

Next, after depositing a metal film made of, for example, Al or an Al alloy by a sputtering method or the like,
The third layer wiring 15L is formed by patterning the metal film by a photolithography technique and an etching technique. Thereafter, a surface protection film 16 made of, for example, SiO2 is deposited on the semiconductor substrate 7s by a CVD method or the like to cover the third layer wiring 15L.

FIG. 20 shows a photolithography process in the manufacturing process of such an SRAM, that is, an exposure process flow diagram in which the exposure process is extracted and made into a flow.

In the figure, an n-well photo process P1
Is a step of depositing an insulating film made of silicon nitride or the like on a semiconductor substrate and then forming a photoresist pattern on the insulating film so as to cover a region other than the n-well formation region.

The field photo step P2 is a step of depositing an insulating film made of silicon nitride or the like on a semiconductor substrate and then forming a photoresist pattern on the insulating film so as to cover only the element forming region. .

The p-well photo step P3 is a step of forming a photoresist pattern covering the n-well in order to form a p-well channel stopper region.

The gate photo step P4 is a step of depositing a conductor film made of polysilicon or the like on a semiconductor substrate and then forming a photoresist pattern on the conductor film so as to cover a gate electrode formation region. .

The n-channel photo step P5 is a step of forming a photoresist pattern covering the p-channel side in order to implant n-type impurities into the n-channel side by using the gate electrode as a mask. Conversely, the p-channel photo step P6 is a step of forming a photoresist pattern covering the n-channel side in order to implant p-type impurities into the P-channel side using the gate electrode as a mask.

In the polycrystalline silicon photo step P7, the wiring and the resistance region are covered on the polycrystalline silicon film deposited on the semiconductor substrate in order to pattern the second polycrystalline silicon film serving as the wiring or the resistance. This is a step of forming such a photoresist pattern. The R photo step P8 is a step of patterning a photoresist pattern serving as a mask when introducing impurities into other regions by a negative process in a state where a photoresist pattern is formed on the resistor.

The contact photo step P9 is a step of forming a photoresist pattern for forming a connection hole by a positive process. Al-1 photo process P10
Is a step of patterning the first layer wiring. The through hole photo step P11 is a step of forming a photoresist pattern for opening a connection hole connecting the first layer wiring and the second layer wiring.

The Al-2 photo step P12 is a step for patterning the second layer wiring. The bonding pad photo step P13 is a step of forming an opening of about 100 μm corresponding to the bonding pad in the surface protection film, and a step of forming a photoresist pattern covering the area other than the bonding pad formation region on the surface protection film. It is.

Of these exposure processes, n-well
The photo process P1, the n-channel photo process P5, the p-channel photo process P6, and the bonding pad photo process P13 have relatively large minimum dimensions, so that it is not generally necessary to use a phase shift mask. Then, a photomask having a phase shift pattern described later in Embodiment Mode 2 may be used for exposure.

In particular, in the gate photo step P4, a gate electrode is formed using a chemically amplified negative photoresist, and in the contact photo step P9, a connection hole is formed using a chemically amplified positive photoresist. Form. This makes it possible to make the gate length of the gate electrode and the opening diameter of the connection hole smaller than the wavelength of the exposure light used in the light exposure method (for example, about 0.3 μm by i-line exposure).

As described above, according to the first embodiment, when the photomask 1 has the correction pattern for the optical proximity correction effect finer than the integrated circuit pattern, and the position coordinates of the integrated circuit pattern are distorted. However, the correction pattern can be formed, and the quality can be reliably and easily inspected. Therefore, high quality photomask 1 without defects
Can be manufactured. In addition, by performing exposure processing using the photomask 1, optical proximity effect correction and position coordinate correction can be performed favorably in the exposure processing, and image resolution, depth of focus, and overlay accuracy can be increased. Therefore, an integrated circuit pattern having a desired shape and dimensions can be satisfactorily transferred onto a semiconductor substrate. Therefore, the yield, reliability, and performance of the semiconductor device can be improved.

That is, when a pattern formed on a photomask is exposed on a semiconductor wafer by using a reduction projection exposure apparatus, the pattern on the semiconductor wafer generated due to the optical system of the reduction projection exposure apparatus or the illumination form is generated. The position shift amount of the pattern of the projection pattern is obtained in advance, and when drawing the pattern of the photomask in accordance with the shift amount, the stage coordinate of the pattern drawing device is shifted and drawn, thereby causing the pattern on the semiconductor wafer. Pattern displacement can be reduced.

FIG. 21 shows that the reference mark pattern is 0 degree, 9 degree,
Measure the position coordinates by rotating 0, 180, and 270 degrees,
FIG. 9 is a diagram illustrating a measurement example of alignment of a mask drawing position by reducing a difference between measurement patterns. According to the method shown in FIG. 21, the positional coordinate accuracy of the stage on which the mask of the mask drawing apparatus itself is mounted is adjusted to the ideal coordinate system, and a reference mark pattern is formed on the photomask substrate shown in FIG. Similarly, the position coordinate accuracy of the stage on which the mask of the mask inspection apparatus is mounted can be adjusted to the ideal coordinate system. Note that the holding of the mask substrate causes the substrate to bend. Therefore, care must be taken when calibrating the position coordinates by rotating the mask substrate.

(Embodiment 2) FIG. 22 is a plan view of a photomask for explaining another optical proximity effect correction method as another embodiment of the present invention. A pattern for transferring a wiring pattern on a photomask is shown. FIG. 3A corresponds to the design data of the integrated circuit pattern, and the wiring pattern (integrated circuit pattern) L before the correction is applied.
1, L2, which is a pattern to be transferred onto a semiconductor wafer. FIG. 3B shows the corrected pattern (wiring patterns L1, L2 and corrected patterns H2, H3).
It is.

The wiring pattern L1 has a large area pattern portion L
1a and a narrow lead pattern portion L1b. The dimensional ratio between the large area pattern portion L1a and the lead pattern portion L1b is twice or more, and the width of the lead pattern portion L1b is less than the exposure wavelength, for example, about 1.5 μm. The correction pattern H2 is arranged in the large-area pattern portion L1a near the junction with the lead pattern portion L1b. This is because when the wiring pattern L1 is transferred onto a semiconductor wafer without providing a correction pattern, the transfer pattern in the portion corresponding to the vicinity of the portion joined to the large-area pattern portion L1a in the extraction pattern portion L1b is narrowed. This is to prevent it. This correction pattern H2
Is formed, for example, in a plane quadrangular shape, and its size is about 1/3 or less of the size of the wiring pattern.

The wiring pattern L2 includes a wide pattern portion L2a and a narrow drawing pattern portion L2b. The width of the wide pattern part L2a is, for example, about 5 μm, and the width of the lead pattern part L2b is about the exposure wavelength or less, for example, about 1.5 μm. Correction pattern H3
Are arranged in the wide pattern portion L2a in the vicinity of the junction with the lead pattern portion L2b. This is because when the wiring pattern L2 is to be transferred onto the semiconductor wafer without providing a correction pattern, the transfer pattern in the portion corresponding to the vicinity of the portion joined to the wide pattern portion L2a in the lead pattern portion L2b is prevented from being narrowed. That's why. The correction pattern H3 is formed, for example, in a plane quadrangular shape, and its dimension is about 1 / the dimension of the wiring pattern.
It is about 3 or less.

The correction of the transfer pattern distortion is performed by creating correction pattern data around the deleted portion and drawing using an electron beam or the like according to the pattern data. FIG. 23 shows a modification of the correction of FIG. That is, in the wiring pattern L1, the lead pattern portion L1
b, a correction pattern H4 for partially increasing the width of the lead pattern portion L1b is arranged near the junction with the large area pattern portion L1a, and the end portion is also provided at the tip of the lead pattern portion L1b. A correction pattern H5 extending and widening is arranged. Further, in the wiring pattern L2, a correction pattern H6 that partially widens the width of the lead pattern portion L2b is disposed near the junction with the wide pattern portion L2a in the lead pattern portion L2b. The correction patterns H4 to H6 are formed in, for example, a plane quadrangular shape, and the size is about 1/3 or less of the size of the wiring pattern. The correction of the transfer pattern distortion is performed by creating circuit pattern data and correction pattern data and combining them at the time of mask drawing.

FIG. 24 shows a pattern for transferring a fine rectangular pattern on a photomask, for example. FIG. 3A corresponds to design data of an integrated circuit pattern, which is a rectangular pattern (integrated circuit pattern) L3 before correction, which is a pattern to be transferred onto a semiconductor wafer. FIG. 7B shows the corrected pattern (rectangular pattern L3a). The corrected rectangular pattern L3a is, for example, a fine rectangular pattern having an aspect ratio of about 1: 4, and the dimension of the short side is equal to or less than the exposure wavelength. In order to correct the thickening of the central portion, the portion has been deleted, and the width of the light transmission region is narrower than the other portions. This is to prevent the increase of the light intensity at the center of the transfer pattern and the increase of the pattern width when the rectangular pattern L3 is transferred onto the semiconductor wafer. The correction amount is about one third or less of the dimension of the short side of the rectangular pattern L3.

The transfer pattern distortion is corrected by creating corresponding pattern data and drawing a mask according to the data. FIG. 25 shows an example in which a block pattern composed of lines and spaces shorter than the exposure wavelength is subjected to distortion correction to an end pattern. For each block pattern, the cell pattern excluding the end portion and the entirety including the cell pattern are defined as a cell pattern of a higher hierarchy, so that the data amount can be reduced and the end portion pattern can be corrected for distortion.

The above-mentioned correction is effective for correcting the edge when the phase shifter is added to the above-described pattern, and is effective for correcting the edge when the top distortion occurs.

The correction data is obtained by enlarging the size of the pattern in the corresponding area until the line portion overlaps, obtaining a logical sum, further reducing the logical sum pattern, and obtaining a logical product with the original area pattern. Only the part pattern can be extracted. A predetermined pattern correction process can be performed on this pattern. As circuit pattern data,
By using the cell pattern for the portion excluding the end portion and the hierarchical structure shown in FIG. 33 including the end portion, an increase in the data amount of the entire circuit pattern can be suppressed.

The distortion of the top aberration at the time of projection exposure is a dimensional shift of the end of the line-and-space pattern separated from the optical axis center of the exposure optical system, but can be corrected by the above method. The displacement of the transfer position can be corrected without increasing the mask drawing data by correcting the stage coordinate system of the pattern drawing apparatus.

(Embodiment 3) FIG. 26 is a flowchart for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention. FIGS. FIG. 31 is a flow chart for explaining a method of manufacturing a photomask used in the method of manufacturing the semiconductor device in FIG. 1.

In the third embodiment, a phase shift pattern is formed in the pair of rectangular areas instead of the optical proximity correction pattern. However, both the phase shift pattern and the optical proximity effect correction pattern may be formed in a pair of rectangular regions. Other than that, it is the same as the first embodiment.

The overall structure of the photomask is the same as that shown in FIG. 2 used in the description of the first embodiment. A phase shift pattern is formed in the memory circuit areas A11 and B11, which are a pair of rectangular areas in FIG. The phase shift technique is a technique for preventing a decrease in contrast of a projected image by manipulating the phase of light transmitted through a photomask. A specific example of this phase shift pattern will be described with reference to FIGS. In each of the drawings, (a) is a cross-sectional view taken along line AA of (b). FIG. 27 shows a mask pattern used for forming a gate pattern of, for example, a MOSFET. On the main surface of the mask substrate 2, for example, C
A light-shielding film S (hatched) made of r or the like is applied. In a part of the light shielding film S, two rectangular opening patterns 17a and 17b through which light can be transmitted are formed.
At the center of one of the opening patterns 17a, a rectangular phase shift pattern (hereinafter, referred to as a phase shifter) 18a is arranged so as to bisect the opening pattern 17a. In the other opening pattern 17b, a rectangular phase shift pattern 18b is arranged so as to cover half of the opening pattern 17b. The phase shift patterns 18a and 18b are means for operating the exposure light so that the phases of the respective lights transmitted through the areas where the phase shift patterns 18a and 18b are present and the areas where the phase shift patterns 18b and 18b are not present are opposite to each other in the opening patterns 17a and 17b. .

In this case, the phase shift pattern 18a, 1
8b is made of, for example, a transparent silicon oxide film formed by the SOG (Spin On Glass) method. In such a mask pattern, in the opening patterns 17a and 17b, the fine pattern projected on the semiconductor wafer surface position corresponding to the boundary (the edge of the phase shift pattern) between the area where the phase shift patterns 18a and 18b exist and the area where it does not exist. Such a shadow is transferred as an integrated circuit pattern (gate electrode). Therefore, in the opening pattern 17a, two gate electrode patterns can be transferred, and in the opening pattern 17b, one gate electrode pattern can be transferred. In such projection exposure, overlapping exposure is performed using a light-shielding mask having a pattern 19 of a strip-shaped light-shielding film S shown in FIG. 24 to form a predetermined integrated circuit pattern (gate electrode) on a semiconductor wafer. FIG. 28 shows a case where the phase shift patterns 18a and 18b of FIG. 27 are formed by grooves dug in the thickness direction of the mask substrate 2. The right side of FIG. 29 shows a case where a thin light-shielding pattern S1 is arranged so as to divide the opening pattern 17a into three equal parts. Thin shading pattern S1
Is, for example, about 0.5 μm. The exposure method of the photomask 1 in this case is the same as that in FIG. FIG.
0 shows a mask pattern for transferring the line pattern. On the main surface of the mask substrate 2, for example, C
A light-shielding film S (hatched) made of r or the like is attached, and rectangular opening patterns 17c to 17h through which light can pass are arranged in a part thereof in parallel with each other.

The opening patterns 17c, 17d, 17
In the vicinity of g and 17h, auxiliary opening patterns 19a to 19g having a narrower width than the opening patterns 17c and 17 are provided.
d, 17g, 17h, and the opening pattern 17
c, 17d, 17g, and 17h are arranged parallel to the long sides. These auxiliary opening patterns 19a to 19g are patterns added by the phase shift pattern adding process, and do not form a bright image by themselves.
/ 3 or less. Although not particularly limited, the width of the opening patterns 17c to 17h is, for example, about 1.5 μm, and the width of the auxiliary opening patterns 19a to 19g is, for example, about 0.3 μm.

Further, phase shift patterns 18c to 18i are arranged in the opening patterns 17d and 17f and the auxiliary opening patterns 19a and 19d to 19g. The phase shift patterns 18c to 18i are formed, for example, by grooves dug in the thickness direction of the mask substrate 2. In this case, the groove is formed so that its end slightly enters below the end of the light shielding film S. This is because, for example, irregular reflection on the edge surface of the groove can be suppressed and a good projected image can be transferred. Of course, the phase shift patterns 18c-1
8i may be formed of a transparent film.

The phase shift patterns 18c and 18d are arranged such that the phases of the respective lights transmitted through the adjacent opening patterns 17c to 17h are opposite to each other.
The phase of the light transmitted through the auxiliary opening pattern 19a is
The phase of the aperture pattern 17c and the phase of the transmitted light are reversed by the phase shift pattern 18e disposed thereon, whereby the edge of the projected image of the aperture pattern 17c is emphasized. . The phase of the light transmitted through the correction aperture patterns 19b and 19c is changed by the phase shift pattern 18c disposed in the aperture pattern 17d.
Thus, the phase of the light transmitted through the aperture pattern 17d is opposite to that of the aperture pattern 17d.
The edge of the projected image of d is emphasized.

The phase of the light transmitted through the correction aperture patterns 19d and 19e is opposite to the phase of the light transmitted through the aperture pattern 17g by the phase shift patterns 18f and 18g disposed there. As a result, the edge of the projected image of the opening pattern 17g is emphasized. Further, the correction aperture pattern 19f, 1
The phase of the light transmitted through 9g is changed by the phase shift patterns 18h and 18i arranged there, and
, The phase of the light transmitted through the aperture pattern 17h is reversed, whereby the edge of the projected image of the aperture pattern 17h is emphasized.

Next, a method for manufacturing the photomask 1 and the method for manufacturing a semiconductor device according to the third embodiment will be described with reference to the process chart of FIG. First, the data of the above-described phase shift pattern is added to the design data of the semiconductor device. In addition, data of an auxiliary opening pattern having a fine size that does not form a bright image by itself in the light transmitting region is added. This processing is performed on at least a part of the integrated circuit pattern on the photomask 1 at least in units of the above-described pair of rectangular areas, and in the main surface of the photomask 1, the area units repeatedly arranged in the vertical and horizontal directions. (Step 100).

Subsequently, the integrated circuit pattern data (including the data of the phase shift pattern and the auxiliary opening pattern) is converted into electron beam drawing pattern data (step 101). Thereafter, based on the electron beam drawing pattern data, an integrated circuit pattern and an auxiliary opening pattern are drawn on the mask substrate 2 (see FIG. 2), and then a phase shift pattern is drawn. At this time, the pair of rectangular regions (for example, the memory circuit region A11 and the memory circuit region B1)
After the mask pattern (integrated circuit pattern, auxiliary opening pattern and phase shift pattern) data of 1) is stored in the buffer memory of the electron beam exposure apparatus (step 10).
2) Exposure data that reads out pattern data of one of the pair of rectangular areas from the data and that can be filled and exposed by combining an electron beam having a sectional shape of one of a figure shape, a rectangular shape, and a spot shape. The pattern is drawn in one rectangular area of the mask substrate 2 by exposing with an electron beam based on the data obtained thereby (step 103).

Thereafter, the pattern data of the other rectangular region is shot-decomposed again, and the pattern is drawn in the other rectangular region of the mask substrate 2 by exposing the electron beam based on the obtained data (step). 104).
At the time of forming the pattern of the light-shielding film in the electron beam writing, a light-shielding film such as Cr is applied on the entire surface of the mask substrate 2 of the photomask 1, and electron beam writing is performed thereon. Electron beam resist film is applied. In forming the phase shift pattern, an electron beam resist film is applied on the mask substrate 2 of the photomask 1. In addition, since the phase shift pattern has a larger pattern size than the pattern of the light shielding film, laser beam exposure may be used instead of electron beam exposure.

Also in this case, the pattern data of a pair of rectangular areas is stored in the buffer memory of the laser beam exposure apparatus, the data is read out, shot-decomposed, and the laser beam exposure processing is performed corresponding to one of the rectangular areas. After that, the pattern data is shot-decomposed again for the other rectangular area, and a laser beam exposure is performed corresponding to the other rectangular area to form a pattern on the photomask.

The mask pattern data (data of the integrated circuit pattern, the auxiliary aperture pattern and the complementary phase shift pattern) of the one rectangular area is subjected to the format change of the deflection field division of the electron beam, and the buffer of the electron beam exposure apparatus is changed. Store in memory. As for the format change, transfer, and storage processing of the pattern data during this time, an abnormality can be detected in the process of each data processing by computer processing, and occurrence of an abnormality at a practical level can be eliminated.

On the other hand, pattern data is read out from the buffer memory at a very high speed, and the electron beam having a cross-sectional shape of one of a figure shape, a rectangular shape, and a spot shape is combined to be shot-decomposed into exposure data that can be painted and exposed. In the process of drawing a pattern with an electron beam, occurrence of abnormal pattern cannot be ignored. This is because in the electron beam exposure apparatus, in the step of pattern drawing, processing such as shot decomposition, beam deflection, beam on-off blanking, etc., charge-up of the electron beam in a high vacuum,
This is due to the fact that it is extremely difficult to guarantee that the electron beam is irradiated in a predetermined shape and at a predetermined position because it fluctuates due to the life of the electron beam source, noise from an external power supply, and the like.

Therefore, when forming a mask pattern (integrated circuit pattern, auxiliary opening pattern, and phase shift pattern) on the photomask 1, the above-described data reading, and the sectional shape is one of a graphic shape, a rectangular shape, and a spot shape. A series of processes of combining shots into exposure data that can be painted and exposed by combining the electron beams and performing pattern drawing are repeatedly performed for each rectangular area. That is, the process of reading the mask pattern data of the rectangular area from the buffer memory at high speed, decomposing the shot, and drawing the pattern is performed for each of the pair of rectangular areas. As a result, in the pattern drawing of the electron beam exposure apparatus, unless there is an abnormality in the pattern data itself, an abnormality does not occur at the same position in each of the pair of rectangular regions at a practical level. It is possible to detect the occurrence of an abnormality in the step of comparing the actual patterns.

Next, after the electron beam exposure process for forming the integrated circuit pattern and the auxiliary opening pattern as described above, the mask substrate 2 is subjected to a development process to form an electron beam resist pattern, and this is used as an etching mask. The integrated circuit pattern and the auxiliary opening pattern are formed on the mask substrate 2 by performing an etching process to pattern the light shielding film. Thereafter, after an electron beam exposure process for forming a phase shift pattern, a development process is performed on the mask substrate 2 to form an electron beam resist pattern, and an etching process is performed using the resist pattern as an etching mask, thereby forming a groove or a transparent film. A photomask 1 is manufactured by forming a phase shift pattern (step 105).

Subsequently, the appearance inspection of the photomask 1 is performed (step 106). At this time, in the second embodiment,
At least for the pair of rectangular regions, the patterns of both regions are compared. That is, the patterns actually formed on the photomask 1 are compared and inspected. As a result, it is possible to reliably and easily inspect the quality of a fine pattern having a dimension of about 1/3 of the integrated circuit pattern. Also, regarding the phase difference error of the phase shift pattern, which is a problem, the pass / fail judgment can be made by comparing the actual pattern on the photomask 1. The specific pattern inspection method of the photomask 1 is the same as that described in Embodiment 1 with reference to FIG. Also, the inspection of the peripheral circuit area A00 in FIG. 2 is the same as that in the first embodiment, and the description is omitted.

Subsequently, classification is performed on the basis of the size and the light detection intensity of the difference portion of the pattern found by the comparison, and the position coordinate data of the location where the difference occurs in the photomask 1 is stored together with the data. The appearance of the photomask 1 is observed in accordance with the position coordinate data of the location where the difference occurs, and the abnormal content of the abnormal location is classified into, for example, a lack of a light-shielding portion, a remaining pattern defect, an attached foreign matter defect, and the like, to determine the quality of the defect. I do.

In such an inspection, the above-mentioned phase shift pattern and auxiliary opening pattern are not provided in at least a part of the pattern on the photomask 1 in a region other than the pair of rectangular regions. Inspection of the pattern at that location is performed by comparing the image data obtained as described above of the pattern with the mask pattern data used when forming the pattern on the photomask 1 to inspect the appearance of the pattern. It is possible to do.

Next, after such an inspection step, correction is made based on the inspection result. At the time of correction, correction or removal of adhered foreign matter is performed so that the size, shape, and the like of both compared patterns are substantially equal at a portion where the pattern is different in the comparative inspection.

Subsequently, after the photomask 1 thus obtained is set in a reduction exposure apparatus, the pattern of the photomask 1 is transferred to a semiconductor wafer by reduction projection exposure (step 107). At this time, at the position where the phase shift pattern and the auxiliary opening pattern are arranged, it is possible to transfer the pattern on the photomask onto the semiconductor wafer with high accuracy by using the interference of the exposure light.

Thereafter, a predetermined integrated circuit pattern is formed on the semiconductor wafer through a series of wafer processing such as development and etching (Step 108). Thereafter, also in the second embodiment, the quality of the pattern on the photomask 1 can be determined by comparing the integrated circuit pattern actually transferred on the semiconductor wafer (step 1).
09). That is, the pass / fail can be determined by comparing the integrated circuit pattern formed by transferring the memory circuit area A11 of the photomask 1 on the semiconductor wafer with the design data of the semiconductor device. An integrated circuit pattern formed by transferring the circuit area A11 and a memory circuit area B11 of the photomask 1;
Can be determined by comparing with the integrated circuit pattern formed by the transfer.

As a result, it is possible to find random defects and adhered foreign substances generated during the photoresist process for forming the integrated circuit pattern. That is,
Abnormalities such as chipping of a light-shielding film, residue, chipping of a phase shift pattern, residue, adhered foreign matter, and phase difference error of the phase shift pattern generated in the photomask 1 during the process of forming an integrated circuit pattern on a semiconductor wafer. Can be detected by comparing the patterns of a pair of rectangular regions formed on the semiconductor wafer. Also in the third embodiment, a highly reliable inspection of a pattern formed on a photomask can be performed without comparison with mask pattern data of a semiconductor device. As described above, according to the second embodiment, even in the case of the photomask 1 having the phase shift pattern and the auxiliary opening pattern, in the inspection process, the extraction of abnormalities and the quality determination, particularly the inspection for the presence or absence of a phase difference error, can be reliably performed. In addition, it can be performed easily.

Next, the mask process (step 105) of FIG. 26 will be described in detail with reference to the flowchart of FIG.
The mask substrate of the photomask is made of, for example, transparent synthetic quartz glass having a refractive index of 1.47. First, a light-shielding film made of, for example, Cr is formed on the main surface of the mask substrate by a sputtering method or the like (Step 201), and then an electron beam resist is spin-coated on the main surface (Step 20).
2).

Then, a predetermined integrated circuit pattern is drawn by irradiating the electron beam resist film on the main surface of the photomask 1 with an electron beam using the above-described electron beam exposure apparatus (step). 203). In this electron beam writing apparatus, an electron beam is formed into a predetermined shape based on pattern data that describes information such as dimensions and position coordinates of individual figures of an integrated circuit pattern (including an auxiliary opening pattern). Irradiate a desired position on the resist film. The pattern data used here corresponds to one of the light transmitting area and the light shielding area on the photomask 1. Usually, a positive resist and a negative resist are selected so that the irradiation area of the electron beam is reduced. I do.
For example, for a pattern such as a contact hole, the exposure area can be reduced by using a positive resist.

In this exposure step, in addition to the above-described pattern, a pattern of two alignment marks for forming a phase shift pattern is simultaneously exposed to a part of the peripheral portion of the mask substrate. Although not particularly limited, this pattern is, for example, 1
A cross mark having a size of about 00 μm is used. Further, in addition to the above-mentioned pattern, a pattern for an alignment mark with a semiconductor wafer is simultaneously exposed to the periphery of the above-mentioned transfer region of the mask substrate. The pattern of the alignment mark is specified corresponding to the reduction projection exposure apparatus.

After such drawing processing, the resist film in the exposed region of the positive resist and the unexposed region of the negative resist is removed with a developing solution (step 204). After the development, the light-shielding film exposed from the pattern of the resist film is removed by etching. The etching of the light-shielding film can be performed by wet etching of, for example, cerium nitrate, secondary ammonium, or the like (Step 205). After such an etching process, the resist film is removed, and a cleaning process is performed on the mask substrate (Step 206).

After forming the pattern of the light shielding film described above,
A chemically amplified electron beam resist is applied on the mask substrate, and a conductive polymer is applied thereon (step 207). Thereafter, the position of the cross mark for alignment described above is detected using an electron beam drawing apparatus, the coordinate system of the pattern of the light-shielding film formed on this mask substrate is adjusted, and the desired pattern is obtained by irradiating an electron beam. Is drawn at a predetermined position. Here, the pattern to be irradiated with the electron beam is a pattern to be a phase shift region (φ = π region). Regarding the writing accuracy of the electron beam writing apparatus, since the pattern superposition can be set to, for example, 0.1 μm or less, this method can be applied to a photomask (reticle) of an exposure apparatus having a reduction rate of 1/5. As the electron beam resist, for example, a chemically amplified positive resist is used (Step 208).

Subsequently, after the baking process, the exposed portion of the resist is removed by performing a developing process to form a resist pattern (step 209). Depending on the combination of the chemically amplified electron beam resist material and the conductive polymer material, the conductive polymer may be washed and removed before baking.

Thereafter, by performing an etching process using the resist pattern as a mask, a groove having a predetermined depth is formed in a selective region on the mask substrate to form a phase shift pattern (step 210). The depth d of this groove is as follows, where λ is the wavelength of the exposure light and n is the refractive index of the mask substrate material.
It is sufficient to set d so that the relationship of d = λ / 2 (n−1) is satisfied. However, it is possible to improve the groove forming accuracy by adopting the following method for determining the etching end point.

First, for example, a parallel plate type plasma etching process is performed as the etching process. As an etching gas, for example, CF4 or CHF3 can be used. The problematic etching conditions are set by the etching time. In this case, the reproducibility of the plasma etching is not sufficient for the target phase difference error. Therefore, when a phase shift pattern is formed by forming a groove on a mask substrate by etching, first, a groove having a depth of about 90% of a target depth is formed by dry etching to set a time, Subsequently, a phase difference is optically measured between the etched region and the unetched region, and an error from a depth of the groove at which a target phase difference can be obtained is obtained. When optically measuring the phase difference, a resist pattern is still formed on the mask substrate, and the unetched region relative to the etched region is locally exposed on the mask substrate before the dry etching process. The method of masking was adopted.

A method may be used in which the relative phase difference between the measurement location and the reference substrate is stored before etching, and the same location is compared after etching. In any case, an error with respect to the target etching depth is obtained by the phase difference measurement after the above-mentioned etching process (Step 2).
11). Thereafter, wet etching is performed on the mask substrate using an aqueous solution of hydrofluoric acid (HF) (Step 21).
2). Accordingly, it is possible to reduce an error with respect to a desired depth of the groove, to reduce damage to the surface of the mask substrate caused by the dry etching process, to make the surface smooth, and to reduce fine foreign matter adhering to the mask substrate surface. It becomes possible. In other words, by this wet etching process, it is possible to accurately form a phase shift pattern composed of grooves having a desired depth on the mask substrate, and to reduce dry etching damage and attached foreign matter. Therefore, manufacturing variations between photomasks can be substantially reduced, and the phase difference of light transmitted through the mask can be set to a desired value.

After such an etching process, the resist is removed, a cleaning process is performed on the mask substrate, and a phase shift with a small phase difference error of the transmitted light is performed through the photomask appearance inspection process (process 106). A photomask having a pattern can be manufactured.

Such an etching method (a method using a combination of a dry etching method and a wet etching method) is applied to a step of correcting a region where a region where a phase shift pattern should be formed originally was not formed due to a defect. Can be.

First, a focused ion beam is applied to the light transmitting region including the defective portion to remove the mask substrate portion by sputtering, and the mask substrate has a predetermined depth of about 9 mm.
A groove having a depth of about 0% is formed by setting the ion beam irradiation time or the number of scans. This focused ion beam processing method is described in, for example, Japanese Patent Application No. Hei.
No. 0. That is, the ion beam emitted from the ion source is narrowed narrowly by a focusing lens or the like, and the irradiated portion is removed by irradiating the ion beam to a predetermined position by a deflector or the like, or a predetermined reaction gas is caused to flow in the irradiation gas. Thus, a technique for forming a predetermined conductor film has been disclosed. Before the ion beam irradiation, the processing speed can be improved by adding a gas that promotes etching to the sample surface.

Also, for example, a coating type transparent film (SOG (Sp
In the case where a phase shift pattern is formed by (in-glass) film, the above-described predetermined gas is added to remove a transparent film for forming the phase shift pattern remaining in an extra area. By using the focused ion beam, the etching selectivity with respect to the mask substrate can be increased, and good pattern formation can be achieved.

Subsequently, the transmitted light of the photomask after the formation of the phase shift pattern is measured and the phase difference is measured in the same manner as described above, an error with a predetermined phase difference is obtained, and the error is eliminated based on the result. For this purpose, a predetermined region of the mask substrate is irradiated with a focused ion beam again to correct the depth of the groove for the phase shift pattern. In this case, the irradiation amount is determined based on a result of measuring an error with the predetermined phase difference. This time, while adding, for example, Zenon Fluoride gas,
By irradiating the focused ion beam, the damage of the mask substrate due to the first ion beam irradiation is reduced, and
A groove having a predetermined depth capable of forming a good phase difference in transmitted light is formed in the mask substrate. As a result, it is possible to correct, with high accuracy, a region where a region where a phase shift pattern should be originally formed was not formed due to a defect.

As described above, in the second embodiment,
Even when the photomask 1 has an auxiliary opening pattern finer than the phase shift pattern or the integrated circuit pattern and distorts the position coordinates of the integrated circuit pattern, it is possible to reliably and easily determine the formation of the pattern and the quality of those patterns. Can be inspected. Therefore, it is possible to manufacture a high quality photomask 1 without defects. In addition, by performing exposure processing using the photomask 1, it is possible to favorably provide a phase difference to transmitted light in the exposure processing, increase the resolution and depth of focus of an image, and reduce Since the overlay accuracy can be improved, an integrated circuit pattern having a desired shape and dimensions can be favorably transferred onto a semiconductor substrate.
Therefore, the yield, reliability, and performance of the semiconductor device can be improved.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, in the first and second embodiments, the regions having the optical proximity effect correction pattern and the phase shift pattern are provided with regions that are paired with the photomask, and the patterns in these regions are compared with each other. Although the case where the inspection is performed has been described, the present invention is not limited to this. For example, when a small oblique figure pattern or a specific shape figure pattern is present on a photomask, a pair is formed with a region having those figures. , A region having the same pattern configuration as that region is provided on the photomask,
The pattern appearance inspection may be performed by comparing the patterns in those areas. Examples 1 and 2
Has described the case where the present invention is applied to a method of manufacturing a DRAM. However, the present invention is not limited to this, and various applications are possible. For example, an SRAM or a flash memory (EEPROM (Electrically Erasable Programmable
le ROM)) or a logic circuit such as a microprocessor.

In the first embodiment, the present invention is applied to the inspection of a photomask having a region in which a proximity effect correction pattern is arranged near the connection hole pattern in order to correct the distortion of the projection image of the connection hole. However, the present invention is not limited to this. An auxiliary opening pattern is provided near the connection hole pattern to emphasize the edge of the projection image of the connection hole, and a phase shift pattern is arranged there. The present invention can also be applied to the inspection of a photomask having a region in which it is present.

In the first embodiment, an electron beam is used to draw a circuit pattern on a mask.
A laser beam can be used. Conversely, a laser beam is used for the mask appearance inspection, but an electron beam can be used.

In the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technology of the semiconductor device, which is the field of application, has been described. However, the present invention is not limited to this. It can be applied to the manufacturing technology and the like.

[0155]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the stage coordinate system of the mask drawing apparatus and the mask inspection apparatus is distorted by a predetermined amount, and the patterns actually formed on each of a pair of regions on the same photomask substrate are compared with each other. By inspecting the quality of the pattern by comparing, on the photomask substrate, a transfer distortion correction pattern for a finer optical proximity correction effect or a fine phase shift auxiliary pattern or in a transmission area on the integrated circuit pattern After adding the phase shifter pattern described above, the position coordinate distortion of the projection exposure optical system can be corrected, and the quality of the corrected pattern can be reliably and easily inspected. Therefore, it is possible to manufacture a photomask with no defects and with little transfer pattern distortion and high overlay accuracy.

(2) According to the present invention, the first region and the second region
By separately performing shot decomposition and exposure processing of the pattern data for each region with a time difference, it becomes possible to detect a pattern abnormality caused by a mask drawing apparatus used for forming a photomask pattern.

(3) According to the present invention, by performing exposure processing using the masks of (1) and (2), circuit pattern distortion correction such as optical proximity correction and transfer pattern position in the exposure processing. It is possible to satisfactorily transfer an integrated circuit pattern of a desired shape and size onto a semiconductor substrate because distortion correction can be performed well, image resolution and depth of focus can be increased, and overlay accuracy can be improved. Can be.
Therefore, the yield, reliability, and performance of the semiconductor device can be improved.

(4) According to the present invention, the quality of a pattern is inspected by comparing patterns actually formed in a pair of regions in the same mask with each other, thereby providing a phase shift to the photomask. Even when there is a region where an auxiliary opening pattern finer than a pattern or an integrated circuit pattern is arranged, the quality of the phase shift pattern or the auxiliary opening pattern can be reliably and easily inspected. Therefore, it is possible to manufacture a high quality mask without defects.

(5) According to the present invention, by performing exposure processing using the photomasks of the above (1) and (4), in the exposure processing, the optical proximity effect correction and the phase difference operation of transmitted light can be performed. Since it can be performed well and the resolution and depth of focus of an image can be increased, an integrated circuit pattern having a desired shape and dimensions can be well transferred onto a semiconductor substrate. Therefore, the yield, reliability, and performance of the semiconductor device can be improved.

(6) According to the present invention, in a reduction projection optical apparatus, when a 5X stepper and a 4X scanner are combined to form a circuit pattern, overlay accuracy can be improved. Further, even when the transfer position accuracy of the projection lens is insufficient, the position coordinates of the mask pattern can be distorted to transfer the integrated circuit pattern onto the wafer satisfactorily. Therefore, the yield, reliability, and performance of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is an overall plan view of a photomask used in the method for manufacturing the semiconductor device of FIG. 1;

FIGS. 3A, 3B, and 3C are plan views of a main portion of the photomask for explaining an optical proximity effect correction pattern formed on the photomask of FIG. 2;

FIG. 4 is a position error display diagram showing an example in which reference mark patterns of an equal interval array formed on a photomask are transferred onto a wafer by light reduction projection exposure, and position errors of the mark patterns are enlarged and displayed.

5 is an explanatory diagram of a position correction vector of a pattern formed by correcting the position error in FIG. 4 on a photomask by distortion correction.

FIG. 6 is an explanatory diagram of a method of performing a coordinate conversion of a position error on the photomask of FIG. 5 and correcting and inspecting a position coordinate of a formed pattern.

FIG. 7 is an explanatory diagram of a mask drawing apparatus used in the method for manufacturing the semiconductor device of FIG. 1;

FIG. 8 is an explanatory diagram of a mask inspection apparatus used in the method for manufacturing the semiconductor device of FIG. 1;

FIG. 9 is an explanatory diagram of an electron beam exposure apparatus used in the method for manufacturing the semiconductor device of FIG. 1;

10 is an explanatory diagram of a main part of the electron beam exposure apparatus of FIG.

11 is an explanatory diagram of a main part of the electron beam exposure apparatus of FIG.

12 is a fragmentary cross-sectional view of a specific semiconductor device during a manufacturing step of the semiconductor device of FIG. 1;

13 is a fragmentary cross-sectional view of a specific semiconductor device during a manufacturing step of the semiconductor device of FIG. 1;

14 is a fragmentary cross-sectional view of a specific semiconductor device during a manufacturing step of the semiconductor device of FIG. 1;

15 is a fragmentary cross-sectional view of a specific semiconductor device during a manufacturing step of the semiconductor device of FIG. 1;

16 is a fragmentary cross-sectional view of a specific semiconductor device during a manufacturing step of the semiconductor device of FIG. 1;

17 is a fragmentary cross-sectional view of a specific semiconductor device during a manufacturing step of the semiconductor device of FIG. 1;

18 is a fragmentary cross-sectional view of a specific semiconductor device during a manufacturing step of the semiconductor device of FIG. 1;

19 is a fragmentary cross-sectional view of a specific semiconductor device during a manufacturing step of the semiconductor device of FIG. 1;

FIG. 20 is a flowchart showing a photolithography process in the manufacturing process of the semiconductor device shown in FIGS. 12 to 19;

FIG. 21 shows reference mark patterns of 0, 90, and 180 degrees.
FIG. 14 is a diagram illustrating a measurement example of alignment of a mask drawing position by measuring position coordinates by rotating by 270 degrees and reducing the difference between measurement patterns.

FIGS. 22A and 22B are plan views of a main part of the photomask for describing the optical proximity effect correction pattern formed on the photomask of FIG. 2;

FIGS. 23A and 23B are plan views of a main part of the photomask for describing the optical proximity effect correction pattern formed on the photomask of FIG. 2;

FIGS. 24A and 24B are plan views of a main portion of the photomask for explaining the optical proximity effect correction pattern formed on the photomask of FIG. 2;

FIGS. 25A and 25B are plan views of a main portion of the photomask for describing the optical proximity effect correction pattern formed on the photomask of FIG. 2;

FIG. 26 is a flowchart illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

27A is a cross-sectional view of a main part of a photomask used in the method for manufacturing the semiconductor device of FIG. 21, and FIG. 27B is a cross-sectional view taken along line AA of FIG.

28A is a cross-sectional view of a main part of a photomask used in the method for manufacturing the semiconductor device of FIG. 21, and FIG. 28B is a cross-sectional view taken along line AA of FIG.

29A is a cross-sectional view of a main part of a photomask used in the method for manufacturing the semiconductor device of FIG. 21, and FIG. 29B is a cross-sectional view of the photomask taken along line AA.

30A is a cross-sectional view of a main part of a photomask used in the method for manufacturing the semiconductor device of FIG. 21, and FIG. 30B is a cross-sectional view taken along line AA of FIG.

FIG. 31 is a flowchart illustrating a method for manufacturing a photomask used in the method for manufacturing the semiconductor device in FIG. 1;

FIG. 32A is an explanatory diagram of a phase shift mask exposure,
(B) is an explanatory view of oblique illumination exposure and modified illumination exposure.

FIG. 33 is an explanatory diagram showing a hierarchical structure of mask data used in the method for manufacturing the semiconductor device of FIG. 1;

[Explanation of symbols]

 Reference Signs List 1 photomask 2 mask substrate 3 light-shielding band 4 mask inspection device 4A XYθ stage 4B stage drive system 4C stage control unit 4D laser interferometer 4E inspection light source 4F1, 4F2 lens 4G image sensor 4H storage unit 4I image data comparison unit 5 electron beam exposure Device 5A Stage 5B Electron beam source 5C1 First aperture 5C1a Opening pattern 5C2 Second aperture 5C2a Opening pattern 5C3 Third aperture 5D Blanking electrode 5E Electron lens 5F1 First deflector 5F2 Second deflector 5F3 Third deflector 5G Laser interference 5H control computer 5I drawing data storage unit 5J buffer memory 5K calculation unit 5L blanking signal generation unit 5LC blanking control 5M first deflection control signal generation unit 5MC first deflection control unit 5N second deflection control signal generation unit 5NC second Direction control unit 5P Movement control signal generation unit 5PC Movement control unit 5Q Third deflection signal generation unit 5QC Third deflector control unit 5R Stage control unit 5S Electronic detector 5T Signal processing unit 5U1, 5U2 Stage 6a0 Rectangular opening pattern 6a1 to 6a5 Batch transfer pattern 7 Semiconductor wafer 7s Semiconductor substrate 8n n well 8p p well 9 Field insulating film 10g Gate electrode 10i Gate insulating film 10pd Semiconductor region 10nd Semiconductor region 11a to 11c Interlayer insulating film 12L First layer wiring 12R Resistance 13a, 13b Connection hole 14a Metal film 14L Second layer wiring 15L Third layer wiring 16 Surface protective film 17a-17h Opening pattern 18a-18i Phase shift pattern 19a-19g Auxiliary opening pattern A, B Chip transfer area A00, B00 Peripheral circuit area A11 Memory circuit area (1st territory A12, A21 Memory circuit area (second area) A22 memory circuit area B11 Memory circuit area (second area) B12, B21, B22 Memory circuit area TH Connection hole pattern H1 to H6 Correction pattern L1, L2 Wiring pattern L1a Large area Pattern part L1 Lead pattern part L2a Wide pattern part L2b Lead pattern part L3 Rectangular pattern L3a Rectangular pattern EB Electron beam S Light shielding film S1 Light shielding pattern.

Claims (13)

[Claims] 1. A method for manufacturing a photomask for forming a pattern on a semiconductor wafer by exposing a pattern formed on a photomask substrate using a reduction projection exposure apparatus, the method comprising the steps of: In the area 2, correction for correcting pattern dimension distortion or pattern shape distortion due to reduced projection exposure of about 1/3 or less of the pattern width corresponding to the circuit pattern data constituting the pattern of the semiconductor integrated circuit. Forming a pattern data, synthesizing them, sequentially exposing them to first and second regions to form a pattern, and comparing and visually inspecting the patterns of the first and second regions. Production method. 2. A method of manufacturing a photomask for forming a pattern on a semiconductor wafer by exposing a pattern formed on a photomask substrate using a reduction projection exposure apparatus, the method corresponding to a pattern of a semiconductor integrated circuit. Then, pattern data for imaging a pattern on the semiconductor wafer using light interference between the transmitted light having light transmitting regions where the phases of the transmitted light are mutually inverted is prepared, In each of the first and second regions, a pattern having a phase inversion boundary in the transmission portion or １ ／ of the circuit pattern width
A method of manufacturing a photomask, comprising sequentially exposing a phase inversion pattern of a degree or less to form a pattern, and comparing the patterns of the first and second regions with each other in appearance. 3. A method for manufacturing a semiconductor device, comprising: exposing a pattern formed on a photomask onto a semiconductor wafer by using a reduction projection exposure apparatus, the method comprising: The position shift amount of the pattern of the projection pattern on the semiconductor wafer caused by the above is obtained in advance, and when drawing the pattern of the photomask according to the position shift amount, the stage coordinate of the pattern drawing apparatus is shifted and drawn. The method of manufacturing a semiconductor device according to claim 1, wherein a pattern displacement generated on the semiconductor wafer is reduced. 4. A method of manufacturing a semiconductor device, comprising: exposing a pattern formed on a photomask onto a semiconductor wafer by using a reduction projection exposure apparatus, wherein the method includes: The position shift amount of the pattern of the projection pattern on the semiconductor wafer caused by the above is obtained in advance, and when drawing the pattern of the photomask according to the position shift amount, the stage coordinate of the pattern drawing apparatus is shifted and drawn. Thereby, the positional deviation of the pattern generated on the semiconductor wafer is reduced, and the distortion of the pattern shape or the dimensional shape of the projected pattern on the semiconductor wafer caused by the optical system or the illumination form of the projection exposure apparatus is predicted in advance. And a semiconductor device for drawing by distorting a photomask pattern in order to reduce the distortion of the dimension and shape. Manufacturing method. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of inspecting a photomask, wherein a mask inspection apparatus is provided for a portion which is drawn by shifting a stage in said pattern drawing step. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the inspection is performed by similarly shifting the position coordinates. 6. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of inspecting a photomask, wherein a correction pattern is added or deleted in consideration of said pattern dimension shape distortion in said pattern drawing step. For parts,
5. The method according to claim 4, wherein a similar pattern is formed on the photomask at the time of drawing the mask pattern, and a comparative inspection is performed. 7. The correction pattern for pattern dimension and shape distortion limits a pattern arrangement in which distortion is expected to be large due to the projection exposure apparatus, and extracts a portion having the pattern arrangement from circuit pattern data. 5. The method according to claim 4, wherein the correction pattern is added or deleted. 8. A pattern arrangement in which distortion is expected to be large due to the projection exposure apparatus is a line and space pattern, and a correction pattern is added to or deleted from an end pattern of the line and space pattern. The method for manufacturing a semiconductor device according to claim 7, wherein: 9. A method for manufacturing a photomask used in a photolithography step for manufacturing a semiconductor device, comprising:
(A) obtaining a relative position error from design data of position coordinates of a transfer pattern obtained by reducing and projecting a pattern formed on a photomask substrate onto a semiconductor wafer by using a reduction projection exposure apparatus; A step of creating the pattern data to be composed and correction pattern data for correcting pattern dimension distortion or pattern shape distortion due to reduced projection exposure; and (c) changing the stage coordinates of the mask pattern drawing apparatus to reduce the relative position error. And (d) correcting the stage coordinates of the inspection apparatus at the time of mask inspection for a portion drawn by correcting the stage coordinates of the pattern writing apparatus at the time of mask pattern writing. A step of performing an appearance defect inspection, and (e) a step of correcting a location where a defect is found by the inspection,
And a method for manufacturing a photomask. 10. The method of manufacturing a photomask according to claim 9, wherein the stage coordinate correction amount at the time of pattern writing and the stage coordinate correction amount at the time of inspection are errors from an ideal lattice point. 11. The correction of the stage coordinates of the pattern drawing apparatus and the pattern inspection apparatus is performed by setting the photomask surface corresponding to the transfer area of the optical system of the reduction projection exposure apparatus to 5 mm.
Is divided into meshes at equal intervals of about 20 mm, x and y correction amounts are set with one point in each mesh as a representative point, and linear or curve approximation with the correction amount between meshes is performed to correct the mask plane. 11. The method according to claim 10, wherein
3. The method for manufacturing a photomask according to 1. 12. A mask drawing apparatus for exposing an integrated circuit pattern on a photomask substrate, wherein when drawing the integrated circuit pattern on the photomask substrate, the coordinates of the stage on which the mask of the drawing apparatus is mounted are determined on the stage. A plurality of two-dimensional position coordinate correction maps corresponding to the two-dimensional coordinate positions, and performing a correction process on the position coordinate data of the integrated circuit pattern using one of the correction maps;
A mask drawing apparatus having a function of drawing a pattern. 13. An inspection apparatus for inspecting the appearance or position coordinates of a mask having an integrated circuit pattern formed on a photomask substrate, wherein the coordinates of the stage on which the mask is mounted correspond to two-dimensional coordinate positions on the stage. A mask inspection apparatus, comprising: a plurality of two-dimensional position coordinate correction maps; and a function of inspecting the appearance or position coordinates of the integrated circuit pattern using one of the correction maps.