JPH11298440A - Ofdm-based transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an OFDM transmitter compatible with many transmission modes where symbol lengths are not uniform. SOLUTION: A buffer control means 2 of this transmitter selects a buffer 1 or 2 by alternately writing a flag to select the buffer to output modulated data generated by an arithmetic processing means 1 and sets output-inhibit to a buffer making data output and sets output-enable to the other when either of the buffers outputting modulated data outputs a switching flag. In an arithmetic processing to generate modulated data of one symbol length, a flag to switch the buffer is added to an arithmetic operation result and a switching timing is automatically generated from transmitted information. Thus it is not required to provide information relating to the symbol length to a part relating to switching control and one simple control means can select a buffer for any symbol length.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to OFDM (Orthog
The present invention relates to an onal frequency division multiplex (TX) transmission device, and more particularly, to an OFDM transmission device used in the field of broadcasting and communication using digital modulation technology.

[0002]

2. Description of the Related Art As in digital television broadcasting,
There is an increasing need to transmit coded digital video signals efficiently. One of the methods for transmitting an encoded digital video signal or the like in a limited frequency band is an OFDM method. In particular, among terrestrial digital broadcasting transmission systems, an OFDM transmission system that is resistant to multipath is considered promising. The OFDM transmission system is a type of multi-carrier modulation system in which a large number of carriers are arranged orthogonally, and independent digital information is transmitted on each carrier. As a modulation method of each carrier, QPSK, 16 quadrature amplitude modulation (QAM: Quadrature Amplitude Modulatio
n), 64QAM, 256QAM, etc. are used.

[0003] Data transmission by the OFDM transmission method is performed in units of transmission symbols. Each transmission symbol includes a period called an effective symbol period and a period called a guard band period (guard interval). An effective symbol period is a signal period substantially required for data transmission. The guard interval is a redundant signal period for reducing the influence of multipath, and is a cyclically repeated signal waveform in an effective symbol period. Approximately several tens to several hundreds of transmission symbols are collected to form one transmission frame. This OFDM transmission frame includes a frame synchronization symbol in addition to a data transmission symbol.

[0004] In a transmitting apparatus, binary transmission data is divided into data blocks each having a certain number of bits, and each data block is input after being converted into one complex value. A serial-parallel converter gives one complex value for each carrier frequency, and an inverse discrete Fourier transform circuit performs inverse discrete Fourier transform on the time axis. Thus, a sample value of the time axis waveform is generated, and a temporally continuous baseband analog signal waveform is obtained from the sample value sequence. The baseband analog signal waveform is converted to a transmission frequency by a frequency converter and transmitted.

[0005] In a receiving apparatus, after a received signal is frequency-converted by a frequency converter to obtain a baseband signal waveform,
Sample at the same sample rate as the sender. This sample value sequence is subjected to discrete Fourier transform on the frequency axis by a discrete Fourier transform circuit unit, the value of the received data is obtained by calculating the phase and amplitude of each carrier frequency component, and converted to serial by a parallel-serial converter. Output. The reception of the OFDM signal detects the amplitude and phase modulation components of the signal transmitted within the symbol period, and decodes the value of the information based on these levels. Since the frequency components of the multipath signal in the same symbol section and the signal to be received are the same, decoding is performed except for the signal in the first guard interval period, so that a decoded digital signal with a relatively narrow frequency band and little transmission distortion is obtained. Can transmit data.

A conventional OFDM transmitting apparatus is disclosed in Japanese Patent Laid-Open No. 9-3683.
As in the device disclosed in Japanese Patent Application Laid-Open No. 5 (1999) -2005, it is configured to perform arithmetic processing on input data and transmit modulated data generated by the arithmetic via a buffer.

Further, as in the device disclosed in Japanese Patent Application Laid-Open No. 9-135230, the output from a plurality of arithmetic processing means corresponding to the type of the symbol length is switched by switching control means to generate a switching timing, and a symbol unit is used. Was switched and sent.

[0008]

In OFDM transmission, there are several transmission modes having different symbol lengths, and the symbol length is not uniform even in one transmission mode.
The conventional OFDM transmission apparatus has a configuration in which modulated data generated by calculation is written into a plurality of buffers, and switched and output in symbol units. In order to generate the switching timing in accordance with the symbol length of the modulation data to be transmitted, the switching control means itself must have information on the symbol length. Therefore, there is a disadvantage that the scale of the switching control means becomes large when trying to correspond to all kinds of symbol lengths and change patterns. There was also a disadvantage that the hardware became bloated due to the need for multiple buffers.

In OFDM transmission, a method is used in which the same waveform as a part of an effective symbol called a guard interval is added to the beginning of a symbol to make one symbol. In order to write all the modulation data for one symbol in the buffer, it is necessary to write the overlapping guard interval phase equivalents, which requires extra writing time. As a result, the time spent for other arithmetic processing is reduced, which has been a factor for using expensive arithmetic means for improving the arithmetic processing speed and increasing the number of arithmetic circuits for performing parallel processing.

[0010] In OFDM transmission, there is a method in which a frame is composed of several consecutive symbols, and a synchronization symbol having the same pattern is inserted into one frame every frame. In the conventional OFDM transmission apparatus, the modulation data is generated by calculation and written to the buffer each time the modulation data of the synchronization symbol is output. This results in an increase in the amount of arithmetic processing, which results in the use of expensive arithmetic means for improving the arithmetic processing speed and an increase in the number of arithmetic circuits for performing parallel processing.

In OFDM transmission / reception, a synchronization signal output is often used separately from a modulated data output to ensure synchronization between devices. Therefore, it is necessary to separately provide a means for generating a synchronization signal.

[0012] In order to solve the above-mentioned problems, the present invention provides an excellent OFDM transmission apparatus which can control switching timing of a buffer freely by providing switching information in an operation result to be written into the buffer. This is the purpose of 1.

It is a second object of the present invention to provide an excellent OFDM transmitting apparatus capable of reducing the number of buffers by using a buffer capable of performing input and output simultaneously.

It is a third object of the present invention to provide an excellent OFDM transmission apparatus capable of reducing the amount of arithmetic processing by eliminating the writing of modulated data in a guard interval portion that is output redundantly.

It is a fourth object of the present invention to provide an excellent OFDM transmission apparatus capable of reducing the amount of calculation processing by omitting generation of modulation data of the same synchronization symbol and writing of the same synchronization symbol in each frame.

It is a fifth object of the present invention to provide an excellent OFDM transmitting apparatus capable of generating a synchronization signal without adding additional hardware.

[0017]

In order to achieve the first object, according to the present invention, an OFDM transmitting apparatus is configured as follows. In the arithmetic processing means, a flag for switching the buffer is written in the buffer together with the modulation data. The buffer is composed of two or more buffers having a bit width larger than the full-scale bit number of the modulation data to be transmitted. Temporarily hold the modulated data and the flag, and switch and output the data.
The output buffer is switched according to the flag output from the buffer. With this configuration, the buffer can be switched using the flag.

Further, in order to achieve the second object,
In the present invention, the OFDM transmission device is configured as follows.
The arithmetic processing means writes a flag for switching the output area together with the modulation data into a buffer, and the buffer
The modulation data to be transmitted is divided into two or more areas having a bit width larger than the full scale bit number, and the modulation data and the flag respectively written are temporarily held, switched and output, and the buffer control means The output area is switched according to the flag output from the buffer. With this configuration, the buffer area can be switched using the flag.

In order to achieve the third object,
In the present invention, the OFDM transmission device is configured as follows.
The arithmetic processing means writes a flag for resetting the output address of the buffer together with the modulation data in the buffer, sets the output start address of the buffer in the buffer control means, and stores the number of full-scale bits of the modulation data to be transmitted in the buffer. It has a larger bit width, temporarily stores and outputs the written modulation data and flag, and the buffer control means controls the output address of the buffer by the set address from the arithmetic processing means and the flag output by the buffer. With this configuration, the buffer address can be controlled by the flag.

In order to achieve the fourth object,
In the present invention, the OFDM transmission device is configured as follows.
In the arithmetic processing means, a flag for switching the output to the memory together with the modulation data is written to the buffer, and the buffer has a bit width larger than the full-scale number of bits of the modulation data to be transmitted, and has a significant width that changes according to the input data. A flag is sequentially written together with the symbol modulation data, and the flag is temporarily stored and output. The memory has a bit width larger than the full-scale bit number of the modulation data to be transmitted, and the modulation data of the same synchronization symbol for each frame. In addition, a flag for switching the output to the buffer is stored in advance, and the buffer control means switches the output to the buffer side according to the flag output from the memory, and switches the output to the memory side according to the flag output from the buffer. With such a configuration, the storage memory for the modulation data of the synchronization symbol can be one.

In order to achieve the fifth object,
In the present invention, the OFDM transmission device is configured as follows.
The arithmetic processing means writes a flag indicating the synchronization point to the buffer together with the modulation data, and the buffer has a bit width larger than the full-scale bit number of the modulation data to be transmitted, and temporarily holds the written modulation data and the flag. And output. With this configuration, it is possible to easily generate the synchronization signal.

[0022]

According to the first aspect of the present invention, there is provided an arithmetic processing means for arithmetically processing input serial data to generate modulated data to be transmitted, and a full-scale bit of the modulated data. In an OFDM transmitting apparatus comprising two or more buffers having a bit width larger than a number and performing switching output, and buffer control means for controlling a switching operation of the buffer, the arithmetic processing means includes: An OFDM transmission apparatus, comprising: means for writing a flag for switching the buffer to the buffer, wherein the buffer control means includes means for switching a buffer to perform output to another according to the flag output by the buffer being output, This has the effect of switching the buffer according to the flag output by the buffer.

According to a second aspect of the present invention, there is provided an arithmetic processing means for performing arithmetic processing on input serial data to generate modulated data to be transmitted, and having a bit number larger than a full-scale bit number of the modulated data. OFDM comprising one buffer having a width and capable of simultaneously performing writing and output by setting an address from both input and output, and buffer control means for controlling an output address of the buffer
In the transmission device, the buffer has two or more regions therein, and the arithmetic processing unit has a unit for writing a flag for switching an output region together with the modulation data in each region of the buffer, The buffer control means is an OFDM transmission apparatus having means for switching from the area being output to another area according to the flag output from the buffer and outputting the same, and has the effect of switching the buffer area according to the flag output from the buffer.

According to a third aspect of the present invention, there is provided an OFDM transmitting apparatus according to the first or second aspect,
The arithmetic processing means has means for writing a flag for resetting an output address of the buffer to the buffer, and the buffer control means sets an output start address of the buffer, and Means for causing the buffer to perform output, means for resetting the output address by a flag issued by the buffer, and means for generating modulated data for a guard interval period. This has the effect of resetting the address.

According to a fourth aspect of the present invention, there is provided an OFDM transmitting apparatus according to the first or second aspect,
A memory in which modulation data of the same synchronization symbol for each frame is stored in advance; and the arithmetic processing unit has a unit for sequentially writing modulation data of a significant symbol that changes according to input data to the buffer, and At this time, there is provided means for outputting modulation data from the memory and outputting modulation data from the buffer during other periods, and has an effect of reading out the modulation data of the synchronization symbol from one memory.

According to a fifth aspect of the present invention, there is provided an arithmetic processing means for performing arithmetic processing on input serial data to generate modulated data to be transmitted, and having a number of bits larger than a full-scale bit number of the modulated data. In an OFDM transmission device having a buffer having a bit width, the arithmetic processing means has means for writing a flag indicating a synchronization point together with the modulation data to the buffer, and using the flag output from the buffer as a synchronization signal. This is an OFDM transmission device provided with a transmitting unit, and has an operation of generating a synchronization signal based on a buffer flag.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described in detail with reference to FIGS.

(First Embodiment) In a first embodiment of the present invention, an arithmetic processing means writes a flag for switching a buffer together with modulated data into a buffer, and a buffer control means outputs a buffer being output. Switches the output buffer to another according to the flag output by
It is a transmitting device.

FIG. 1 shows an OF according to a first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a DM transmission device. In FIG. 1, an arithmetic processing means 1 is means for performing arithmetic processing on serial data. The buffer control means 2 is a means for switching buffers. The buffers 3 and 4 are memories for temporarily storing modulated data.

The arithmetic processing means 1 performs arithmetic processing on the input serial data based on the transmission mode to generate modulated data, and then, together with the modulated data, sets a flag for switching a buffer (hereinafter referred to as a switching flag). Write to buffer. The buffer control means 2 controls an output switching operation of the buffer. The buffer (1) and the buffer (2) are temporary memories having a bit width larger than the full-scale number of bits of the modulation data to be transmitted, and temporarily store and output the written modulation data and the switching flag.

First, the write operation from the arithmetic processing means 1 to each buffer will be described. At the time of start-up, all buffers have not been written with modulated data, so that the buffer control means 2 puts them in an output-prohibited state, and no data is output from any of them. First, the arithmetic processing means 1 writes the modulated data generated by performing the operation in units of one symbol to the buffer (1). At the last address of one symbol data, a switching flag is also written together with the modulation data. The switching flag uses bits of the modulation data that are not used for transmission. When the writing of the data of one symbol is completed, the buffer control means 2 sets the buffer (1)
Is in an output permission state, and the buffer (1) starts outputting modulated data.

In parallel with the output of data from the buffer (1), the arithmetic processing means 1 performs a similar write operation on the buffer (2). At the last address of one symbol data, a switching flag is also written together with the modulation data. At the time of completion of the writing, the buffer (2) enters an output waiting state, and stops the operation without performing the output while waiting for the output of the buffer (1) to end. Thereafter, writing is again performed on the buffer (1). If the buffer (1) is still outputting, the writing is waited until the output is completed, and the writing is started as soon as the output is completed.

Next, the output operation of the buffer will be described with reference to FIG. FIG. 2 shows how the output buffer is switched by the switching flag. When the output of the buffer (1) reaches the final point of one symbol and the switching flag a is output, the buffer is output. Control means 2
Puts the buffer (1) into the output prohibited state, puts the buffer (2) waiting for output into the output permitted state, and causes the buffer (2) to output. Similarly, when the output of the buffer (2) reaches the final point of one symbol and the switch flag b is output, the buffer control unit 2 sets the buffer (2)
Are set to the output prohibited state, the buffer (1) is set to the output enabled state, and the buffer (1) outputs the data.

In this way, the output buffer is switched in sequence, and the modulated data is transmitted continuously without interruption.

Here, the arithmetic processing means 1 adds a switching flag to the end point of one symbol in the process of generating the modulation data based on the transmission mode and writes it in the buffer at a time. Buffer switching is performed.

The write position of the switching flag in each buffer is determined by taking into account the delay caused by hardware and the like.
It is not always necessary to set the last address of one symbol, but it is also possible to set it to the address one or two before. Alternatively, the switching flag may be set so that the buffer is switched in units of a plurality of symbols, such as for each frame instead of for each symbol.

As described above, in the first embodiment of the present invention, the OFDM transmitting apparatus writes the flag for switching the buffer together with the modulation data into the buffer by the arithmetic processing means, Since the buffer is switched according to the output flag, modulated data can be transmitted continuously without interruption even if the symbol length changes.

(Second Embodiment) In a second embodiment of the present invention, two or more areas are provided inside a buffer, and an output area is provided together with modulation data in each area of the buffer by arithmetic processing means. Write a flag to switch,
This is an OFDM transmission device that switches an output area according to a flag by a buffer control unit.

FIG. 3 shows an OF according to a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a DM transmission device. In FIG. 3, the arithmetic processing unit 1 performs arithmetic processing on serial data input based on a transmission mode to generate modulation data to be transmitted, and then sets a flag (hereinafter, jump) for switching an output area together with the modulation data in a buffer. (Referred to as a flag). The buffer 5 has a bit width larger than the full scale of the modulation data to be transmitted, has an address set from both input and output, is a single buffer capable of writing and outputting at the same time, and internally has two or more areas. Used separately. Buffer control means 6
Is a means for controlling the output address of the buffer 5 by the jump flag output from the buffer 5 and switching the output area.

Next, the operation of the OFDM transmitting apparatus according to the second embodiment will be described with reference to FIG. FIG. 4 shows an example in which the inside of the buffer 5 is divided into four areas. The arithmetic processing means 1 writes the jump flag along with the modulation data in order from the area A of the buffer 5 to the area B, the area C, the area D, and again to the area A and the area B. Output is performed sequentially from the area in which writing has been completed. First, output is performed from area A. When the jump flag jA is output at the end point of area A, the output area is switched to area B by buffer control means 6. Be replaced. The area is switched to the area C with the jump flag jB, the area D with the jump flag jC, and the area A again with the jump flag jD. In this way, by repeating these operations repeatedly, modulated data is continuously transmitted without interruption.

As described above, in the second embodiment of the present invention, the flag for switching the output area together with the modulation data in the OFDM transmitting apparatus is divided into two or more areas by the arithmetic processing means. Since the output area is switched in accordance with the flag by the buffer control means by writing to the buffer, the buffer area can be switched by the flag.

(Third Embodiment) In a third embodiment of the present invention, a flag for resetting the output address of the buffer is written into the buffer by the arithmetic processing means, and the output of the buffer is written by the buffer control means. Set the start address, output to the buffer from the output start address,
This is an OFDM transmitter that resets an output address according to a flag and generates modulated data during a guard interval period.

FIG. 5 shows an OF according to a third embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a DM transmission device. In FIG. 5, the buffer control means 2 has a function of controlling the output address of the buffer according to a flag for resetting the output address of the buffer (hereinafter, referred to as a reset flag). The other configuration is the same as the configuration shown in FIG.

First, the write operation from the arithmetic processing means 1 to the buffer will be described with reference to FIG. The arithmetic processing means 1 writes the modulation data for the effective symbol generated by the operation from address A0 of the buffer (1) to address AE, and writes the modulation data transmission and switching flag on the data bus at address AE. Write the reset flag to unused bits. At the same time, since the AE address is also the end point of one symbol, a switching flag is written. Then, writing is performed again at the start address AG0 of the portion corresponding to the guard interval, the output start address AG0 of the buffer (1) 3 is set in the buffer control means 2, and the writing is completed. Output permission. Here, the order of writing may be such that the modulation data for the effective symbol is written from address A0 to address AE, the reset flag is written into address AE, and the writing is completed with output starting from address AG0. Then, writing is similarly performed on the buffer (2).

Next, the output operation of the buffer will be described with reference to FIG. The buffer (1) for which output is enabled is the AG
The output of the modulation data written from address 0 is started, and a reset flag c is output when the address reaches address AE. The reset flag c allows the buffer control means 2
Resets the output address of buffer (1)
Address 0. Then, the output from the address A0 is performed, and the address reaches the address AE again via the address AG0, and the output buffer is switched to the buffer (2). Similarly, the buffer (2) also starts outputting from address AG0 and reaches AE, outputs a reset flag d, and outputs A from address AG0.
The data is output from the address G0 to the address AE.

As described above, the effective symbol period A0
A part of the address from the address AE to the address AE is redundantly output from the address AG0 to the address AE and transmitted as a guard interval period.

Normally, the end point of the guard interval coincides with the AE address of the effective symbol end point, but it is also possible to arbitrarily write a reset flag at another position to generate a guard interval.

As described above, in the third embodiment of the present invention, the OFDM transmission apparatus writes the flag for resetting the output address of the buffer together with the modulation data into the buffer by the arithmetic processing means, and outputs the buffer. Since the start address is set in the buffer control means, and the buffer control means controls the output address of the buffer by the set address and the flag, the buffer address can be controlled by the flag.

(Fourth Embodiment) In a fourth embodiment of the present invention, modulation data of a synchronization symbol is stored in a memory in advance, and a significant symbol changed by input data is calculated by arithmetic processing means. This is an OFDM transmission apparatus that sequentially writes modulation data to a buffer, outputs synchronization symbol modulation data from a memory during a synchronization symbol period, and outputs modulation data of input data from the buffer during other periods.

FIG. 8 shows an OF according to a fourth embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a DM transmission device. In FIG. 8, a synchronization symbol memory 7 is a memory in which a switching flag is stored in advance together with modulation data of the same synchronization symbol for each frame, and a flag for switching output from a buffer to the memory (hereinafter referred to as a synchronization switching flag). ) Is separately provided for another bit on the data bus. The other configuration is the same as the configuration shown in FIG.

Next, the operation of the OFDM transmitting apparatus according to the fourth embodiment will be described. In the period of the significant symbol that changes according to the input serial data, the arithmetic processing unit 1 generates the modulation data by the sequential calculation,
The buffer (1) and the buffer (2) are alternately written, and the same operation as that described in the first embodiment is repeated, so that the modulated data is alternately output from the buffer (1) and the buffer (2). You. Therefore, between the series of operations, a synchronization switching flag is written at the end point of the symbol immediately preceding the synchronization symbol, and when the synchronization switching flag is output from the buffer, the buffer switching means 2 disables the output of the buffer. The synchronization symbol memory 7 is permitted to output, and the modulation data of the synchronization symbol is output. When the switching flag 9 stored in advance is output from the synchronous symbol memory 7 at the end of the synchronous symbol period, the output of the synchronous symbol memory 7 is again inhibited by the buffer control means 2 and the output of the buffer is permitted. , Switch to the modulated data output of the significant symbol.

Here, the order of switching by the switching flag is as follows: a is switched to the buffer (2), b is switched to the buffer (1), e is switched to the synchronous symbol memory 7, f is switched to the synchronous symbol 7, and g is switched to g. In the case of, if the front of g is e, the buffer is switched to buffer (2), and if the front of g is f, the buffer is switched to buffer (1).

In this way, the modulation data of the synchronization symbol is transmitted during the synchronization symbol period, and the modulation data of the significant symbol is transmitted during the other periods.

In the fourth embodiment, the synchronous symbol memory 7 uses a nonvolatile storage means such as a ROM. However, the synchronous symbol memory 7 is activated once by the arithmetic processing means using a RAM. May be generated and written.

As described above, in the fourth embodiment of the present invention, the OFDM transmitting apparatus stores in advance the flag for switching the output to the buffer together with the modulation data of the synchronization symbol in the memory, In the processing means,
With the modulation data, a flag for switching the output to the memory is written in the buffer, and the buffer control means switches the output to the buffer side by the flag output from the memory, and switches the output to the memory side by the flag output from the buffer. Therefore, the storage memory for the modulation data of the synchronization symbol can be one.

(Fifth Embodiment) In a fifth embodiment of the present invention, the arithmetic processing means writes a flag indicating a synchronization point together with modulation data into a buffer, and uses the flag output from the buffer as a synchronization signal. This is an OFDM transmitting apparatus for transmitting.

FIG. 9 shows an OF according to a fifth embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a DM transmission device. In FIG. 9, the arithmetic processing means 1 is means for performing arithmetic processing on input serial data and writing a flag indicating a synchronization point (hereinafter, referred to as a synchronization flag) together with modulation data in a buffer. The buffer 8 is a buffer having a bit width larger than the full-scale bit number of the modulated data to be transmitted, which temporarily stores and outputs the written modulation data and the synchronization flag.

The modulation data is written from the arithmetic processing means 1 to the buffer 8. At the synchronization point, a synchronization flag is also written together with the modulation data. The synchronization flag is written in bits not used for modulation data transmission on the data bus. The buffer 8 temporarily holds the written modulation data and the synchronization flag, outputs the written modulation data at the time of output, and outputs the synchronization flag at the synchronization point,
The synchronization flag is transmitted as a synchronization signal.

Here, if a synchronization flag is written at a symbol-to-symbol breakpoint, a synchronization signal with a symbol period can be obtained, and the synchronization flag is set only during a specific symbol period of a frame composed of several consecutive symbols. By writing, a synchronization signal of the frame period can be obtained.

As described above, in the fifth embodiment of the present invention, the OFDM transmitting apparatus writes the flag indicating the synchronization point together with the modulation data into the buffer by the arithmetic processing means.
Since the buffer is configured to temporarily hold and output the written modulation data and flag, it is possible to easily generate a synchronization signal.

[0061]

As described above, according to the present invention, OFD
A configuration in which, in the M transmitting apparatus, a flag for switching the buffer together with the modulated data is written into the buffer by the arithmetic processing means, and the buffer for outputting is switched by the buffer control means to another buffer according to the flag output by the buffer being output. Therefore, a flag for switching the buffer is added to the calculation result in the process of generating the modulation data of one symbol length, and the switching timing is automatically generated from the information transmitted. Therefore, it is not necessary to provide information relating to the symbol length in the portion related to the switching control, and the effect that the switching operation can be performed on one simple control means regardless of the symbol length is obtained. Can be

Further, by using a buffer capable of simultaneously writing and outputting and dividing the inside of the buffer into two or more areas, one buffer can be used as if it were a plurality of buffers. Is required, it is possible to reduce the number of buffers.

Further, by using a flag for resetting an address and outputting a part of the effective symbol period twice to generate modulated data for the guard interval period, it is not necessary to separately write data for the guard interval to the buffer. The load on the arithmetic processing means can be reduced, and the use of inexpensive arithmetic processing means with low processing capacity
Alternatively, the effect of increasing the possibility of reducing the number of arithmetic processing means for performing parallel processing is obtained.

Further, the modulation data of the synchronization symbol having the same pattern every frame is stored in the memory as a table, and the data is switched from the buffer in which the modulation data of the significant symbol is written to be output. Since it is not necessary to perform writing every time and the load on the arithmetic processing means can be reduced, there is an effect that the possibility of using an inexpensive arithmetic processing means with low processing capacity or reducing the arithmetic processing means for performing parallel processing increases. can get.

Further, since a flag is set at a synchronization point and a synchronization pulse is automatically generated from information to be transmitted, a synchronization signal can be easily generated without separately providing synchronization generation means. The effect of being able to generate is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an OFDM transmitting apparatus according to a first embodiment of the present invention;

FIG. 2 is an explanatory diagram of an output operation of the OFDM transmitting apparatus according to the first embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of an OFDM transmitting apparatus according to a second embodiment of the present invention;

FIG. 4 is an explanatory diagram of a buffer of an OFDM transmitting apparatus according to a second embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of an OFDM transmitting apparatus according to a third embodiment of the present invention;

FIG. 6 is an explanatory diagram of a write operation of an OFDM transmission device according to a third embodiment of the present invention;

FIG. 7 is an explanatory diagram of an output operation of an OFDM transmitting apparatus according to a third embodiment of the present invention;

FIG. 8 is a block diagram showing a configuration of an OFDM transmitting apparatus according to a fourth embodiment of the present invention;

FIG. 9 is a block diagram illustrating a configuration of an OFDM transmitting apparatus according to a fifth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Operation processing means 2 Buffer control means 3 Buffer (1) 4 Buffer (2) 5 Buffer 6 Buffer control means 7 Synchronous symbol memory 8 Buffer

Claims (5)

[Claims] 1. An arithmetic processing means for arithmetically processing input serial data to generate modulated data to be transmitted, and performing switching output having a bit width larger than a full-scale bit number of the modulated data. In an OFDM transmission apparatus comprising at least one buffer and buffer control means for controlling a switching operation of the buffer, the arithmetic processing means includes means for writing a flag for switching the buffer together with the modulated data to the buffer. The OFDM transmission apparatus, wherein the buffer control means includes means for switching the output buffer to another according to the flag output by the buffer being output. 2. An arithmetic processing means for arithmetically processing input serial data to generate modulation data to be transmitted, and having a bit width larger than the full-scale bit number of the modulation data and having an address from both input and output. One buffer that can be set to perform writing and output simultaneously;
In an OFDM transmission device comprising: a buffer control unit that controls an output address of the buffer, the buffer has two or more areas inside, and the arithmetic processing unit includes:
Means for writing a flag for switching an output area together with the modulation data to each area of the buffer, wherein the buffer control means switches from the area being output to another area according to the flag output by the buffer. An OFDM transmitting apparatus, comprising: means for outputting a signal. 3. The arithmetic processing means includes means for writing a flag for resetting an output address of the buffer to the buffer, wherein the buffer control means sets an output start address of the buffer; Means for causing the buffer to output from the output start address, means for resetting the output address in accordance with the flag output by the buffer, and means for generating modulated data for a guard interval period. The OFDM transmitting apparatus according to claim 1 or 2, wherein 4. A memory in which modulation data of the same synchronization symbol for each frame is stored in advance, and said arithmetic processing means has means for sequentially writing modulation data of a significant symbol that changes according to input data to said buffer. ,
3. The OFDM transmission apparatus according to claim 1, further comprising a unit that outputs modulated data from the memory during a synchronization symbol period and outputs modulated data from the buffer during other periods. . 5. An OFDM system comprising: an arithmetic processing means for arithmetically processing input serial data to generate modulated data to be transmitted; and a buffer having a bit width larger than the full-scale number of bits of the modulated data. In the transmission device, the arithmetic processing unit includes a unit that writes a flag indicating a synchronization point together with the modulation data to the buffer, and includes a unit that transmits a flag output from the buffer as a synchronization signal. OFDM transmission device.