JPH11297996A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high breakdown strength semiconductor device having an offset drain, wherein formation of an accumulating layer on a drift region plane is prevented and a junction breakdown voltage (BVds ) is improved, and to provide a method for manufacturing such semiconductor device. SOLUTION: This semiconductor device is provided with an (n) type epitaxial layer 4 on a (p) type semiconductor substrate 1, a (p) well 25 whereupon an n<+> type source region 31 is formed, an n<+> type drain region 32 formed through the n<+> type drain region 31 and an element isolating layer 13, and a gate electrode 16 composed of polysilicon formed on the upper layer of the n<+> type source region 31, (p) well 25 and the element isolating layer 13 through an insulating film. In this case, a polysilicon layer (gate electrode) on the upper layer of an (n) type drift region 14 is selectively oxidized to be a polysilicon oxide film 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device having an offset drain and a method of manufacturing the same, and more particularly to a high breakdown voltage MOS device in which formation of a carrier accumulation layer on a drift region surface is prevented and a junction breakdown voltage is improved.
The present invention relates to a transistor and a method for manufacturing the transistor.

[0002]

2. Description of the Related Art In recent years, with the spread of personal computers and the enlargement of home televisions, the display market has been rapidly expanding. In the current display market, cathode ray tubes (CRTs) having high definition, high brightness, wide viewing angle, and high contrast are the most common.
However, increasing the size of the cathode ray tube increases the occupied area and weight. Therefore, as next-generation displays, such as liquid crystal displays and plasma displays,
Expectations are growing for flat panel displays (FPDs) that can be made thinner and lighter.

In these flat panel displays, several hundred volts for controlling plasma are used in the process of manufacturing an electric field driving substrate for controlling the electric field intensity to the pixel cells.
It is necessary to form an electric field drive circuit having a high withstand voltage on a semiconductor substrate. FIGS. 18A and 18B are sectional views showing the basic structure of a conventional high breakdown voltage MOS transistor.
The high breakdown voltage MOS transistor as shown in FIG.
(LOCOS offset drain) type MOS transistor.

[0004] In the LOD type MOS transistor,
High junction breakdown voltage (BV _ds ; Breakdown Vo)
l ⁺ ) to secure the n ⁺ type drain region 49.
Are formed separated from the p-well 43 by a LOCOS oxide film 45. On the other hand, n ⁺ type source region 48 and p
^{Since the +} -type p-well extraction region 50 is short-circuited by the source electrode 51, when a reverse bias is applied between the source and the drain, the p-well 43 and the n-type drift region 46
The depletion layer extends from the junction of n to the n-type drift region 46. By using the extension of the depletion layer to the n-type drift region 46 to suppress electric field concentration (electric field relaxation), the withstand voltage of the transistor is ensured.

Further, in the transistor shown in FIG. 18, RESURF (Reduced SURface F)
A high breakdown voltage is also achieved by an electric field relaxation utilizing the extension of a depletion layer in the surface direction at the junction between the p-type substrate 41 and the n-type epitaxial layer 42. The RESURF structure can be easily combined with the pn junction isolation, and the breakdown voltage can be controlled by adjusting the length of the drift region. Therefore, the RESURF structure is advantageous as a structure of a high breakdown voltage transistor.

[0006]

However, in the above-mentioned conventional high breakdown voltage semiconductor device, BV _ds is usually a breakdown voltage when the transistor is in an off state (gate potential V _g = 0 V), and a high voltage is actually applied to the gate. It is known that the withstand voltage when applied is lower than that. When a positive high voltage is applied to the gate, a channel is formed on the surface of the p-well 43 immediately below the gate oxide film 44. At the same time, LO
Electrons are concentrated on the surface of the n-type drift region 46 immediately below the LOCOS oxide film 45 by the gate polysilicon electrode 47 having a shape extending to the COS oxide film 45. In the state where electrons are accumulated in the n-type drift region 46, the junction concentration between the p-well 43 and the n-type drift region 46 is apparently increased, and it is considered that the breakdown voltage of the transistor is thereby reduced.

Further, as shown in FIG. 18B, in order to reduce the resistance when the transistor is turned on,
There is also a high breakdown voltage MOS transistor in which the resistance of the n-type drift region is reduced by forming an n-type impurity diffusion layer in the n-type drift region. In this case, the decrease in breakdown voltage when a high voltage is applied to the gate as described above becomes more remarkable.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. Accordingly, the present invention provides a high-breakdown-voltage transistor having a LOCOS offset drain in a drift region surface via a field insulating film (LOCOS) due to wiring. It is an object of the present invention to provide a high breakdown voltage semiconductor device in which the formation of an electron storage layer is suppressed and the junction breakdown voltage (BV _ds ) is improved, and a method of manufacturing the same.

[0009]

In order to achieve the above object, a semiconductor device of the present invention comprises a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate of the first conductivity type. An insulating film formed on the second conductivity type semiconductor layer;
A first conductivity type impurity diffusion layer formed in a surface region of the second conductivity type semiconductor layer; a second conductivity type source region formed in a surface region of the first conductivity type impurity diffusion layer; A second conductivity type drain region formed at a predetermined distance from the first conductivity type impurity diffusion layer in a surface region of the type semiconductor layer; and a second conductivity type source region and a second conductivity type drain region. An element isolation layer made of an insulator formed in a surface region of the second conductivity type semiconductor layer between the second conduction type source region, the first conductivity type impurity diffusion layer and the element isolation layer. In an insulated gate field effect transistor having at least a gate electrode made of polysilicon formed through an insulating film, at least an upper portion of the element isolation layer of the gate electrode is selectively oxidized. And it features.

In the semiconductor device according to the present invention, preferably, a second conductive type impurity having a higher concentration than the second conductive type semiconductor layer is diffused below the element isolation layer of the second conductive type semiconductor layer. It has a second conductivity type drift region. The semiconductor device of the present invention is preferably characterized in that the first conductivity type is a p-type. More preferably, the second conductivity type semiconductor layer is an epitaxial layer. Preferably, the insulating film is a silicon oxide film. The semiconductor device of the present invention
Preferably, the impurity diffused in the first conductivity type impurity diffusion layer is boron, and the impurity diffused in the second conductivity type drift region is phosphorus.

According to the semiconductor device of the present invention, the gate polysilicon layer is formed so as to cover the upper part of the field oxide film (LOCOS), and the gate polysilicon layer on the drift region of the offset drain is selectively oxidized. I have. Therefore, an electron accumulation layer is not formed on the surface of the drift region due to the influence of the wiring via the field insulating film,
The apparent junction concentration between the p-well and the n-type drift region does not increase. Therefore, a decrease in the withstand voltage of the transistor when the transistor is on (when a high voltage is applied to the gate) can be suppressed.

According to another aspect of the present invention, there is provided a semiconductor device according to the present invention, wherein a first conductivity type semiconductor substrate and a first conductivity type impurity formed in a surface region of the first conductivity type semiconductor substrate are diffused. A first conductive type buried layer, a second conductive type semiconductor layer formed on the first conductive type semiconductor substrate, an insulating film formed on the second conductive type semiconductor layer, and a second conductive type buried layer. A first conductivity type impurity diffusion layer formed on the first conductivity type buried layer of the semiconductor layer, the first conductivity type impurity being diffused at a higher concentration than the first conductivity type buried layer; A second conductivity type source region formed in a surface region of the first conductivity type impurity diffusion layer; and a second conductivity type source region formed in the surface region of the second conductivity type semiconductor layer at a predetermined distance from the first conductivity type impurity diffusion layer. A conductive type drain region; the second conductive type source region; Wherein an element isolation layer formed of an insulating material formed on a surface region of the second conductivity type semiconductor layer, the second conductivity type source region between the conductivity type drain region, said first
In an insulated gate field effect transistor having at least a conductive impurity diffusion layer and a gate electrode made of polysilicon formed on the element isolation layer with the insulating film interposed therebetween, the gate electrode is at least the element isolation layer. The upper part of the layer is selectively oxidized. The semiconductor device of the present invention is preferably characterized in that the first conductivity type is a p-type, and preferably the first conductivity type is a p-type.
The impurity diffused in the conductive buried layer is boron.

As a result, the junction breakdown voltage (BV _ds ) of the LOD type field effect transistor can be improved. The gate electrode structure of the semiconductor device according to the present invention is a conventional L
D (Lateral double-diffuse)
d) It can be easily combined with the structure. Therefore, when the present invention is applied to the LOD type LDMOS transistor, a high breakdown voltage semiconductor device can be obtained.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a second conductive type semiconductor layer on a first conductive type semiconductor substrate, and a step of forming a second conductive type semiconductor layer on the second conductive type semiconductor layer. Forming an insulating film, forming a first nitride film on the insulating film, performing predetermined patterning, oxidizing the second conductivity type semiconductor layer using the first nitride film as a mask, and forming an element isolation layer. Forming a polysilicon layer, an oxide film, and a second nitride film on the entire surface in order, and removing the oxide film and the second nitride film while leaving only a gate electrode formation region; Oxidizing the polysilicon layer using the film as a mask to form a polysilicon oxide film; performing a predetermined patterning on the polysilicon oxide film to form an unoxidized portion of the polysilicon layer; The port at the top Leaving the silicon oxide film in continuous shape, forming a gate polysilicon electrode, in the surface region of the second conductivity type semiconductor layer, to diffuse the first conductivity type impurity using the gate polysilicon electrode as a mask,
Forming a first conductivity type impurity diffusion layer, forming a second conductivity type source region in a surface region of the first conductivity type impurity diffusion layer, and forming a second conductivity type source region in the surface region of the second conductivity type semiconductor layer.
Forming a second conductivity type drain region through the first conductivity type impurity diffusion layer, the gate polysilicon electrode, and the element isolation layer; and forming an interlayer insulating film over the entire surface, and forming the source of the interlayer insulating film. Forming an opening in the region and the drain region; and depositing a wiring metal layer on the entire surface including the opening and performing predetermined patterning to form an insulated gate field effect transistor. .

The method of manufacturing a semiconductor device according to the present invention is preferably arranged such that the second conductive type semiconductor layer is provided below the element isolation layer.
Forming a second conductivity type drift region by diffusing a second conductivity type impurity at a higher concentration than the second conductivity type semiconductor layer. The method of manufacturing a semiconductor device according to the present invention is preferably characterized in that the first conductivity type is a p-type. Further, the method for manufacturing a semiconductor device according to the present invention includes:
Preferably, the second conductivity type semiconductor layer is formed by epitaxial growth. In the method of manufacturing a semiconductor device according to the present invention, preferably, the insulating film is a silicon oxide film. In the method of manufacturing a semiconductor device according to the present invention, preferably, the impurity diffused into the first conductivity type impurity diffusion layer is boron.
Preferably, the impurity diffused into the second conductivity type drift region is phosphorus.

Preferably, in the method of manufacturing a semiconductor device according to the present invention, the first conductive type impurity diffusion layer in the surface region of the first conductive type semiconductor substrate is provided before the step of forming the second conductive type semiconductor layer. A lower concentration of the first conductivity type impurity than the first conductivity type impurity diffusion layer,
A step of forming a first conductivity type buried layer. Preferably, the first conductivity type is p-type, and more preferably, the impurity diffused into the first conductivity type buried layer is boron.

According to the method of manufacturing a semiconductor device of the present invention, since the gate polysilicon layer is selectively oxidized, the formation of the electron accumulation layer on the surface of the drift region due to the influence of the wiring via the field insulating film is prevented. Is suppressed. Therefore, even when the transistor is on (when a high voltage is applied to the gate), a high breakdown voltage is ensured for the transistor.

According to the method of manufacturing a semiconductor device of the present invention,
The gate polysilicon layer is replaced with a field oxide film (LOCO
S) A gate electrode is formed by covering the upper portion and selectively oxidizing the polysilicon layer on the drift region using the nitride film layer on the polysilicon layer as a mask (antioxidant film). Therefore, it is possible to control the gate length with high accuracy without being restricted by the mask alignment accuracy for the LOCOS and the polysilicon layer. This makes it possible to easily control the junction breakdown voltage depending on the gate length.

[0019]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of the semiconductor device of the present embodiment. The semiconductor device of FIG. 1 has a LOD (LOCOS
ffset drain) LD (Lateral d)
a p-type buried layer 3 is formed on the p-type substrate 1, an n-type epitaxial layer 4 is formed on the substrate surface of the p-type substrate 1, and the p-type buried layer 3 is formed on the n-type epitaxial layer 4. Well 25
An n ⁺ -type source region 31 is formed therein, and an n ⁺ -type drain region 32 is formed in the n-type epitaxial layer 4. p
The well 25 and the n ⁺ type drain region 32 are
, The p well 25 and the n ⁺ type drain region 3
An n-type drift region 14 is formed immediately below the element isolation layer 13 between the two.

The polysilicon layer 16 serving as a gate electrode is formed in a shape protruding above the element isolation layer 13, and the polysilicon layer 16 above the n-type drift region 14 is oxidized to form a polysilicon oxide film 20. n ⁺ type source region 3
1 and n ⁺ type drain region 32, an interlayer insulating film 3
4 is provided with a contact hole, and a source electrode 36 and a drain electrode 37 are formed respectively.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. First, 9
A film thickness of 60 by steam oxidation at about 100 to 1000 ° C.
An oxide film (SiO ₂ film) 2 having a thickness of about 100 nm is formed. Next, a photoresist having an opening in the formation region of the p-type buried layer 3 is formed on the SiO ₂ film 2 by a known photolithography technique, ion implantation is performed using the photoresist as a mask, and boron (B) is doped with 1 × 10 ¹² to 1 × 10 ¹³ /
About ² cm ^{2 is} introduced. After removing the photoresist, 11
When the heat treatment at about 00 to 1200 ° C. is performed to form the p-type buried layer 3, a structure as shown in FIG. 2 is obtained.

Next, the SiO ₂ film 2 on the p-type substrate 1 is removed using a hydrofluoric acid (HF) chemical. Subsequently, an n-type epitaxial layer 4 having a resistivity of about 5 to 10 Ω · cm is formed on the p-type substrate 1. The thickness of the n-type epitaxial layer 4 is
In general, 1 per 100 V according to the required breakdown voltage
It is determined using about 0 μm as a guide.

Next, the surface of the n-type epitaxial layer 4 is
A film thickness of 60 by steam oxidation at about 100 to 1000 ° C.
An SiO ₂ film 5 of about 100 nm is formed. Further, a photoresist 6 having an opening in an element isolation diffusion layer forming region (element isolation diffusion layer impurity implantation region 7) is formed by a known photolithography technique, and ion implantation is performed using the photoresist 6 as a mask to form boron (B). ) Or Al
Of about 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ² . This results in a structure as shown in FIG. The region where the impurities are diffused becomes an element isolation diffusion layer 9 for pn junction isolation by performing annealing in a subsequent step.

After removing the photoresist 6, an Si ₃ N ₄ film 8 having a thickness of about 80 to 100 nm is formed on the entire surface by a low pressure CVD method. Subsequently, annealing is performed by performing a heat treatment at about 1100 to 1200 ° C. to form the element isolation diffusion layer 9. Thereby, a structure as shown in FIG. 4 is obtained.

Next, in order to process a region, also called an active region, in which a source, a drain, a gate and the like are formed, a photoresist 10 having an opening in the active region is formed by a known photolithography technique. By a known etching method using a photoresist as a mask, for example, reactive ion etching (RIE),
Only the Si ₃ N ₄ film 8 on the active region is left, and the Si ₃ N
_{4 The} film 8 is removed. This results in a structure as shown in FIG.

After the photoresist 10 is removed, Si ₃ N ₄
Using the Si ₃ N ₄ film 8 as a mask, phosphorus (P) is ion-implanted into a region between the films 8, that is, a portion where the n-type drift region 14 is formed, at a concentration of about 1 × 10 ¹² to 1 × 10 ¹³ / cm ² I do. As shown in FIG. 6, a resist 11 is formed on portions where the Si ₃ N ₄ film 8 has been removed but phosphorus ions are not implanted, to avoid phosphorus ion implantation. In this ion implantation, phosphorus is implanted in a self-aligned manner by the Si ₃ N ₄ film 8, so that the ion implantation position can be controlled with high accuracy without being affected by misalignment of the mask in photolithography. As a result, as shown in FIG. 6, the n-type drift region
2 are formed.

950 to 10 after removal of the photoresist 11
Steam oxidation at about 00 ° C. is performed to form an n-type drift region 1
4 and a LOCOS 13 formed of an oxide film having a thickness of about 500 to 700 nm. As a result, a structure as shown in FIG. 7 is obtained. The n-type drift region 14 is provided for the purpose of reducing the on-resistance of the drift region immediately below the LOCOS of the offset drain. Subsequently, the Si ₃ N ₄ film 8 is removed by hot phosphoric acid, and the SiO ₂ film 5 on the surface of the n-type epitaxial layer 4 is removed by using a hydrofluoric acid (HF) chemical. As a result, a structure as shown in FIG. 8 is obtained.

Next, steam oxidation is performed at 950 to 1000 ° C. to form a gate oxide film 1 on the surface of the n-type epitaxial layer 4.
5 is formed. Subsequently, the thickness is 400 nm by the CVD method.
An approximately n ⁺ -type polysilicon layer 16 is formed. further,
An SiO ₂ film 17 having a thickness of about 50 nm and a Si ₃ N ₄ film 18 having a thickness of about 100 nm are sequentially laminated on the entire surface by CVD.

Subsequently, a photoresist 19 is formed in a gate formation region by a known photolithography technique.
Using the photoresist 19 as a mask, the SiO ₂ film 17 and Si ₃ N are formed by a known etching method, for example, RIE.
_When the etching of the ₄ film 18 is performed, the SiO ₂ film 17 and the Si ₃ N ₄ film 18 remain only on the gate formation region, and FIG.
The structure is as shown in FIG.

Next, the photoresist 19 is removed and 95
The n ⁺ -type polysilicon layer 16 is oxidized by performing steam oxidation at 0 to 1000 ° C. to form a polysilicon oxide film 20. In this steam oxidation, the Si ₃ N ₄ film 18 serves as an oxidation prevention mask, and selective oxidation is performed.
The n ⁺ -type polysilicon remains only in the gate formation region without being oxidized, and a gate polysilicon electrode is formed. Thereby, a structure as shown in FIG. 10 is obtained.

As described above, the n ⁺ type polysilicon 16 has
Since the polysilicon oxide film 20 is formed by performing selective oxidation using the i ₃ N ₄ film 18 as a mask, the gate electrode length is S
It can be controlled by the width of the i ₃ N ₄ film 18. Therefore, the LOCOS 13 and the n ⁺ -type polysilicon layer 16 are not affected by misalignment of the mask, so that highly accurate processing can be performed.

Next, as shown in FIG. 11, a photoresist 21 having an opening in an active region is formed by a known photolithography technique. When the polysilicon oxide film 20 is etched by a known etching method using the photoresist 21 as a mask, for example, RIE, FIG.
As shown in FIG. 1, the gate polysilicon electrode is formed in a shape extended to the field insulating film (LOCOS) 13 on the n-type drift region 14, and the gate polysilicon on the offset drain is in an oxidized state.

With the gate electrode structure shown in FIG. 11, the formation of an electron accumulation layer on the surface of the n-type drift region 14 via the offset drain field oxide film (LOCOS) 13 is suppressed, and the polysilicon layer is formed. Apparent pn compared to the case where 16 is not oxidized
The junction concentration is reduced, so that a decrease in the withstand voltage of the transistor can be effectively prevented.

Subsequently, the photoresist 21 is removed, and SiO ₂ on the gate polysilicon 16 is removed by hot phosphoric acid.
The film 17 and the Si ₃ N ₄ film 18 are removed. Then 8
Steam oxidation at about 00 to 900 ° C. is performed to form an oxide film (SiO ₂ film) 22 having a thickness of about 10 to 20 nm on the gate polysilicon 16 and on the surface of the n-type epitaxial layer 4. As a result, a structure as shown in FIG. 12 is obtained.

Next, a photoresist 23 having an opening in a p-well formation region by a known photolithography technique.
Is formed, and boron (B) is added to the p-well formation region at 1 × 10
Ion implantation is performed at about ¹³ to 1 × 10 ¹⁴ / cm ² . As a result, as shown in FIG.
Is formed. In this ion implantation, the p-well is L
It is formed in a self-aligned manner using the OCOS 13 and the n ⁺ type polysilicon layer 16 as a mask. Accordingly, high-precision processing can be performed without being affected by mask misalignment that occurs in a photolithography step of performing mask patterning for ion implantation.

After the removal of the photoresist 23, 950-1
A heat treatment at about 000 ° C. is performed to diffuse the impurities in the p-well impurity implantation region 24 to form a p-well 25. Further, a photoresist 26 having an opening in the n ⁺ type source and n ⁺ type drain formation regions is formed by a known photolithography technique, and 1 × 10 ¹⁵ to 1 × 10 ⁵ is formed in the n ⁺ type source and n ⁺ type drain formation regions. Arsenic of about ¹⁶ / cm ² (A
s) is ion-implanted. Thus, an n ⁺ -type source impurity implantation region 27 and an n ⁺ -type drain impurity implantation region 28 are formed as shown in FIG.

In this ion implantation, the n ⁺ type source region 31 is formed by using the n ⁺ type polysilicon layer 16 as a mask.
^{The +} type drain region 32 is formed in a self-aligned manner using the LOCOS 13 as a mask. Therefore, high-precision processing can be performed without being affected by mask misalignment that occurs when performing mask patterning for ion implantation by a photolithography process.

Further, after the photoresist 26 is removed, a photoresist 29 is formed by a known photolithography technique as in the case of the n ⁺ -type source impurity implantation region 27 and the n ⁺ -type drain impurity implantation region 28 described above. From the 1 × 10 ¹⁵ to 1 × 10 ¹⁶
/ Cm ² of boron (B) is ion-implanted. Thus, ap ⁺ -type source impurity implantation region 30 is formed as shown in FIG.

Subsequently, after removing the photoresist 29, C
An interlayer insulating film (SiO.
₂ ) is deposited on the entire surface. Then 850-95
A heat treatment of about 0 ° C., the n ⁺ -type source impurity implanted regions 27 and n ⁺ -type drain impurity implantation arsenic in region 28, and p ⁺ type source impurity implantation to diffuse the boron in the region 30, n ⁺ -type source region 31, n ⁺ type drain region 32, p ⁺ type source region (p well take-out region) 3
Form 3 As a result, a structure as shown in FIG. 16 is obtained.

A photoresist having openings in the source, gate, and drain electrode formation regions of the interlayer insulating film (SiO ₂ film) 34 is formed by a known photolithography technique, and a known etching method using the photoresist as a mask, for example, The interlayer insulating film 34 is etched by RIE. After removing the photoresist, Al or Ti / TiON is formed in each electrode forming opening formed in the interlayer insulating film 34.
A wiring metal layer 35 including a barrier metal layer such as / Ti is deposited. As a result, a structure as shown in FIG. 17 is obtained.

Further, by patterning the wiring metal layer 35 by a known photolithography technique and RIE, the source electrode 36 and the drain electrode 3 as shown in FIG.
7 is formed. Thereby, the semiconductor device of the present embodiment having the structure as shown in FIG. 1 is obtained.

According to the method of manufacturing a semiconductor device of the embodiment of the present invention, in a high breakdown voltage semiconductor device having an offset drain, formation of a carrier (electron) accumulation layer on a drift region surface is prevented, and a junction breakdown voltage is reduced. It is possible to manufacture an improved high voltage MOS transistor. The semiconductor device and the method of manufacturing the same according to the present invention are not limited to the above embodiments. For example, a first conductivity type buried layer in which a first conductivity type impurity is diffused, that is, a p-type buried layer 3 formed on the p-type substrate 1 in the present embodiment is formed in a surface region of the first conductivity type semiconductor substrate. Instead, the polysilicon gate electrode of the semiconductor device of the present invention can be formed. In addition, various changes can be made without departing from the gist of the present invention.

[0043]

According to the semiconductor device of the present invention, the gate polysilicon layer is formed so as to cover the upper part of the field oxide film (LOCOS), and the gate polysilicon layer on the drift region is selectively oxidized. Therefore, the formation of the electron accumulation layer on the surface of the drift region due to the influence of the wiring via the field insulating film is suppressed. Therefore, even when the transistor is on (when a high voltage is applied to the gate), a high breakdown voltage is ensured for the transistor.

According to the method of manufacturing a semiconductor device of the present invention,
Since the gate electrode is formed by selectively oxidizing the polysilicon layer using the nitride film layer formed on the polysilicon layer as an antioxidant film, there is no limitation on the mask alignment accuracy for the LOCOS and the polysilicon layer. Therefore, it is possible to control the gate length with high accuracy, and it is also easy to control the junction breakdown voltage depending on the gate length.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 11 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 12 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 13 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 14 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 15 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 16 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 17 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIGS. 18A and 18B are cross-sectional views of a conventional semiconductor device.

[Explanation of symbols]

1, 41: p-type semiconductor substrate, ₂ , 5, 17, 22: oxide film (SiO ₂ film), 3: p-type buried layer, 4, 42: n
Type epitaxial layer, 6, 10, 11, 19, 21, 2
3, 26, 29: photoresist, 7: element isolation diffusion layer impurity implantation region, 8, 18: nitride film (Si ₃ N ₄ film),
9 ... element isolation diffusion layer, 12 ... n-type drift region impurity implantation region, 13, 45 ... element isolation layer (LOCOS), 1
4, 46: n-type drift region, 15, 44: gate oxide film (SiO ₂ film), 16: polysilicon layer, 20: polysilicon oxide film, 24: p-well impurity implantation region, 2
5,43 ... p-well, 27 ... n ⁺ -type source impurity implanted region, 28 ... n ⁺ -type drain impurity implantation region, 30 ... p ⁺
.. N ⁺ -type source regions, 32, 49... N ⁺ -type drain regions, 33, 50.
⁺ Type source region (p-well extraction region), 34: interlayer insulating film, 35: metal wiring layer, 36, 51: source electrode,
37, 52: a drain electrode; 46 ', an n-type drift region impurity diffusion layer; 47, a gate polysilicon electrode.

Claims (30)

[Claims] A first conductive type semiconductor substrate; a second conductive type semiconductor layer formed on the first conductive type semiconductor substrate; an insulating film formed on the second conductive type semiconductor layer; A first conductivity type impurity diffusion layer formed in a surface region of the second conductivity type semiconductor layer; and a second conductivity type impurity diffusion layer formed in a surface region of the first conductivity type impurity diffusion layer.
A conductivity type source region; a second conductivity type drain region formed in the surface region of the second conductivity type semiconductor layer at a predetermined distance from the first conductivity type impurity diffusion layer; and the second conductivity type source region. An element isolation layer made of an insulator formed in a surface region of the second conductivity type semiconductor layer between the second conductivity type drain region and the second conductivity type drain region; An insulated gate field effect transistor having at least a diffusion layer and a gate electrode made of polysilicon formed on the element isolation layer with the insulating film interposed therebetween, wherein the gate electrode is at least above the element isolation layer. Is a selectively oxidized semiconductor device. 2. The semiconductor device according to claim 2, further comprising a second conductivity type drift region in which a second conductivity type impurity having a higher concentration than the second conductivity type semiconductor is diffused below the device isolation layer of the second conductivity type semiconductor layer. Item 2. The semiconductor device according to item 1. 3. The semiconductor device according to claim 2, wherein said first conductivity type is a p-type. 4. The semiconductor device according to claim 1, wherein said second conductivity type semiconductor layer is an epitaxial layer. 5. The semiconductor device according to claim 1, wherein said insulating film is a silicon oxide film. 6. The semiconductor device according to claim 3, wherein the impurity diffused in the first conductivity type impurity diffusion layer is boron. 7. The semiconductor device according to claim 3, wherein said impurity diffused into said second conductivity type drift region is phosphorus. 8. A first conductivity type semiconductor substrate, and a first conductivity type semiconductor substrate formed in a surface region of the first conductivity type semiconductor substrate.
A first conductivity type buried layer in which a conductivity type impurity is diffused, a second conductivity type semiconductor layer formed on the first conductivity type semiconductor substrate, and an insulating film formed on the second conductivity type semiconductor layer. A first-conductivity-type impurity diffusion layer formed on the first-conductivity-type buried layer of the second-conductivity-type semiconductor layer, the first-conductivity-type impurity having a higher concentration than the first-conductivity-type buried layer is diffused; A second conductivity type source region formed in a surface region of the first conductivity type impurity diffusion layer; and a predetermined distance from the first conductivity type impurity diffusion layer in a surface region of the second conductivity type semiconductor layer. And a second conductive type drain region formed between the second conductive type drain region and the second conductive type semiconductor layer and between the second conductive type source region and the second conductive type drain region. An element isolation layer; the second conductivity type source region; An insulated-gate field-effect transistor having at least a 1-conductivity-type impurity diffusion layer and a gate electrode made of polysilicon formed on the element isolation layer with the insulating film interposed therebetween, wherein the gate electrode comprises at least the element A semiconductor device in which an upper portion of a separation layer is selectively oxidized. 9. A second conductivity type drift region in which a second conductivity type impurity having a higher concentration than the second conductivity type impurity is diffused below the device isolation layer of the second conductivity type semiconductor layer. Item 9. The semiconductor device according to item 8. 10. The first conductivity type is a p-type.
13. The semiconductor device according to claim 1. 11. The semiconductor device according to claim 8, wherein said second conductivity type semiconductor layer is an epitaxial layer. 12. The semiconductor device according to claim 8, wherein said insulating film is a silicon oxide film. 13. The semiconductor device according to claim 10, wherein said impurity diffused in said first conductivity type buried layer is boron. 14. The semiconductor device according to claim 10, wherein said impurity diffused in said first conductivity type impurity diffusion layer is boron. 15. The semiconductor device according to claim 10, wherein said impurity diffused into said second conductivity type drift region is phosphorus. 16. A step of forming a second conductive type semiconductor layer on a first conductive type semiconductor substrate; a step of forming an insulating film on the second conductive type semiconductor layer; Forming a first nitride film, performing predetermined patterning, oxidizing the second conductivity type semiconductor layer using the first nitride film as a mask, and forming an element isolation layer; and forming a polysilicon layer, an oxide film, Depositing a second nitride film in order and removing the oxide film and the second nitride film while leaving only a gate electrode formation region; and oxidizing the polysilicon layer using the second nitride film as a mask. Forming a film, performing predetermined patterning on the polysilicon oxide film, leaving a non-oxidized portion of the polysilicon layer and the polysilicon oxide film on the element isolation layer in a continuous shape, Gate poly Forming a first conductive type impurity in a surface region of the second conductive type semiconductor layer using the gate polysilicon electrode as a mask, and forming a first conductive type impurity diffusion layer; Forming a second conductivity type source region in the surface region of the first conductivity type impurity diffusion layer; and forming the first conductivity type impurity diffusion layer and the gate polysilicon electrode in the surface region of the second conductivity type semiconductor layer. Forming a second conductivity type drain region through the element isolation layer; forming an interlayer insulating film over the entire surface; and providing openings in the source region and the drain region of the interlayer insulating film; Depositing a wiring metal layer on the entire surface including the portion and performing predetermined patterning to form an insulated gate field effect transistor. 17. The semiconductor device according to claim 17, wherein the second conductive type semiconductor layer has a second concentration lower than that of the second conductive type semiconductor layer below the element isolation layer.
17. The method of manufacturing a semiconductor device according to claim 16, further comprising a step of forming a second conductivity type drift region by diffusing a conductivity type impurity. 18. The semiconductor device according to claim 1, wherein said first conductivity type is a p-type.
8. The method for manufacturing a semiconductor device according to item 7. 19. The method according to claim 16, wherein the second conductivity type semiconductor layer is formed by epitaxial growth. 20. The method according to claim 16, wherein said insulating film is a silicon oxide film. 21. The method according to claim 18, wherein the impurity diffused into the first conductivity type impurity diffusion layer is boron. 22. The method according to claim 18, wherein the impurity diffused into the second conductivity type drift region is phosphorus. 23. Prior to the step of forming the second conductivity type semiconductor layer, the first conductivity type semiconductor substrate is provided with the first conductivity type impurity diffusion layer below the region where the first conductivity type impurity diffusion layer is formed.
17. The method of manufacturing a semiconductor device according to claim 16, further comprising a step of diffusing a first conductivity type impurity at a lower concentration than the conductivity type impurity diffusion layer to form a first conductivity type buried layer. 24. A semiconductor device, comprising: a second conductive type semiconductor layer having a lower concentration than a second conductive type semiconductor layer;
24. The method of manufacturing a semiconductor device according to claim 23, further comprising a step of forming a second conductivity type drift region by diffusing a conductivity type impurity. 25. The semiconductor device according to claim 2, wherein the first conductivity type is a p-type.
5. The method for manufacturing a semiconductor device according to item 4. 26. The method according to claim 23, wherein the second conductivity type semiconductor layer is formed by epitaxial growth. 27. The method according to claim 23, wherein said insulating film is a silicon oxide film. 28. The method according to claim 25, wherein the impurity diffused into the first conductivity type buried layer is boron. 29. The method according to claim 25, wherein the impurity diffused into the first conductivity type impurity diffusion layer is boron. 30. The method according to claim 25, wherein the impurity diffused into the second conductivity type drift region is phosphorus.