JPH11289068A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the generation of leak currents between a capacitive insulating film and an upper electrode, and between the capacitive insulating film and a lower electrode at the time of using ferroelectric materials for the capacitive insulating film, and to obtain a large storage capacity while suppressing the deterioration of characteristics such as the leak currents. SOLUTION: In this method for manufacturing a semiconductor storage device, a capacitive insulating film 33 of the memory capacitor of a DRAM is formed in a three-layer structure in which the both upper and lower surface layers are Ta2 O5 films 27 and 29 deoxidized by heat treatment in an oxygen plasma atmosphere, and the inner layer is a Ta2 O5 film 28 in an amorphous state. That is, an amorphous Ta2 O5 film 26 is formed, and almost the whole part is anneal processed in an oxygen plasma atmosphere so that the Ta2 O5 film 27 can be formed, and only the surface layer of the successively formed amorphous Ta2 O5 film 28 is processed in the same way so that the Ta2 O5 film 29 can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and is particularly suitable for application to a semiconductor memory device having a memory capacitor such as a DRAM.

[0002]

2. Description of the Related Art In recent years, miniaturization and high integration of semiconductor devices have been progressing. As a result, the area occupied by the memory capacitor in the DRAM has been reduced, and it has become difficult to secure a sufficient storage capacity. Ensuring the storage capacity is one of the important issues to be overcome. Thus, several solutions have been proposed. For example, JP-A-62-1
Japanese Patent Application Laid-Open No. 20072 discloses that an insulating material having a higher relative dielectric constant than silicon nitride, for example, Ta ₂ O ₅ is used as a material of a capacitance insulating film of a memory capacitor, and a large storage capacity can be obtained even with a small occupation area. Techniques are disclosed. It is known that the Ta ₂ O ₅ film has a higher relative dielectric constant in an amorphous state than in a crystallized state, and is preferably used in an amorphous state.

[0003]

However, in the case of Japanese Patent Application Laid-Open No. Sho 62-120072, an amorphous Ta ₂
The O ₅ film has a disadvantage of a large leak current, and when this film is formed by a CVD method, Ta gas is used as a source gas.
There is a serious problem that the use of (OC ₂ H ₅ ) ₅ causes carbon to be mixed into the Ta ₂ O ₅ film, which further increases the leak current.

[0004] As measures to improve the leakage current, for example, JP-A-7-14986, heat-treated in an oxygen plasma atmosphere in the Ta ₂ O ₅ film of the formed amorphous state the Ta ₂ O ₅ film A technique for crystallizing is disclosed. According to this method, the oxygen is supplied to the Ta ₂ O ₅ film in the carbon in the Ta ₂ O ₅ film is removed, it is possible to suppress generation of leakage current. However, in this case,
Since the Ta ₂ O ₅ film is completely crystallized and the dielectric constant is not so high, a large storage capacity cannot be implemented.

Therefore, it is conceivable to decrystallize only by crystallizing only the surface of the Ta ₂ O ₅ film. In this case, however, the leakage between the Ta ₂ O ₅ film, that is, the capacitance insulating film and the upper electrode is considered. Although the current can be suppressed, the leak current between the capacitor insulating film and the lower electrode cannot be suppressed.

SUMMARY OF THE INVENTION It is an object of the present invention to improve not only the occurrence of a leakage current between a capacitor insulating film and an upper electrode but also the use of a ferroelectric material for the capacitor insulating film, as well as to improve the capacity between a capacitor insulating film and a lower electrode. Reliable semiconductor memory device capable of obtaining a large storage capacity while suppressing the characteristic degradation typified by the leak current even if the further miniaturization of the semiconductor element progresses by improving the generation of the leak current of the semiconductor device. And a method for producing the same.

[0007]

According to the present invention, there is provided a semiconductor memory device having a capacitor portion in which a lower electrode and an upper electrode are capacitively coupled to each other via a capacitive insulating film. The insulating film includes an amorphous ferroelectric material, and both upper and lower surface layers are decarbonized.

In one embodiment of the semiconductor memory device of the present invention, an oxidation-resistant protective film is formed between the lower electrode and the dielectric film.

In one embodiment of the semiconductor memory device according to the present invention, the lower electrode contains, as a material, one selected from tungsten, platinum, titanium nitride and ruthenium.

In one embodiment of the semiconductor memory device according to the present invention, the capacitance insulating film contains Ta ₂ O ₅ as a material.

In one embodiment of the semiconductor memory device according to the present invention, the upper electrode includes, as a material, one selected from titanium nitride, tungsten, and polycrystalline silicon.

A method of manufacturing a semiconductor memory device according to the present invention is a method of manufacturing a semiconductor memory device having a capacitor portion in which a lower electrode and an upper electrode face and capacitively oppose each other via a capacitive insulating film. A first step of depositing a first conductive film at least through an interlayer insulating film on the upper layer, processing the first conductive film into an island shape to form a lower electrode, and so as to cover the lower electrode. , Including an amorphous ferroelectric material
A second step of depositing the first dielectric film, a third step of subjecting the first dielectric film to a heat treatment in an oxygen plasma atmosphere, and decarbonizing the first dielectric film, A fourth step of depositing a second dielectric film containing an amorphous ferroelectric material so as to cover the first dielectric film, and performing a heat treatment on the second dielectric film in an oxygen plasma atmosphere. A fifth step of decarbonizing the surface layer of the second dielectric film, forming a second conductive film so as to cover the second dielectric film, and processing the second conductive film. A sixth step of forming the upper electrode by decapping the upper and lower surface layers of the capacitive insulating film as a laminated structure of the first and second dielectric films, respectively. It is composed of

In one embodiment of the method of manufacturing a semiconductor memory device according to the present invention, after the first step and before the second step, an oxidation-resistant protective film is formed so as to cover the lower electrode. Form.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the first dielectric film is formed to be thinner than the second dielectric film.

In one embodiment of the method for manufacturing a semiconductor memory device of the present invention, the first conductive film is made of tungsten,
The material includes one selected from platinum, titanium nitride, and ruthenium.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the capacitance insulating film contains Ta ₂ O ₅ as a material.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the second conductive film contains, as a material, one selected from titanium nitride, tungsten, and polycrystalline silicon.

[0018]

In the present invention, the capacitor insulating film of the capacitor portion contains an amorphous ferroelectric material, and both upper and lower surface layers are decarbonized by, for example, heat treatment in an oxygen plasma atmosphere. In other words, this capacitive insulating film has a substantially three-layer structure of both the decarbonized surface layer in the crystallized state and the inner layer in the amorphous state. In this case, in addition to the amorphous state in which the inner layer contributes to the suppression of generation of a leak current, the decarbonized crystallization state is formed between the capacitor insulating film and the lower electrode and between the capacitor insulating film and the upper electrode. The leakage current is suppressed to a negligible level between the capacitor insulating film and both electrodes without being adversely affected by the presence of carbon or the like.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings.

In this embodiment, a DRAM having a so-called COB (Capacitor Over Bitline) structure in which an access transistor and a memory capacitor are provided as a semiconductor memory device, and the memory capacitor is formed substantially above a bit line. The configuration will be described together with the manufacturing method. 1 to 3 are schematic sectional views showing a method of manufacturing the DRAM of the first embodiment in the order of steps.

First, as shown in FIG.
A field oxide film 13 is formed as a device isolation structure on a silicon semiconductor substrate 11 of a die by a so-called LOCOS method to define a device active region. Instead of the field oxide film 13, a conductive film is buried in the oxide film by a field shield element isolation method, and a portion of the silicon semiconductor substrate immediately below is fixed at a predetermined potential by the conductive film to perform element isolation. Or an STI (Shallow Trench Isolation) structure in which a groove is formed in the element isolation region of the substrate and an oxide film is buried in the groove, and the upper part protrudes from the substrate surface. It may be formed.

Next, a thermal oxide film is formed by performing a heat treatment on the surface of the silicon semiconductor substrate 11 in the element forming region which is separated from each other by the field oxide film 13 and is relatively defined. A polycrystalline silicon film and a silicon oxide film are deposited and formed.

Next, the thermal oxide film, the polycrystalline silicon film, and the silicon oxide film are patterned by photolithography and subsequent dry etching, and the thermal oxide film, the polycrystalline silicon film, and the silicon oxide film are formed into an electrode shape in the element formation region. Leave the gate oxide film 12 and the gate electrode 15
Then, the cap insulating film 16 is patterned. Here, on the field oxide film 13, only the gate electrode 15 and the cap insulating film 16 are formed so as to extend over the field oxide film 13.

Next, after the photoresist used for patterning is removed by ashing, a silicon oxide film is deposited and formed on the entire surface including the gate electrode 15 by CVD.
The entire surface of the silicon oxide film is anisotropically etched to form a sidewall 17 while leaving the silicon oxide film only on the side surfaces of the gate oxide film 12, the gate electrode 15, and the cap insulating film 16.

Next, using the cap insulating film 16 and the side wall 17 as a mask, an impurity is introduced into the surface region of the silicon semiconductor substrate 11 on both sides of the gate electrode 15 by ion implantation to form a pair of impurity diffusion layers 10 serving as a source / drain. To complete the access transistor having the gate electrode 15 and the pair of impurity diffusion layers 10.

Next, a polycrystalline silicon film is formed on the entire surface including the field oxide film 13 by the CVD method, and the polycrystalline silicon film is patterned by photolithography and subsequent dry etching to cover the impurity diffusion layer 10. The extraction electrode 14 is formed while leaving the polycrystalline silicon film in an island shape extending between the adjacent field oxide films 13. The lead electrode 14 functions as a pad for securing a margin for matching with the impurity diffusion layer 10 when forming each of the openings (bit contact holes 19 and storage contact holes 23) described later. Note that the extraction electrode 14 is formed before the impurity diffusion layer 10 is formed, and the impurity in the extraction electrode 14 is diffused into the silicon semiconductor substrate 11 by subjecting the silicon semiconductor substrate 11 to heat treatment. May be formed.

Next, a silicon oxide film is deposited on the entire surface of the silicon semiconductor substrate 11 including the field oxide film 13 by a CVD method, and the surface is flattened by a reflow process to form an interlayer insulating film 18. continue,
A bit contact that exposes a part of the surface of the extraction electrode 14 formed on one of the pair of impurity diffusion layers 10 (usually serving as a drain) by patterning the interlayer insulating film 18 by photolithography and subsequent dry etching. A hole 19 is formed. Subsequently, a conductive protective film 31 such as titanium (Ti) or titanium (Ti) / titanium nitride (TiN) is formed on the interlayer insulating film 18 including the inner wall of the bit contact hole 19. Thereafter, a polycrystalline silicon film is deposited and formed on the protective film 31 including the inside of the bit contact hole 19 by the CVD method, and the polycrystalline silicon film is patterned into a band shape by photolithography and subsequent dry etching to form the extraction electrode 14. Then, the bit line 20 connected to the lower impurity diffusion layer 10 via the protective film 31 is formed. Here, the bit line 20
May be a polycide layer in which a WSi layer is stacked on a polycrystalline silicon film in order to improve the signal processing speed.

Next, a silicon oxide film is deposited by CVD to cover the bit line 20, an interlayer insulating film 22 is formed, and the interlayer insulating films 22, 18 are patterned by photolithography and subsequent dry etching. Then, a storage contact hole 23 (indicated by a broken line in the drawing) is formed to expose a part of the surface of the extraction electrode 14 formed on the other (usually a source) of the pair of impurity diffusion layers 10.

Next, as shown in FIG. 1B, the entire surface of the interlayer insulating film 22 including the inside of the storage contact hole 23 is C
After a polycrystalline silicon film 32 doped with impurities is deposited to a thickness of about 5000 ° by the VD method, as shown in FIG. 1C, the polycrystalline silicon film is formed into an island shape by photolithography and subsequent dry etching. By patterning, a storage node electrode 24 is formed. Note that, instead of the polycrystalline silicon film 32, a tungsten film,
The storage node electrode may be patterned by forming a platinum film, a titanium nitride film, a ruthenium film, or the like.

Next, as shown in FIG. 2A, an oxidation-resistant protective film, here a silicon nitride film 25, is deposited to a thickness of about 20 ° by a CVD method so as to cover the storage node electrode 24. Subsequently, the source gas is made of Ta (OC ₂ H ₅ ) by CVD so as to cover the silicon nitride film 25.
_A first dielectric film, here, an amorphous Ta ₂ O ₅ film 26 is deposited to a film thickness of about 50 ° at a temperature of about 450 ° C. as ₅ .

Next, as shown in FIG. ₂ (b), Ta 2 O
_5. Anneal the film 26 in oxygen plasma. Specifically, the pressure is set to 1.0 T using a predetermined ashing device.
Processing is performed for about 15 minutes in an atmosphere of about orr, an oxygen flow rate of about 200 sccm, an RF output of about 800 W, and a temperature of about 500 ° C. By this annealing treatment, Ta ₂
The carbon is removed from the O ₅ film 26 and crystallized to form a Ta ₂ O ₅ film 27 having a stoichiometric composition. Here, Ta ₂
Since the O ₅ film 26 is formed to have a relatively small thickness, Ta ₂ O
_{The 5} film 27 is obtained by crystallizing almost the entire Ta ₂ O ₅ film 26. At this time, the oxidation of the storage node electrode 24 is prevented by the presence of the silicon nitride film 25 covering the storage node electrode 24.

[0032] Next, as shown in FIG. ₂ (c), Ta 2 O
_{5 The} source gas is made of Ta by CVD so as to cover the film 27.
At a temperature of about 450 ° C. as (OC ₂ H ₅ ) ₅ , a second dielectric film, here, an amorphous Ta ₂ O ₅ film 28 is
Deposition is formed at about 0 °.

Next, as shown in FIG. 3 (a), Ta ₂ O
₅ Anneal the film 28 in oxygen plasma. Specifically, the pressure is set to 1.0 T using a predetermined ashing device.
Processing is performed for about 15 minutes in an atmosphere of about orr, an oxygen flow rate of about 200 sccm, an RF output of about 800 W, and a temperature of about 500 ° C. By this annealing treatment, Ta ₂
Carbon is removed from the surface layer of the O ₅ film 26 and crystallized, and a Ta ₂ O ₅ film 29 having a stoichiometric composition is formed. Where T
The a ₂ O ₅ film 28 is thicker than the Ta ₂ O ₅ film 26 (3
), And both were annealed under substantially the same conditions. Therefore, unlike the case of the Ta ₂ O ₅ film 27, only the surface layer of the Ta ₂ O ₅ film 28 was crystallized in the Ta ₂ O ₅ film 29. It will be. At this time, similarly, the presence of the silicon nitride film 25 covering the storage node electrode 24 prevents the storage node electrode 24 from being oxidized. Where Ta
_{The 2} O ₅ films 27, 28 and 29 constitute the capacitance insulating film 33.

Next, as shown in FIG. 3B, a titanium nitride (TiN) film is deposited and formed by a CVD method so as to cover the storage node electrode 24 with the capacitance insulating film 33 interposed therebetween, and is subjected to predetermined patterning. Cell plate electrode 34
To form In addition, as a material of the cell plate electrode,
Tungsten or polycrystalline silicon may be used instead of TiN. Here, a memory capacitor including the storage node electrode 24 and the cell plate electrode 34 is completed, in which the storage node electrode 24 and the cell plate electrode 34 are opposed to each other via a capacitance insulating film 33 as a dielectric film and capacitively coupled. I do.

Thereafter, although not shown, further formation of an interlayer insulating film, formation of a connection hole and subsequent formation of a wiring layer, formation of a peripheral circuit portion of a memory cell portion (this peripheral circuit portion is a memory cell portion Are often formed sequentially.)
Through various steps such as the above, the DRAM is completed.

As described above, in the present embodiment, the upper and lower surface layers of Ta ₂ O ₅ , which is an amorphous ferroelectric material, are heat-treated in an oxygen plasma atmosphere. Decarbonized by Ta ₂ O ₅
Films 27 and 29 are formed. That is, the capacitance insulating film 33
Are the Ta ₂ O ₅ films 27 and 29, which are both surface layers in the decarbonized crystallized state, and the T, the inner layer in the amorphous state.
The a ₂ O ₅ film 28 has a three-layer structure. In this case, in addition to the fact that the inner layer is in an amorphous state contributing to the suppression of generation of leakage current, decarbonization occurs between the capacitor insulating film 33 and the storage node electrode 24 and between the capacitor insulating film 33 and the cell plate electrode 34. Since the crystallized surface layer exists, the leakage current between the capacitance insulating film 33 and the electrodes 24 and 34 is suppressed to a negligible level without being hindered by the adverse effects of the presence of carbon or the like. Become.

Therefore, according to the present embodiment, when Ta ₂ O ₅ which is a ferroelectric material is used for the capacitor insulating film 33, the generation of the leak current between the capacitor insulating film 33 and the storage node electrode 24 is improved. Not only that, the generation of a leak current between the capacitor insulating film 33 and the cell plate electrode 34 is also improved, and even if the further miniaturization of the DRAM advances, the characteristic deterioration typified by the leak current is suppressed while the DRAM is greatly reduced. It is possible to obtain a storage capacity.

In this embodiment, a DRAM is shown as an example of a semiconductor memory device. However, the present invention is not limited to this. For example, the present invention is applicable not only to EPROM and EEPROM but also to any other semiconductor memory device.

[0039]

According to the present invention, when a ferroelectric material is used for a capacitor insulating film, not only the leakage current between the capacitor insulating film and the upper electrode can be improved, but also the capacitor insulating film and the lower electrode can be used. In addition, it is possible to obtain a large storage capacity while suppressing the characteristic deterioration represented by the leak current even if the further miniaturization of the semiconductor element progresses.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating a method for manufacturing a DRAM according to an embodiment of the present invention.

FIG. 2 is a continuation of FIG. 1 showing D in an embodiment of the present invention;
FIG. 4 is a schematic sectional view illustrating a method for manufacturing a RAM.

FIG. 3 is a continuation of FIG. 2 showing D in the embodiment of the present invention;
FIG. 4 is a schematic sectional view illustrating a method for manufacturing a RAM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Silicon semiconductor substrate 12 Gate oxide film 13 Field oxide film 14 Leader electrode 15 Gate electrode 16 Cap insulating film 17 Side wall 18, 22 Interlayer insulating film 19 Bit contact hole 20 Bit line 23 Storage contact hole 24 Storage node electrode 25 Silicon nitride film 26, 28 amorphous the Ta ₂ O ₅ film 27, 29 the Ta ₂ O ₅ film 31 conductive underlying film 32 of polycrystalline silicon film 33 capacitive insulating film 34 cell plate electrode of the crystalline state

Claims (11)

[Claims] 1. A semiconductor memory device comprising: a capacitor portion in which a lower electrode and an upper electrode are capacitively coupled to each other via a capacitive insulating film, wherein the capacitive insulating film is made of an amorphous ferroelectric material. A semiconductor memory device, wherein both upper and lower surface layers are decarbonized. 2. The semiconductor memory device according to claim 1, wherein an oxidation-resistant protective film is formed between said lower electrode and said dielectric film. 3. The method according to claim 1, wherein the lower electrode comprises tungsten, platinum,
The semiconductor memory device according to claim 1, wherein the semiconductor memory device includes one selected from titanium nitride and ruthenium as a material. 4. The semiconductor memory device according to claim 1, wherein said capacitor insulating film contains Ta ₂ O ₅ as a material. 5. The method according to claim 1, wherein the upper electrode includes one material selected from titanium nitride, tungsten, and polycrystalline silicon as a material.
13. The semiconductor memory device according to item 9. 6. A method of manufacturing a semiconductor memory device comprising a capacitor portion in which a lower electrode and an upper electrode are capacitively coupled to each other via a capacitive insulating film, wherein at least an interlayer insulating film is formed on an upper layer of the semiconductor substrate. First
A first step of forming the lower electrode by depositing a conductive film and forming the lower electrode by processing the first conductive film into an island shape; and forming a lower electrode including an amorphous ferroelectric material so as to cover the lower electrode. A second step of depositing the first dielectric film; a third step of performing a heat treatment on the first dielectric film in an oxygen plasma atmosphere to decarbonize the first dielectric film; A fourth step of depositing a second dielectric film containing an amorphous ferroelectric material so as to cover the first dielectric film, and performing a heat treatment on the second dielectric film in an oxygen plasma atmosphere. Performing a fifth step of decarbonizing the surface layer of the second dielectric film, depositing a second conductive film so as to cover the second dielectric film, and processing the second conductive film. And forming a sixth step of forming the upper electrode, wherein the capacitive insulating film is a laminated structure of the first and second dielectric films. Method of manufacturing a semiconductor memory device characterized by configuring the shape of both surface layers of the lower is decarbonisation respectively. 7. The semiconductor according to claim 6, wherein an oxidation-resistant protective film is formed so as to cover the lower electrode after the first step and before the second step. A method for manufacturing a storage device. 8. The method according to claim 6, wherein the first dielectric film is formed to be thinner than the second dielectric film. 9. The method according to claim 6, wherein the first conductive film contains, as a material, one selected from tungsten, platinum, titanium nitride, and ruthenium. . 10. The capacitor insulating film according to claim 6, wherein the capacitor insulating film contains Ta ₂ O ₅ as a material.
13. The method for manufacturing a semiconductor memory device according to item 13. 11. The semiconductor device according to claim 6, wherein the second conductive film contains, as a material, one selected from titanium nitride, tungsten, and polycrystalline silicon. Manufacturing method of a semiconductor memory device.