JPH11289046A - High-density interconnection structure body with chamber - Google Patents

Abstract

PURPOSE: To accept the overlay sensing property of a number of elements without sacrificing wiring density by arranging a dielectric layer at the upper portion of the active region of a chip. CONSTITUTION: A substrate 12 is provided with a cavity 14 inside, and a semiconductor and other chips 20 are placed inside the cavity 14. The chip 20 has its active region on an upper surface and a plurality of connection pads 24 are arranged along the outer periphery of the upper surface. Then, a first dielectric layer 32 is glued to a flat part on the upper surface of the substrate 12 and the upper surface of the chip 20, and a window 50 of the dielectric layer 32 surrounds the active region of the chip 20. Also, the second dielectric layer 36 is extended to the chip 20 including the cavity 14 and forms a chamber 18. The ceiling of the chamber 18 is separated to an upper portion from the active part of the chip 20, and a gap in the height direction is selected according to the degree of operating characteristics and sensitivity of the chip 20 and is determined by the depth of the cavity 14 with the height of the chip 20 as a reference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to the field of high density interconnects, and more particularly to high density interconnects suitable for packing microwave and other overlay sensitive devices. . The present invention
W. P. US Patent Application No. by Kornrumpf et al.
No. (RD-19,879), named "A Bu
ilding Block Approach to
Microwave Modules ", W.M. P. Ko
RNrumpf et al., U.S. Patent Application No. (RD-19,880), entitled "High Densi
ty Interconnected Microwa
ve Circuit Assembly ", W.C. P.
US Patent Application No. by Kornrumpf et al.
No. (RD-19,907), named "Microwav"
e Component Test Method a
nd Apparatus ".
Each of the foregoing is currently pending and is incorporated herein by reference in its entirety.

[0002]

2. Description of the Related Art Microwave systems include monolithic microwave integrated circuits (MMICs), other active microwave devices such as GaAs transistors, passive microwave devices and non-microwave devices such as logic and control structures. Often composed of

A monolithic microwave integrated circuit or MM
An IC is an integrated circuit designed to operate at microwave frequencies. Because GaAs has a much higher possible operating frequency compared to silicon, MMICs
It is usually manufactured in. In a typical MMIC, 1
Includes one or more amplifying elements, several passive elements, and one or more feedback loops that provide feedback from the output of the amplifying element or circuit to provide the integrated circuit with the desired conversion function. In.

In order to manufacture a microwave system including such various elements, a ceramic substrate on which a microstrip RF circuit, a DC supply line (conductor), a logic system, a control system, and connection pads are arranged is manufactured. It is known in the art to attach devices and components such as, MMICs, GaAs transistors, and other microwave and auxiliary components to a substrate and connect them using wire bonding or tab interconnects.

[0005] Such manufacturing techniques have a number of disadvantages. Thick and thin film methods for forming circuitry on ceramic substrates have tolerance limits that make it difficult to manufacture such structures with tight tolerances and reproducible microwave characteristics. To Therefore, the microwave characteristics are different for each substrate even if the substrates are nominally the same. Furthermore,
Due to manufacturing tolerances of active microwave devices themselves such as MMICs and GaAs transistors, there are also differences in operating characteristics between devices. Further, in such structures, there is usually an impedance discontinuity and mismatch at the edges of the MMIC and GaAs transistors. These impedance discontinuities depend on the specific chip placement on the surface of the ceramic substrate or within the cavity. This is because such small changes in the arrangement of the devices change both the width of the gap between the device and the substrate and the arrangement of the device structure with respect to the substrate structure. In addition, these physical assembly tolerances can lead to varying interconnect bond lengths, resulting in different inductances, and thus different circuit performance. These impedance mismatches also change depending on the specific element and the impedance value of the substrate. In addition, the differences in impedance due to these and other manufacturing tolerances are:
It creates reflections and other undesirable operating effects and degrades system operating characteristics. The cumulative effect of these differences manifests in a wide range of system operating characteristics. Therefore, assembling a microwave system using such devices is a relatively low-yield manufacturing process, and many of the manufactured systems do not conform to standards. For this low yield event, it is not easy to couple devices to test equipment, so many active microwave devices can be accurately tested in a non-destructive manner over the entire expected range of operating frequencies and power. We cannot ignore the fact that it is difficult to do. Therefore, many of the devices that have passed the pre-assembly tests do not actually meet the standards.

As the desired operating frequency of such microwave systems has increased from around 2 GHz to higher frequencies in the range of 8 GHz to 16 GHz or more, tolerances and device testing methods in thin film and thick film manufacturing methods. Are more problematic than ever.

Many MMICs and other active microwave devices have delicate structures that are susceptible to breakage or destruction. Among these structures are conductors (structures known as "air bridges") that are located at a certain gap from the surface of the GaAs (air gap).
There is. Wind bridges are used in these MMICs to impart the desired specific operating characteristics to the MMIC. Because of these delicate structures, there are severe limitations on the assembly techniques that can be used to connect these devices into microwave systems. Moreover, such devices are very sensitive when placed with conductors or dielectric materials with a dielectric constant greater than 1 near the surface of the device, especially near inductors, wind bridges, and gate regions of field effect devices. Be affected by it.

In digital systems, individual chips can be extensively tested using wafer probes or other test equipment before being assembled into individual packages.
After packaging, the package can be further tested before being assembled into the system. As a result, the yield in the system assembly is typically very high. This guarantee allowed the digital components to be assembled smoothly into the final system for operation, providing microcomputers and other digital systems at a cost-effective price not imaginable ten years ago.

[0009] Such pre-packaging has not been possible with active microwave devices because the losses and other sacrifices created by the packaging have worse consequences than the anomalies sought to be rescued by the packaging. Therefore, in microwave systems, post-package testing at the element stage cannot be applied as a mechanism for improving the yield of the final assembly. Attempting to fully test a device at the wafer stage requires a relatively large probe to achieve impedance matching with the MMIC or other device under test, and even that is usually not possible. However, to solve the problem of low final yield, active microwave devices for testing, such as those manufactured by Cascade Microtech, so-called co-planar probes.
probe). To use this element, the chip is oversized, a space is provided in the upper surface of the chip, and the space is provided with a signal conductor in the center and two true grounds on both sides of the signal conductor. A microwave port must be provided with symmetrically arranged conductors. This structure is necessary to connect the coplanar probe to the microwave port with sufficient alignment and reproducibility. At microwave frequencies (typically 50M
Unlike the situation with digital chips operating at frequencies below Hz, forming a true ground on the upper surface of the microwave chip is not a simple matter. This generally requires the use of metal connections between the front and back surfaces of the chip. Although such metal connections can be achieved by plated through holes, making plated through holes further complicates the manufacturing process and reduces yield. Even chips designed to use coplanar probes cannot be tested at full power over the entire operating range due to the low thermal conductivity of MMICs. Thus, the design of microwave devices for coplanar probes involves the sacrifice associated with the device itself, such as increased size, increased complexity, and reduced process yield, and is related to system performance by test results. Complete assurance is not obtained.

It is not possible to replace defective elements and rework such structures effectively, since the connection of the elements cannot be removed in a non-destructive manner, which results in a low yield of a complete assembly system. Is a problem that cannot be ignored. Therefore, if the system does not conform to the standard when assembled, it must be scrapped. On the other hand, if the microwave module is designed to be re-workable, the re-work-induced loss is common, but the re-work-induced increase in revenue is of course obtained, although limited.

[0011] This allows for passive components manufactured with highly reproducible characteristics, and pre-tests active devices and / or eliminates any non-defective products when the system fails to meet standards. There is a continuing need for microwave manufacturing processes that allow removal and replacement of defective elements without loss.

The high-density interconnect (HDI) structure or system developed by General Electric offers many advantages with respect to small assemblies of digital and other electronic systems. For example, 30 to 5
An electronic system such as a microcomputer incorporating 0 chips is 2 inches long × 2 inches wide × 0.05.
It can be fully assembled and interconnected on a single 0 inch thick substrate. The maximum operating frequency of such systems is now typically less than about 50 MHz. The compactness of this high density interconnect structure (comp
Even more important is the fact that the structure can be disassembled for repair or replacement of a defective element and reassembled without the danger of a good element incorporated into the system. This reworkability or repairability is a substantial advance over conventional connection systems where reworking of the system for replacing a failed element is not possible or is associated with a substantial danger of a good element. It is.

In summary, in this high density interconnect structure, a ceramic substrate, such as alumina, having a suitable size and length of 25-100 mils thick throughout the system is provided. This dimension is typically less than 2 inches square. Once the various chip locations are defined, separate cavities of appropriate depth or one large cavity are created at the desired locations of the chips. This process may start with a blank substrate having a uniform thickness and desired dimensions. By convention,
Laser or ultrasonic milling is used to form a cavity in which various chips and other elements are placed. In many systems where one wants to arrange the chips edge-to-edge, a single large cavity is sufficient. Large cavities typically have a uniform depth where the semiconductor chip is of substantially uniform thickness. Where a particularly thick or particularly thin element is to be placed, the bottom of the cavity is made deeper or shallower than the other, so that the top surface of the element and the surface of the rest of the element and the surface of the substrate surrounding the cavity are substantially separated. In the same plane. Next, a thermoplastic adhesive layer of a polyetherimide resin, commercially available under the trade name ULTEM from General Electric, is applied to the bottom of the cavity. Next, the various elements are placed at desired locations in the cavity and the entire structure is ULTE
M Polyetherimide softening point (217 ° C to 235 ° C
(Depending on the configuration used) and then cooled until the individual elements are thermoplastically bonded to the substrate. At this stage, the upper surfaces of all the elements are arranged on a substantially common plane. Thereafter, E.I. I. du Pont de N
A 0.0005-0.003 inch (12.5-75 micron) thick polyimide thin film made of emours (trade name: Kapton) is pre-treated so that it can be easily bonded, and one side is ULTEM polyetherimide. Or coated with another thermoplastic resin and laminated over the top surface of the chip group and other elements and the substrate, thereby fixing the Kapton in the correct position using ULTEM resin for the thermoplastic adhesive. I do. Then, Kapton and U are adjusted according to the position of the electronic element connection pad to be connected.
Guide hole (via hole) with laser in LTEM layer
Open s). A metallization layer deposited over the Kapton layer extends through the guide holes and makes electrical contact with the underlying connection pads. The metallization layer may be made to form individual conductor patterns during the deposition process, or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist preferably produces a precisely aligned conductor pattern by exposure at the end of the process using a laser scan relative to the substrate.

Other dielectric and metallization layers are made as needed to make all of the desired electrical connections between the chips. Using an adaptive laser lithography apparatus, which is the subject of a U.S. Pat.

The high-density interconnect structure, manufacturing method and manufacturing equipment of the present invention are disclosed in the following documents. That is, C.I. W. U.S. Patent No. 4,783,695 to Eichelberger et al.
hip Integrated Circuit Pa
cking Configuration and M
method "), C.I. W. U.S. Pat. No. 4,835,704 to Eichelberger et al.
live Lithography System to
Provide High Density Inte
rconnect "), C.I. W. Eichelberg
U.S. Pat. No. 4,714,516 (named "Me
thing to Product Via Holes
in Polymer Dielectrics f
or Multiple Electronic Ci
rcuit Chip Packing "); J. W
U.S. Pat. No. 4,780,17 to Ojnarowski et al.
No. 7 (named "Excimer Laser Patte"
ringing of a Novel Resistance
t "), R.C. J. U.S. Patent Application No. 249,917 to Wojnarrowski et al. (Filed September 27, 1989;
Name "Method and Apparatus f
or Removing Components Bo
nd to a Substrate "), C.I.
W. U.S. Patent Application No. 31 to Eichelberger et al.
No. 0,149 (filed on Feb. 14, 1989, with the name "La
ser Beam Scanning Method
for Forming Via Holes in
Polymer Materials "); J. W
and US Patent Application No. 312,79.
No. 8 (filed on Feb. 21, 1989, entitled "High D
efficiency Interconnect Therp
lastie Attach Materialia
l and Solvent Die Attachm
ent Processing "), C.I. W. Eich
US Patent Application No. 283,095 to Elberger et al. (filed December 12, 1988, entitled "Simplif"
ied Method for Repair of
High Density Interconnect
Circuits "), H.C. S. U.S. Patent Application No. 305,314 to Cole et al. (Filed February 3, 1989;
The name "Fabrication Process an
d Integrated Circuit Test
Structure "), C.I. W. Eichelbe
rger et al., U.S. Patent Application No. 250,010 (198
Filed on September 27, 2008, entitled "High Density
Interconnect With High V
olumetric Efficiency ");
j. U.S. Patent Application No. 32 to Wojnarrowski et al.
No. 9,478 (filed on Mar. 28, 1989, titled "Di
e Attachment Method for U
se in High Density Interc
connect Assemblies "); S. C
Ole et al., U.S. Patent Application No. 253,020 (1988).
Filed on October 4, 2010, titled "Laser Interco
nect Process "), C.I. W. Eiche
Iberger et al., U.S. Patent Application No. 230,654, filed August 5, 1988, entitled "Method and
d Configuration for Select
sonic Circuits and Integr
provided Circuit Chips Using
a Removable Overlay Layer
r "), Y. S. US Patent Application No. 233,9, Liu et al.
No. 65 (filed on August 8, 1988, with the name "Direct
Deposition of Metal Patt
erns for Use in Integrate
d Circuit Devices "); S. L
iu, et al., U.S. Patent Application No. 237,638 (filed August 23, 1988, entitled "Method for Pho").
toppatterning Metallatio
n Via UV Laser Ablation
of the Activator "); S. Li
U.S. Patent Application No. 237,685 (August 1988)
Filed on March 25, with the name "Direct Writing"
of Refractory Metal Lines
for Use in Integrated Ci
rcuit Devices "), C.I. W. Eiche
No. 240,367 (filed Aug. 30, 1988, entitled "Method a."
second Apparatus for Packing
Integrated Circuit Chips
Employing a Polymer Film
Overlay Layer "); S. Cole
Et al., U.S. Patent Application No. 342,153 (filed April 24, 1989, entitled "Method of Procedures").
sing Siloxane-Polyimides
for Electronic Packaging
Applications "), Y. et al. S. U.S. Patent Application No. 289,944 to Liu et al. (December 27, 1988)
Filed under the name of “Selective Electric
ytic Deposition on Conduct
tive and Non-Conductive S
ubstrates "); J. Wojnarrows
No. 312,536 (filed February 17, 1989, entitled "Method of Bond").
ing a Thermoset Film to a
Thermoplastic Material t
o Form a Bondable Laminat
e "), C.I. W. U.S. Patent Application No. 363,646 to Eichelberger et al. (Filed June 8, 1989;
Name "Integrated Circuit Pac
kaging Configuration for
Rapid Customized Design a
nd Unique Test Capabilit
y "), H.E. S. U.S. patent application Ser.
No. 9,844 (filed Jan. 2, 1990, entitled “Are
a-Selective Metallization
Process "); R. No. 07 / 457,023 to Haller et al. (Filed December 26, 1989, entitled "Locally Orientat"
ion Specific Routing System
em "), H.E. S. US Patent Application No. 45 to Cole et al.
No. 6,421 (filed on December 26, 1989, with the name "L
aser Ableable Polymer Di
electrics and Methods "),
W. P. U.S. Patent Application No. 45 to Kornrumpf et al.
No. 4,546 (filed on December 21, 1989, with the name "H
ermatic High Density Inte
rconnected Electronic Sys
tem "); S. U.S. Patent Application No. 07 to Cole et al.
No./457,127 (filed on December 26, 1989, entitled "Enhanced Fluorescence P
oligomers and Interconnect
Structures Using Them ") and C.I. W. U.S. Patent Application No. 454,545 to Eichelberger et al. (Filed December 21, 1989, entitled "An Epoxy / Polyimide Copol"
ymer Blend Dielectric and
Layered Circuits Incorpo
rating It "). These patents and patent application specifications are hereby incorporated by reference.

This high density interconnect system has been developed for use in interconnect semiconductor chips forming a digital system. That is, for connecting systems whose operating frequency is typically less than about 50 MHz, at which frequency transmission lines, other wave impedance matching and dielectric loading effects may not be considered necessary. Low.

[0017] In the interconnection of microwave structures or devices that wish to operate at GHz frequencies, a number of problems, considerations and endeavors have not been encountered in interconnecting digital systems operating at frequencies below 50 MHz. Surface. The use of microwave frequencies does not matter at low frequencies, such as digital systems, with respect to wave characteristics, transmission line effects, the presence of sensitive structures where MMICs and other components are bare, and the characteristics of systems and components. It becomes necessary to consider such matters. These considerations include that dielectric materials are suitable for use at microwave frequencies because materials that were good dielectrics at low frequencies also exhibit high loss or even conductivity in microwaves There is a question of why. Further, even if the dielectric does not exhibit lossy properties at microwave frequencies, the dielectric constant itself is too high and MMIC, GaAs interconnected using high density interconnect structures.
The operating characteristics of the s-transistor and other microwave elements or structures may be altered unacceptably.
In the process of depositing the first dielectric layer of this high density interconnect structure, substantial pressure is applied to the polyimide thin film, so that laminating pressure may disrupt the structure or cause the thermoplastic adhesive to adhere to the conductor. Permeation into the lower air gap may change the dielectric properties of the air gap, or even the mere presence of the dielectric may significantly change the operating characteristics of the device,
Damage, collapse or deformation of the air bridge and other sensitive structures of the microwave element may occur.

[0018] Low yields of the final assembly of the microwave system raise the cost of the final device and make the manufacturing process more technically colored than semiconductor manufacturing technology, so this type of system is very Become expensive. In order to increase the yield of the final system and reduce the cost to the extent that it can be used for service systems, efficient, high-yield systems that enable individual microwave components and subsystems to be assembled into the final system at high yields. Techniques for packing by methods are needed.

The related application No. ((RD-19,88)
0) Name "High Density Interco
nnected Microwave Circuit
Assembly ") solves the problems associated with the reworkability and low tolerance of passive components of prior art thin and thick film microwave system assembly methods, which may result in non-compliant microwave systems when assembled. If
Disassemble and remove defective elements so that they can be reassembled without damaging good elements. The application also discloses a method of removing the high density interconnect dielectric from the overlay-sensitive portion of the chip. However, overlay sensitivity is
Devices where the device or element is unaffected by the interconnect dielectric material and where the high density interconnect dielectric is located on the chip or structure or on at least an overlay-sensitive portion of the chip or structure Alternatively, it means that the operation characteristics of the elements are different.

The related application No. ((RD-19,87)
9) Name "A Building Block App"
roach to Microwave Module
s ") provides a solution to the problem of how to pack microwave devices in an efficient, reliable, and high yield manner, and assembles microwave system assemblies in terms of both efficiency and yield. Manufactured from fascinating and desirable prepackaged parts.

The related application No. ((RD-19,90)
7) Name "Microwave Component"
Test Method and Apparatus
s ") provides a solution to the problem of testing microwave devices in an efficient and highly correlated manner with little risk of damaging the device.

Unfortunately, RD-19,880 and R
While the technique disclosed in D-19,879 offers the advantage that the microwave device can be packaged with the high density interconnect structure, the conductors of the high density interconnect structure have an area where the dielectric layer is to be removed. Because it can not be wired above
The disadvantage is that the high-density interconnect dielectric layer must be excluded from the surface of the overlay-sensitive microwave device, which severely limits the surface area available for wiring conductors of the high-density interconnect structure. If the chips are tightly packed at maximum density, this is an inherent limitation, in that the high-density interconnect structure extends from the connection pads of one chip to the connection pads of an adjacent chip. It must be wired to conductors in body passages and street sections. If only a relatively low interconnect density is needed,
This constraint is acceptable without seriously affecting the structure or operation of the system. However, if high density interconnect conductors are required, such constraints may render the system unwiringable or require an extra number of interconnect conductor layers, or may otherwise be necessary. Not so wide that the passages and streets to accommodate the required amount of interconnect conductors need to be widened.

Very small digital systems and / or digital systems designed to operate at frequencies in the GHz range are sensitive to the presence of a coating dielectric layer and are in the ordinary sense of microwave circuits. Otherwise, it does not use transmission lines and similar technologies. Such a VHF digital system requires interconnects as dense as those required for systems operating in the frequency range below 50 MHz. Eliminating the dielectric layer on the center of the chip places severe restrictions on the available wiring area.

[0024]

Therefore, there is a need for a high density interconnect structure that accommodates the overlay sensitivity of many devices without sacrificing the wiring density of the high density interconnect structure.

Accordingly, a primary object of the present invention is to provide an active die area at the expense of circuit density.
The purpose of the present invention is to enable a high-density interconnect process to be used with a VHF system without excluding the polymer dielectric layer from rea).

It is another object of the present invention to facilitate removal of a dielectric layer of a high density interconnect structure from the active area of a high frequency chip without adversely affecting the operating characteristics of the chip.

Another object of the present invention is to enable the use of high-density interconnect structures in cameras or line array technologies that require an active area of the device that eliminates the obstruction to a clear, unattenuated scene. is there.

[0028]

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects will become apparent from the following description taken in conjunction with the accompanying drawings, in which the present invention allows the dielectric layer of a high density interconnect structure to be integrated into a chip. Achieved by raising above the active area. In one embodiment, if the chip is overlay sensitive, create a chamber over the active portion of the chip. This can prevent unwanted deleterious interactions between the high density interconnect structure and the overlay-sensitive chip.

According to one embodiment of the invention, the chip is placed in a cavity of the substrate that is deeper than the thickness of the chip. The first dielectric layer of the high density interconnect structure is laminated to a flat portion of the upper surface of the substrate and is pressed down into the cavity during the lamination process and adhered to the exposed surface of the chip.
A patterned first metallization layer is supported by the dielectric layer and extends from an ohmic contact with a connection pad of the chip onto a flat portion of the upper surface of the substrate. The first layer of dielectric material is remote from the overlay-sensitive portion of the chip. Thereafter, a second dielectric layer of the high density interconnect structure is laminated over the first layer of dielectric material, the first metallized layer. During the lamination process, this second dielectric layer is pulled taut and sags down to the chip or the first dielectric layer portion extending downwardly to the recess where the chip is located;
Never contact. A second metallization layer (of the normal pattern of the high density interconnect) is disposed over the second dielectric layer. Because there is a gap between the second dielectric layer and the active portion of the chip due to the chamber, even though the chip is overlay-sensitive, the conductor of the second metallization layer extends across the chip. It does not adversely affect the operating characteristics of the device. One or more chips may be located in the cavity, and there may be one or more such cavities in the structure. In one structure, some chips may have a raised dielectric layer, while others may not.

This structure can be manufactured in various ways. The second, strained dielectric layer may be formed by holding and extending the preformed dielectric layer to the frame during lamination. Alternatively, the second dielectric layer can be used to prevent it from sagging during the bonding process.
It may be pre-adhered to a rigid support such as a metal backing layer. To aid in preventing droop, a fluid conduit port may be provided in the substrate to balance the lamination pressure with the pressure in the chamber where the chips are located during the lamination process.

The atmosphere within the chamber may be adjusted by evacuating the chamber of the final structure or by introducing a selected fluid (gas or liquid) into the chamber via a pressure equilibrium conduit. If desired, the conduit may be formed to provide a continuous flow of gas or liquid through the chamber for cooling or other purposes.

The subject matter of the present invention is particularly pointed out and distinctly claimed in the appended claims. However, the invention, together with further objects and advantages, can be best understood with reference to the following description, taken in conjunction with the accompanying drawings, in which the mechanism and method of practice of the invention are practiced.

[0033]

FIG. 1 is a cross-sectional view of a portion of a system 10 according to the present invention. The system 10 includes a substrate 12. The substrate is preferably ceramic, but may be a metal or other material that provides a good match for the coefficient of thermal expansion of the substrate and the chips mounted thereon. The substrate 12 includes a cavity 14 inside which a semiconductor chip and other electronic elements 20 are mounted. Two fluid conduits 16 communicate with the cavity 14 from the back of the substrate. Semiconductor or other chip 20 is preferably a thermoplastic (not shown)
To fix in the chamber. Chip 20 has an active area 22 on the upper surface, and a plurality of connection pads 24 are disposed on the upper surface along the periphery of the upper surface. First H
A DI dielectric layer 32 is adhered to the flat portion 13 on the upper surface of the substrate 12 and the upper surface of the chip 20. Dielectric layer 3
Two windows 50 are located over the active area of the chip. No dielectric is disposed inside the window 50. A plurality of conductors 34 are disposed on the dielectric layer 32 and the connection pads 2
4 and extends into guide holes drilled in the dielectric layer. The conductor 34 further extends over the flat portion 13 of the substrate surface. This interconnect structure has unique features in the manufacturing process (as disclosed by the related patents and patent applications), first the process of bonding the dielectric layer to the underlying structure and then the laser "drill". Forming a guide hole in the dielectric layer from above, followed by placing a metal conductor 34 over the dielectric and into the guide hole, where the conductor is located underneath connection pads and other metallized portions. And forming an ohmic contact. In particular, the external shape of the metal in the guide hole takes on the shape of the guide hole, as opposed to the case where the metal is formed first and the dielectric is filled around it. The nature of the laser drilling process used to form guide holes by drilling from the top is typically
That is, a guide hole in which the top portion is wider than the bottom portion is obtained. The shape of the guide hole improves the continuity of the metal between the conductor portion disposed on the bottom portion of the guide hole and the conductor portion outside the guide hole. This is because the wall surface of the guide hole where the metal is arranged is inclined upward and outward (slopin).
Due to g-upward-and-outward) shapes, it is known in semiconductor technology that such shapes result in better step coverage of the deposited metallization layer than vertical wall shapes. The term "step coating"
Means the uniformity of the metallization when the deposition surface changes height from one planar area (bottom of the guide hole) to another planar area (top of the dielectric layer). Once the conductor is formed according to the preferred methods described in the related patents and patent applications, the conductor metal is found everywhere, including in the guide holes (not filled prior to the deposition of the metal across the plane of the dielectric layer). Is deposited to a substantially uniform thickness, the upper surface of the metal conductor is typically depressed or dimpled where it hits the guide holes.
e) is possible. Thus, the topology of the metallized surface will be the same as that of the layer on which the metal is deposited.

The main role of the conductor 34 is to guide the connection pad 24 to the flat portion 13 to connect the next high-density interconnect layer. Further, the interconnect conductor extends through this layer to the flat portion of the substrate. The inclusion of wired conductors in this layer is particularly advantageous in that there is no need to provide an extra interconnect layer in the overall structure.

A window 50 in the dielectric layer 32 surrounds the active area 22 of the chip 20. The second dielectric layer 36 extends to the chip including the cavity and forms the chamber 18 and the chamber 1
8, the ceiling of the chip 20 is separated from the active portion 22 of the chip 20 by an upward direction, that is, is raised. The height of the ceiling is selected according to the operating characteristics and the degree of sensitivity of the chip 20. Is determined by the depth of the cavity 14. This gap is preferably 1 to 12 mils in height. A plurality of high-density interconnect conductors 38 are disposed on the upper surface of dielectric layer 36 and are aligned with conductors 34 suitable for the desired interconnect pattern for the overall system.
Into the drilled guide hole. The conductor 38 is the chip 2
0 may extend across the active region 22 of the chamber 18.
Is sufficiently high that the dielectric layer 36 and the conductor 38 disposed thereon are disposed on the upper surface sufficiently far from the upper surface of the chip 20 to substantially prevent interference between the dielectric layer 36 and the operating characteristics of the device 20. Therefore, the operation characteristics of the chip 20 are not adversely affected.

The first stage of manufacture of the system 10 of FIG. 1 is shown in cross section in FIG. In FIG. 2, the first dielectric layer 32
Is located on top of the substrate 12 and chip 20. On the chip 20, a dielectric layer 4 is arranged which extends over the active part or at least the overlay-sensitive part of the chip.
0, which layer is somewhat larger than the active area 22 of the chip 20. This dielectric layer is made of Kzpton or Teflon.
Any of those considered desirable may be used. In any case, layer 40 is preferably merely physically disposed on the surface of the chip instead of being adhered to chip 20. next,
A dielectric layer 32 is stacked over the chip, dielectric 40 and substrate 12. In carrying out this stacking, the cavity 14
And a laminating pressure source that brings the Kapton layer into intimate contact with the flat surface 13 of the upper surface of the substrate and the upper surface of the chip.

Following this lamination process, the guide holes 33 are laser drilled in the dielectric layer 32. Next, as shown in FIG. 3, a pattern of conductors 34 is formed on the surface of the dielectric layer 32 with suitable conductors 34 extending into the guide holes and to the ohmic contacts comprising the connection pads 34 of the chip. All conductors 34
Is a flat portion 1 of the substrate surface from the guide hole 33 on the chip 20.
3 to cover.

Next, as shown in FIG.
Is laser cut around the outer edge of the dielectric layer 40,
A kerf 52 is formed to facilitate removal of the portion 32W of the dielectric layer 32 that covers the overlay sensitive portion of the chip 20.

FIG. 5 shows the structure after removal of the cut or window portion 32W of the dielectric layer, together with the dielectric layer 40 to which it was adhered. This leaves a window 50 without the high density interconnect dielectric. Window 50 surrounds active area 22 of the chip. Next, a second layer 36 of dielectric material is laminated over the structure, with a guide hole drilled thereon, and a pattern of metal conductors 38 drawn thereon to form a structure as shown in FIG. The body is obtained.

While the first dielectric layer 32 is being laminated to the substrate 12 and the chip 20, the conduit 16 is preferably connected to a vacuum device to bond the dielectric layer 32 to the surface of the chip 20 It is easy to shape the structure to fill the gap 17 between the upper surface and the flat portion of the substrate 16. Second
During the lamination of the dielectric layer 36, a positive pressure is introduced into the cavity 18 via the conduit 16 so that the dielectric layer 36 remains in the chamber 18 while the lamination pressure is applied to the second dielectric layer 36.
You may prevent it from hanging inside.

In a typical high density interconnect structure, as described in related patents and patent applications, the dielectric layer 3
The portion of the cavity 14 below 2 is sealed against the outside air above the dielectric layer 32 by the lamination of the air-impermeable layer 32. Such sealing is inconsistent with applying a positive pressure in the chamber to support the ceiling of the chamber during lamination. Therefore, if it is desired to apply a positive pressure to the chamber 18 during lamination or at other times, laser drill a suitable hole in the dielectric layer 32 before laminating the second dielectric layer 36 to the structure. Is preferred. The laser drill is preferably performed after the deposition and patterning of the conductive traces 34 so that no extra liquid processing steps are performed after drilling and before laminating the second dielectric 36. In this way, the presence of the first dielectric layer 32 can prevent the liquid processing liquid from entering the cavity and accumulating.

If desired, the dielectric layer 36 may be taut and adhered to the rigid washer and then disposed on the layer 32. Thereafter, laminating pressure is applied to the rigid washer to prevent the dielectric layer 36 from sagging, and the dielectric layer 36
2 and the exposed portion of the body 34. The material of this washer is preferably aluminum or other metal,
After the completion of the lamination process, the dielectric layer 36 is removed by being corroded or dissolved.

The Teflon layer 40 was used to allow the dielectric layer 32 to be removed from the active portion of the chip 20 without detrimentally affecting the active portion of the chip 20, but instead was soluble. Is deposited on the active portion of the chip 20 with a non-laser abradable adhesive layer, which is then laser abradable so as to be deposited as a layer 32 on the upper surface of the substrate and chip. Thermoplastic adhesives may be used. In this method, the laser abradable dielectric deposited over the active portion of the chip is removed by laser ablation. In this laser ablation, a laser is scanned across the active area of the chip 20 in a suitable pattern, and substantially all of the laser abradable portion of the dielectric layer 32 is laser ablated. Thereafter, the system 10 may be immersed in a suitable solvent to dissolve the exposed soluble adhesive,
Alternatively, the surface of the dense interconnect structure is sprayed with a solvent and the exposed portions of the non-laser abradable thermoplastic adhesive are removed by dissolving in the solvent. According to this method, there is no need to remove chip fragments generated by laser abrasion by plasma etching. (Plasma cleaning of the surface of the HDI structure may be performed before dissolving the non-abrasive adhesive.)

A typical microwave device is made of gallium arsenide. Gallium arsenide has a thermal conductivity that is approximately 1/3 that of silicon. Thus, heat generated in the gallium arsenide active device is not readily conducted from gallium arsenide to substrate 12. Accordingly, it has been found desirable to couple the pressure equalizing conduit 16 to a suitable cooling system suitable for flowing a gaseous or liquid coolant through the chamber 18 to facilitate the heat dissipation process. Alternatively, rather than continuously flowing the liquid coolant through the chamber, the chamber may be maintained in a suitable atmosphere to facilitate heat transfer from the chip, or the interior of the chamber may be maintained at a desired dielectric constant. it can.

In high density interconnect structures, the dielectric layer 36 is typically continuous and substantially impermeable,
Dielectric layer 36 has an opening formed in the interior ceiling portion to prevent chamber 18 from being a sealed chamber or for other purposes, to provide a specific portion of the electromagnetic spectrum, including ultraviolet and infrared portions. In some cases, ultraviolet light or infrared light is transmitted into the chamber 18 while avoiding attenuation due to transmission through the highly absorbing dielectric layer 36.

The chamber 18 is preferably a vacant in which the chip 20 is particularly sensitive to an increase in the relative permittivity of objects adjacent the chip surface. The term "hollow" is used in this connection, including the presence of a vacuum and gas atmosphere in the chamber. Chamber 1
8 may be considered as a low dielectric constant chamber because a fluid is present in the interior instead of a solid. In this broad sense, fluids include liquids, gases and vacuum, which is effectively a very low density gas.

Although a particular embodiment of the present invention has been illustrated and described, structures that include multiple chips in a single cavity or structures that include multiple separate chambers in a single high density interconnect structure Or this combination, such as a combination of a chip having a high density interconnect dielectric lifted up and a chip having a high density interconnect dielectric placed in contact with the entire upper surface of the chip. It will be understood that many variations can be made.

Although the present invention has been described in detail by way of a preferred embodiment, many modifications and variations will be apparent to those skilled in the art and, therefore, the scope of the present invention is deemed to be limited to the true spirit and scope of the invention. It is intended to cover all such modifications and variations contained within.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a system including a chamber manufactured according to the present invention.

FIG. 2 is a cross-sectional view showing a lamination process in a manufacturing process of the structure shown in FIG.

FIG. 3 is a cross-sectional view showing a conductor forming process in the manufacturing process of the structure of FIG. 1;

FIG. 4 is a cross-sectional view showing a process of forming a kerf in a process of manufacturing the structure of FIG. 1;

5 is a cross-sectional view showing a process of removing a window portion and a dielectric layer in the manufacturing process of the structure of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 System 12 Substrate 13 Upper flat part of substrate 12 14 Cavity 16 Conduit 17 Gap 18 Chamber 20 Semiconductor or other chip 22 Active area of chip 20 24 Connection pad 32 First dielectric layer 33 Guide hole 34 Conductor 36 Second dielectric Body layer 38 High-density interconnect conductor 40 Dielectric layer 50 Window

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Charles William Eichelberger, United States 12308, Schenectady, Weverly Place, New York 1256 (72) Inventor William Paul Kornluff, 12202, New York, United States Elm Street 218

Claims (45)

[Claims] A high density interconnect structure comprising: a plurality of electronic chips; a layer of dielectric material adhered to said chips; and a pattern of conductors deposited on or within said dielectric material. A high density interconnect system of the type wherein the conductors of said high density interconnect structure electrically interconnect said electronic chips, wherein one of said chips is a chamber chip and the upper surface thereof is said high density. A chip spaced from the overlay layer of the interconnect structure; and a portion disposed at an angle to the plane of the overlay layer at an angle to the top of the chamber chip from the overlay layer. A first dielectric layer of the dense interconnect structure extending to a surface, the first dielectric layer being adhered to both the overlay layer and the upper surface of the chamber chip; A first layer of high density interconnect dielectric, disposed over the first dielectric layer of the high density interconnect structure, extending from ohmic contacts to connection pads of the chamber chip to the overlay layer A first layer of a high density interconnect conductor comprising a conductor. 2. The structure of claim 1, wherein said overlay layer comprises a second dielectric layer of said high density interconnect structure, and wherein said second dielectric layer comprises said first dielectric layer. A second dielectric layer adhered to portions of the body layer and extending to the chamber chip and spaced from the upper surface, whereby the second
Wherein the dielectric layer forms a ceiling of a chamber disposed between the chamber chip and the second dielectric layer. 3. The structure of claim 2, wherein said chamber extends from said upper surface of said chamber to said second dielectric layer. 4. The method according to claim 1, further comprising a second layer of high density interconnect conductor disposed on said second dielectric layer, wherein at least some conductors of said second conductor layer are said first conductor. 3. The structure according to claim 2, wherein the structure is in ohmic connection with the conductor of the layer. 5. The structure of claim 4, wherein said ohmic contact contacts said conductor of said first conductor layer at a location where said first conductor is separated from a plane of an upper surface of said chamber chip. . 6. The structure of claim 5, wherein said second conductor layer extends over said ceiling portion of said second dielectric layer. 7. The structure of claim 2, wherein said chamber is hollow. 8. The structure of claim 1, wherein said chamber chip is an overlay-sensitive chip having an overlay-sensitive portion on an upper surface. 9. The structure of claim 8, wherein said overlay-sensitive portion of said overlay-sensitive chip lacks a high density interconnect dielectric material. 10. The dielectric material of the high density interconnect structure wherein the overlay-sensitive portion of the overlay-sensitive chip extends in alignment with the overlay-sensitive portion of the overlay sensitive chip. 10. The structure of claim 9 further separated by at least 1 mil. 11. The overlay-sensitive tip of the overlay-sensitive tip is 1-2 mils apart from any of the structures extending in alignment with the overlay-sensitive portion of the upper surface of the overlay-sensitive tip. The structure of claim 10, wherein the structure is: 12. The structure of claim 1, wherein the system comprises a substrate having a chip containing cavity therein, wherein the chamber chip is disposed in a cavity deeper than the thickness of the chip, The upper surface of the chamber chip is
A structure disposed in a recess relative to a flat portion of an upper surface of the substrate. 13. The structure of claim 12, wherein a portion of said first layer of high density interconnect dielectric is adhered to said flat portion of an upper surface of said substrate. 14. The structure of claim 12, wherein said substrate comprises a fluid conduit disposed in communication with said chamber. 15. The structure of claim 14, wherein the conduit is configured to form a fluid flow through the chamber. 16. The ohmic contact between the conductor of the first layer of the high density interconnect conductor and the conductor of the second layer of the high density interconnect conductor, wherein the ohmic contact is formed on the upper surface of the substrate. 5. The structure of claim 4, wherein the structure is disposed over the flat portion. 17. The structure of claim 4, wherein several conductors of said second layer of high density interconnect conductors are located on or within said ceiling portion of said high density interconnect structure. 18. The structure of claim 17, wherein several conductors of said second layer of high density interconnect conductor extend over said chamber chip. 19. A high density interconnect structure comprising: a plurality of electronic chips; a layer of dielectric material adhered to said chips; and a pattern of conductors deposited on or within said dielectric material. A high density interconnect system of the type wherein the conductors of said high density interconnect structure electrically interconnect said electronic chips, wherein one of said chips is raised above a portion of its upper surface. A structure comprising a dielectric material. 20. The structure of claim 19, wherein said raised dielectric material comprises a conductor of said high density interconnect structure extending over said one of said chips. 21. A structure comprising a combination of a semiconductor chip, a layer of a dielectric material lifted up to reach the chip, and a layer of the dielectric material having conductor wiring on an upper surface thereof. . 22. The combination of claim 21, wherein said dielectric layer supports said conductor. 23. A high density interconnect structure comprising: a plurality of electronic chips; a layer of dielectric material adhered to said chips; and a pattern of conductors deposited on or within said dielectric material. A method of manufacturing a high-density interconnect system of the type in which the conductors of the high-density interconnect structure electrically interconnect the electronic chip, comprising: (a) flattening the upper surface of the chip with the upper surface of the substrate; Recessing the portion and placing the chip; (b) depositing a first layer of high density interconnect dielectric on a flat portion of an upper surface of the substrate;
(C) forming a high-density interconnect conductor on the first layer of the high-density interconnect dielectric, and forming the high-density interconnect conductor on the first layer of the high-density interconnect conductor; Including a conductor extending from an ohmic contact to a connection pad of a placed chip to the flat portion of the upper surface of the substrate; and (d) a second layer of high density interconnect dielectric comprising: Bonding the second layer of high density interconnect dielectric to the plurality of portions of the first layer of high density interconnect dielectric disposed over the flat portion of the upper surface of the substrate, wherein the second layer of high density interconnect dielectric is recessed. Spreading to a recess containing the chip located at a location and spaced from the upper surface of the chip located at the recess by a chamber; and (e) a second of the high density interconnect conductors. Forming a layer over the second layer of high density interconnect dielectric; The second layer of interconnect conductor is ohmic-connected to the conductor of the first layer of high-density interconnect conductor at a contact disposed over the flat portion of an upper surface of the substrate. A method comprising the steps of: 24. The method of claim 23, wherein prior to step (d), a high density interconnect dielectric of the first layer of high density interconnect dielectric from the portion of the recessed surface. A method further comprising performing a step of removing material. 25. The method of claim 24, wherein the chip located in the recess has an overlay-sensitive portion, and bonding the first layer of the high density interconnect dielectric. Prior to the step of placing a release layer overlying the overlay-sensitive portion of the chip located in the recess. 26. The method of claim 25, wherein said release layer is not adhered to said chip. 27. The second of the high density interconnect dielectrics
Prior to the step of bonding the layers, further comprising the step of trimming the portion of the release layer and the first layer of high density interconnect dielectric over the overlay sensitive portion of the released chip. 25. The method of claim 25. 28. The method of claim 25, wherein the release layer comprises: an upper layer that can be abraded by a particular wavelength of ultraviolet light; and a lower layer that is not abradable by the particular wavelength of ultraviolet light. A method comprising providing a laminate having: 29. The method of claim 25, wherein prior to the step of bonding said second layer of said high density interconnect dielectric, said first layer of high density interconnect dielectric; Abrading a portion of the release layer disposed over the overlay sensitive portion of the released chip with a portion of the upper layer; bonding the second layer of the high density interconnect dielectric Dissolving a portion of the lower layer of the release layer disposed over the overlay sensitive portion of the released chip, prior to the step of dissolving. 30. The method of claim 25, wherein step (d) comprises: securing the second layer of the high density interconnect dielectric to a fixture, wherein the fixture includes the high density interconnect. Operation of the chip in which the second layer of interconnect dielectric is supported in full tension with the second layer of high density interconnect dielectric depending on the interior of the chamber and in the recess Preventing the detrimental effect on properties; and bonding the second layer of the high density interconnect dielectric to the first layer of the high density interconnect dielectric. A method further comprising: 31. The method of claim 30, wherein the fixture is attached to the first layer of the high density interconnect dielectric and the second of the high density interconnect dielectric is bonded to the first layer of the high density interconnect dielectric. A method further comprising separating from a portion of the layer. 32. The method of claim 25, wherein step (d) comprises: securing the second layer of the high density interconnect dielectric to a backing plate, wherein the backing plate comprises the high density interconnect. Operation of the chip in which the second layer of interconnect dielectric is supported in full tension with the second layer of high density interconnect dielectric depending on the interior of the chamber and in the recess Preventing the detrimental effect on properties; and bonding the second layer of the high density interconnect dielectric to the first layer of the high density interconnect dielectric. A method further comprising: 33. The method of claim 32, wherein the back plate is adhered to the first layer of the high density interconnect dielectric or spans the chamber. A method further comprising separating from a portion of the second layer of dielectric. 34. The method of claim 23, wherein as part of step (d), providing a pressure-balancing opening within the second layer of the high density interconnect dielectric; Bonding the second layer of interconnect dielectric, the method comprising: helping prevent the second layer of the high density interconnect dielectric from drooping into the chamber. . 35. The method of claim 25, wherein a pressure balancing opening is provided within the substrate to bond the second layer of the high density interconnect dielectric. A method comprising: allowing the second layer of interconnect dielectric to drip into the chamber to help prevent a deleterious effect on operating characteristics of the chip located in the recess. 36. A high density interconnect structure comprising: a plurality of electronic chips; a layer of dielectric material adhered to said chips; and a pattern of conductors deposited on or within said dielectric material. A method of manufacturing a high density interconnect system of the type wherein the conductors of the high density interconnect structure electrically interconnect the electronic chips, wherein the upper surface is higher than a plane of a flat portion of the upper surface of the substrate. One of the chips located in the recess recessed downwardly, extending from above the top of the flat portion of the upper surface of the substrate to the recessed upper surface of the chip located in the recess, and A first layer of high density interconnect dielectric adhered to both the flat portion and the upper surface of the chip located in the recess; and a first dielectric of high density interconnect structure Placed on a layer Method of manufacturing and a first layer of high density interconnect conductors having a conductor extending from the ohmic contact to the connection pads of the chips arranged in said recess to said flat portion of the upper surface of the substrate. 37. The method of claim 36, wherein the high density bonded to a portion of the first layer of a high density interconnect dielectric disposed over the flat portion of an upper surface of the substrate. A second layer of interconnect dielectric, wherein the second layer of high density interconnect dielectric spans a recess containing a chip disposed in the recess and is free of solid and liquid dielectrics; Forming a canopy overlying the chip located in the recess, spaced from an upper surface of the chip located in the recess, and the second layer of high density interconnect dielectric For a second layer of high density interconnect conductors disposed above the at least some of said second layers of high density interconnect conductors are ohmically connected to said first layer of high density interconnect conductors And b. Further comprising the steps of: 38. The ohmic connection contacts the conductor of the first layer of a high density interconnect conductor where the conductor is located over the flat portion of the upper surface of the substrate. the method of. 39. The method of claim 38, wherein said second layer of high density interconnect conductor comprises a conductor extending over said canopy portion of said second layer of high density interconnect dielectric. 40. The method of claim 36, wherein the chip located in the recess is an overlay-sensitive chip having an overlay-sensitive portion. 41. The method of claim 40, wherein said overlay-sensitive portion of said overlay-sensitive chip does not include a high density interconnect dielectric material. 42. A second layer of high density interconnect dielectric adhered to a portion of said first layer of high density interconnect dielectric disposed over said flat portion of an upper surface of said substrate. Wherein the second layer of high density interconnect dielectric includes a canopy portion that spans a depression containing the chip located in the recess, and solids and liquids from the upper surface of the chip located in the recess. And a second layer of high density interconnect conductor disposed over said second layer of high density interconnect dielectric, wherein said second layer of high density interconnect dielectric comprises: 42. The method of claim 41, further comprising: ohmic connecting at least some of the second layers to the first layer conductors of the high density interconnect conductor. 43. The liquid-free and solid-free volume:
5. The method of claim 4 wherein said recess extends from an upper surface of said chip to a lower surface of said second layer of high density interconnect dielectric.
2. The method according to 2. 44. The ohmic connection contacts the conductor of the first layer of a high density interconnect conductor where a conductor is disposed over the flat portion of an upper surface of the substrate. the method of. 45. The method of claim 44, wherein said second layer of high density interconnect conductor comprises a conductor extending over said overlay-sensitive portion of said overlay-sensitive chip.