JPH11285008A - Image coding method and image coder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a required processing bit number, to decrease the circuit scale and to enhance the signal processing speed in the case of coding an image through the use of orthogonal transform such as DCT. SOLUTION: In the case of coding an image using orthogonal transform such as DCT, an input to quantization 14 is subtracted from output data of inverse quantization 18 by a subtractor 22, and the result is given to inverse DCT 19. An output of the inverse DCT 19 is added to the input to the DCT 13 by an adder 23 and the sum is added to data after motion compensation by an adder 25 to obtain local decoding data. Or local decoding data are obtained by adding original image date to be coded to an output of the inverse DCT 19 at an adder 33. Number of bits (dynamic range) of input data to the inverse DCT is decreased and the arithmetic operation speed is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding method and an image encoding apparatus, and more particularly to a signal processing method of an image signal encoding unit using an orthogonal transform such as DCT and an apparatus therefor.

[0002]

2. Description of the Related Art When transmitting or storing image information (image data) as digital data, encoding is performed by compressing redundancy in order to reduce the amount of data. As a coding method for compressing the redundancy, there is a method of reducing the redundancy by utilizing the temporal or spatial correlation of the image data. In particular, as a method using spatial correlation, an image is divided into blocks of a predetermined size (for example, a block of 8 pixels in both the vertical and horizontal directions), and the data in the blocks are subjected to orthogonal transform, and transform coefficients are calculated. There is a method of performing scan conversion (for example, rearranging in order from low frequency components to high frequency components), quantizing, and performing variable length coding. H.2 has become an international standard for videophones. 261 and H.E. H.263, and an image coding method MPEG2, for which MPEG (Moving Picture Experts Group) for broadcasting and storage uses has established a standard, employs the above-described compression coding method. H. 261 and H.E. The H.263 Recommendation is based on ITU-T (International Telecommunication Uni
t) recommends that the MPEG2 recommendation be based on ISO / IEC1
3818-2.

[0003] In image coding such as MPEG2, in order to further reduce redundancy by utilizing temporal correlation, a difference between two screens (frames) that are temporally different from each other is encoded, or motion of an image is detected. To perform motion compensation. Therefore, the quantized signal is decoded into a signal before being subjected to the orthogonal transform (hereinafter, referred to as local decoding), and this is used as one of the two screens, and the reference image signal of the block to be newly encoded is used. Processing or a device for obtaining

The above-described local decoding process is performed in units of blocks. As described above, the blocks are divided into eight in both the vertical and horizontal directions.
It is composed of pixels. Further, since the input of the subtracter for obtaining the difference between two screens (frames) is 8 bits, the output is 9 bits.
Bit. Therefore, D for converting the output of the subtractor
In the CT processing, the number of input bits is 9 bits. DCT
In the processing, a 9-bit input and a coefficient are multiplied by a coefficient and the addition thereof is performed, so that the output requires 12 bits. This is quantized into 8-bit data. In the inverse quantization process for local decoding, the quantized 8-bit data is converted into 12 bits again, and the inverse DCT process becomes 9 bits. Further, the data is added to the 8-bit motion compensation data by an adder to obtain 8 bits of reproduced pixel data.

[0005]

As described above, the conventional image signal processing has a disadvantage that the input of the inverse DCT processing is as large as 12 bits and the circuit scale of the inverse DCT is increased. The DCT processing and the inverse DCT processing may be configured by hardware, but may be configured by software. Even in the case of software processing, calculations with a large dynamic range as in the past require a CPU or DSP.
However, there is a drawback that the processing speed is reduced in order to secure the internal calculation accuracy of the above.

A main object of the present invention is to realize a method and an apparatus for reducing the number of bits of input data in an inverse DCT process. Another object of the present invention is to provide a method for improving the processing speed of the inverse DCT processing of the local decoding unit and reducing the number of required processing bits of the inverse DCT processing unit without deteriorating the image quality in encoding the image signal. The realization of the device.

[0007]

In order to achieve the above object, an input image is divided into blocks each having a predetermined number of pixels, and an image signal of the block is orthogonally transformed with difference data between a reference block. , Further quantized and encoded, inversely quantized the quantized data, inversely orthogonally transformed the inversely quantized signal, and locally decoded using the inversely orthogonally transformed signal, see above. In the image encoding method for obtaining a block signal, the orthogonally transformed data is subtracted from the inversely quantized data, the result of the subtraction is inversely orthogonally transformed, and the inversely orthogonally transformed signal and the difference data are added. To obtain locally decoded data.

Further, in the image coding apparatus according to the present invention, the local decoding unit includes a subtractor for subtracting an input of the quantization unit from output data of the inverse quantization unit, and an output of the subtractor for inputting to an inverse orthogonal transform. An adder for adding the output of the inverse orthogonal transform unit to the input of the orthogonal transform unit or the image signal of the block to be encoded is provided.

According to the present invention, for the following reasons, the dynamic range of signal processing data for obtaining locally decoded data can be reduced, the number of processing bits can be reduced, and the processing speed can be improved. Generally, the input of the DCT process is x
Where DCT (x) is the DCT output. Here, DCT () is a DCT operator. DCT
When (x) is quantized and the result is inversely quantized, an error d occurs because the quantization / inverse quantization processing is irreversible. That is, the inverse quantization output is DCT (x) + d. When this is inverse DCT, IDCT (DCT (x)
+ D). Here, IDCT () is an inverse DCT operator. Since DCT / IDCT is a linear operation, IDT
CT (DCT (x) + d) = IDCT (DCT (x))
+ IDCT (d). DCT / IDCT is not generally a reversible operation. That is, IDCT (DCT
(X)) = x. This is because the DCT / IDCT operation is performed with a finite word length. Conventional processing and apparatuses generally perform highly accurate calculations in order to approach IDCT (DCT (x)) = x. As a result, the output of the inverse DCT is approximately x + IDCT (d).

On the other hand, in the present invention, since the input DCT (x) of the quantization operation is subtracted from the output DCT (x) + d of the inverse quantization, the resulting output is d. Since this is subjected to inverse DCT, the output obtained by performing inverse DCT processing is IDCT.
(D). When this is added to the input x of the DCT processing unit, x + IDCT (d) is obtained. The result is the same as described in the general case. As described above, in the present invention, since only the error value d by the quantization / inverse quantization processing is inverse DCT, the input dynamic range of the inverse DCT, that is, the required number of processing bits can be reduced.
The signal processing speed can be increased, and the circuit configuration scale of the arithmetic circuit can be reduced.

[0011]

<First Embodiment> FIG. 1 is a block diagram showing a configuration of a first embodiment of an image coding apparatus according to the present invention. This embodiment is an image encoding device that generates data encoded by MPEG2. In the figure, other parts of the local decoding unit 20 are the same as those conventionally known, but before the description of the present embodiment, the image encoding apparatus will be briefly described.

The reorder control unit 11 performs an operation (reorder) for rearranging the order of frames of image input described below,
Processing such as a pre-processing filter, down-sampling of a color signal, and division of one frame of an image into blocks of 16 pixels in each of the horizontal and vertical directions (referred to as macroblocks; hereinafter, abbreviated to MBs) are performed.

In MPEG2 encoding, an image is encoded in the order of a predetermined frame with reference to the preceding and succeeding frames. The case of predicting the current frame from a past frame is called forward prediction, the case of predicting the current frame from a future frame is called backward prediction, and the case of predicting the current frame from both past and future frames is called bidirectional prediction. Frames coded without using inter-frame prediction are intra frames (I frames), frames coded by forward prediction are forward predicted frames (P frames), and frames coded by bidirectional prediction are bidirectional prediction. It is called a frame (B frame). The prediction method in the P frame and the B frame is determined for each macro block.

That is, a macroblock in a P frame is an intra macroblock or a forward prediction macroblock without motion compensation, and a macroblock in a B frame is an intra macroblock, a forward prediction macroblock, a backward prediction macroblock, a bidirectional macroblock. It will be one of the predicted macroblocks. In order to encode a B-frame, the reference frames on either side must be encoded first. Therefore, the order of the frames to be encoded is different from the order of the frames of the input image. The operation of rearranging the frame order is called reordering.

As described above, the prediction method is determined for each macroblock. A macroblock with a P frame is
When encoding with reference to an I frame, a portion most similar to a certain macroblock in a P frame is searched from the I frame, and an error from the portion is encoded. At the same time, the moving amount is encoded as a motion vector. The above-described process of searching for the most similar part is called motion vector detection.
Executed in The operation of finally extracting the most similar part is called motion compensation, and the motion compensation unit 24 performs this operation. The difference between the macro block to be encoded and the most similar part (reference block) is calculated by the subtractor 12.

The output of the subtractor 12 is a DCT 13 which
Orthogonal transform by DCT is performed in units of pixels and blocks of eight horizontal pixels to generate DCT coefficients of spatial frequency components. The DCT coefficient is quantized by the quantizer 14. This operation divides the DCT coefficient by a predetermined coefficient to obtain the DCT coefficient.
Information is compressed by lowering the expression accuracy of the T coefficient. Next, the quantized signal is converted by the scan conversion unit 15 into a DCT signal.
The coefficients can be rearranged in order from low frequency to high frequency. The output of the scan converter is variable-length encoded by a variable-length encoder 16. A buffer control unit for controlling a normal bit stream output buffer is provided at the subsequent stage of the variable length coding unit 16, but is not shown in FIG.

The local decoding unit 20, which is a feature of the present invention, comprises:
An inverse quantizer 18 for inversely quantizing the output of the quantizer 14; a subtractor 22 for subtracting the output of the DCT unit 13 (ie, the input of the quantizer 14) from the output of the inverse quantizer 18;
2 is multiplied by a predetermined coefficient to the DCT coefficient,
13. An inverse DCT 19 and an inverse DCT unit 19 for reproducing the error of the real image from the coefficients of the spatial frequency component by the operation opposite to the operation of FIG.
, And an input of the DCT unit 13, and an adder 25 that adds the output of the adder 23 and the signal from the motion compensation unit 24 to generate a reproduced image. Adder 2
The output of 5 reproduces the image of the encoded macroblock. When the reproduced image data is used for encoding a subsequent frame, the reproduced image data is stored in the frame memory 26 or 27.
Is accumulated in

Reference numerals 26 and 27 denote a forward prediction frame memory and a backward prediction frame memory, respectively, for storing reference images, and reference numeral 28 denotes a motion vector detector for detecting the motion of an encoded frame with respect to the reference image.

In the case of encoding by MPEG2, the inverse quantization processing is ((2 × DCT (x) + k) × W × q-scal
e) / 32. Here, k is 0 or + /
-1, W is the coefficient of the quantization matrix, q-scale
Is a quantization coefficient determined in MB units. Since W is a maximum of 255 and q-scale is a maximum of 112, the inverse quantization processing is a multiplication of 1785 times at the maximum. The quantization process is an operation of dividing by a maximum of 1785. The output DCT (x) of the DCT unit 13 is represented by a code and an 11-bit numerical value, and the maximum value is +2047. When this is divided by 1785 as the maximum quantization processing, it is approximately +1.16, that is, 1 bit. Numeric. If this is multiplied by 1785 as the maximum inverse quantization processing, the output of the inverse quantizer 18 becomes +1
785 are obtained. The output of the subtracter 22 is 2047 and 1
Since the difference is 785, the difference is 262. Therefore, it becomes a 10-bit numerical value. Further, if a code is added, 11 bits are required. Thus, the input of the inverse DCT unit 19 has 11 bits. However, it is rarely necessary to perform such coarse quantization. This is because the image quality is extremely deteriorated. Normally, W is about 83 at the maximum and q-scal
Since e is about 32 at the maximum, the input of the inverse DCT unit 19 may be 8 bits if it is obtained in the same manner as the above calculation.
As described above, by limiting the W and the q-scale, the effect of reducing the dynamic range of the input of the inverse DCT unit 19 can be increased. This gives the inverse D
The circuit size of the CT unit is reduced.

Conventionally, IDCT (DCT (x))
= X, a highly accurate calculation was required. This processing means that the result of the DCT is directly subjected to IDCT, that is, when the quantization / inverse quantization processing is not performed, the value returns to the original value. In the present embodiment, this corresponds to the case of d = 0, which means IDCT (0) = 0. In the conventional processing, IDCT (D
Although it was difficult to obtain CT (x)) = x, it is easy to obtain the present embodiment IDCT (0) = 0.

Hereinafter, the inverse DCT unit 1 in this embodiment will be described.
The configuration and effect of No. 9 will be described in more detail. Two-dimensional inverse DC
T can be decomposed into a one-dimensional horizontal and vertical inverse DCT, as described in KRRao, P. Yip, Translated by Yasuda and Fujiwara, "Image Coding Techniques" (Ohm), page 126. An 8-point one-way DCT is represented as f (m) = 1 / 2Σ (ck) F (k) cos ((2m + 1) kπ / 16)). Here, k, m = 0, 1, 2, 3, 4,
5, 6, 7, where Σ is the sum of k from 0 to 7. F (k) is the coefficient of the inverse DCT, f (m) is the result of the inverse DCT operation, and c (k) is 1 / when k = 0.
(Square root of 2), and becomes 1 when k = 1, 2, 3, 4, 5, 6, 7. As can be seen from this equation, the inverse DCT is basically based on the input F (k) and the cosine coefficient cos ((2m +
1) The product-sum operation of kπ / 16), and the cosine coefficient is set to about 13 to 14 bits so as to obtain sufficient calculation accuracy (Peter A. Ruetz et al., “A High Performance Full-Mot”
ion Video Compression Chip Set] IEEE Transaction on
Circuits and Systems For Video Technology, 2nd
Vol. 2, No. 2, June 1992, p. 111).

FIG. 2 shows the configuration of the inverse DCT unit using a product-sum operation. Conventionally, since the DCT coefficient is 12 bits,
If the cosine coefficient from the coefficient ROM 30 is 13 bits, the multiplier 31 has 13 bits × 12 bits. Although the multiplier 31 has various configurations, a parallel multiplier will be described as an example. The parallel multiplier for two's complement is shown in FIG.
By four types of full adders (b), (c) and (d),
A conventional inverse DCT is configured as shown in FIG.
Author, "Computer Arithmetic", John and Sons 117
page). FIG. 3A is a full adder in the case where the three inputs X, Y, Z, the sum S, and the carry C are all positive numbers, and FIG.
Is a full adder when any two of the three inputs X, Y, and Z are positive numbers, one is a negative number, the sum S is a negative number, and the carry C is a positive number. One of the three inputs X, Y, and Z is a positive number, two are negative numbers, a full adder when the sum S is a positive number, and the carry C is a negative number, and FIG. This is a full adder when the inputs X, Y, Z, the sum S, and the carry C are all negative numbers. In FIG. 4, the cosine coefficients are a12, a11, a10, a9, a8, a7, a6, a
13-bit number of 5, a4, a3, a2, a1, a0, D
The CT coefficients are calculated as b11, b10, b9, b8, b7, b6.
It is a 12-bit number of b5, b4, b3, b2, b1, and b0. Also, for simplicity of the drawing, the input of the full adder is partially omitted for simplicity. It is clear when viewed in conjunction with the literature by Hwang. Thus, in the conventional case, 144 full adders were required as shown in FIG.

On the other hand, in the present embodiment, the DCT coefficient is 8 bits b7, b6, b5, b4, b3, b2, b
Since the cosine coefficient can be reduced to 13 bits a12, a11, a10, a9, a8, a7, a6,
Also for a5, a4, a3, a2, a1, a0, the multiplier has 13 × 8 bits, and the parallel multiplier can be composed of 96 full adders as shown in FIG.

In FIGS. 4 and 5, the carry must propagate from the upper right full adder to the lower left full adder in order to complete all the operations. In the conventional example of FIG. 4, there are 23 stages of propagation, but according to the embodiment of the present invention of FIG. 5, the propagation is reduced to 19 stages. As a result, the calculation speed is increased.

<Embodiment 2> FIG. 6 is a block diagram showing a configuration of a second embodiment of the image encoding apparatus according to the present invention. 1 are denoted by the same reference numerals as those in FIG.
Has functions. In the present embodiment, a mismatch control unit 21 is provided before the inverse DCT unit 19. In the inverse DCT unit 19, the obtained result is output within a predetermined number of bits.
You must round up or down numbers that are less than the specified number of bits. For a given input, the result of the operation is the boundary portion between rounding up and rounding down. The result is truncated in a certain finite precision operation and truncated in another finite precision operation, causing an error. Therefore, there is a method of avoiding an input that may be a calculation result at a boundary between rounding up and rounding down. This is called mismatch control, and the method is MPEG
2 recommendation. In this embodiment, the inverse DCT unit 1
9, a mismatch control unit 21 is provided.

<Embodiment 3> FIG. 7 is a block diagram showing the configuration of a third embodiment of the image encoding apparatus according to the present invention. 1 are denoted by the same reference numerals as those in FIG.
Has functions. In the present embodiment, the processing unit for the output of the inverse DCT unit 19 is different from the first and second embodiments. Figure 1,
Assuming that the input of the subtractor 12 in FIG. 7 is a and the output of the motion compensation 24 is b, the input of the DCT unit 13 is ab.
As described in the first embodiment, the output of the inverse DCT unit 19 is IDCT (d). In FIG. 1, the output of the adder 23 is a−b + IDCT (d), and the output of the adder 25 is a + IDCT (d). In the present embodiment, the adder 33 adds a to IDCT (d), and directly adds a + ID
Obtain CT (d). In this embodiment, the number of addition operations can be reduced as compared with the first embodiment.

In the above description of the embodiment of the present invention, the description has been made with reference to a block configuration diagram on the premise that the present invention is implemented by hardware. However, the present invention is not limited to the above embodiment, and processing by software is also possible. It goes without saying that it is possible. In software processing by a processor having no multiplier, multiplication is performed by repeating addition. The reduction of the number of input bits of the inverse DCT according to the present invention is as follows.
Since the number of additions is reduced, the number of steps can be reduced by that much, and the speed of signal processing can be increased.

Further, even in software processing by a processor having a multiplier, when the precision of a single precision operation is insufficient, a double precision operation for executing the single precision operation a plurality of times must be performed. In the double precision operation, a single precision operation is first performed on the lower bits, and the carry generated at this time is used in the upper bits operation. The double-precision operation requires multiplication of a multiplier, a lower multiplication of a multiplicand, multiplication of a lower multiplier and a higher multiplier, a multiplication of a higher multiplier and a lower multiplier, and a multiplication of a multiplier and a higher multiplicand. According to the method, the inverse DCT
The number of input bits can be reduced by reducing the number of double-precision operations in the middle of the inverse DCT operation, and improving the signal processing speed.

Although the DCT and the IDCT, and the quantizer and the inverse quantizer have been described as separate blocks, it goes without saying that these may be configured as a combined operation unit.

[0030]

The conventional image encoder has the disadvantage that the dynamic range of the input data of the inverse DCT is large and the logical configuration is large. It is also a disadvantage in terms of calculation speed. According to the present invention, the dynamic range of input data of the inverse DCT can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first embodiment of an image encoding device according to the present invention.

FIG. 2 is a block diagram showing a general configuration of an inverse DCT calculator;

FIG. 3 is an explanatory diagram of an adder used in the inverse DCT calculator of FIG. 2;

FIG. 4 is a configuration diagram of a multiplier required in a conventional configuration.

FIG. 5 is a configuration diagram of a multiplier used in an embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a second embodiment of the image encoding device according to the present invention.

FIG. 7 is a block diagram illustrating a configuration of a third embodiment of the image encoding device according to the present invention.

[Explanation of symbols]

11: reorder control unit, 12, 22: subtractor, 13: D
CT unit, 14: quantizer, 15: scan converter 16:
Variable length coding, 18: inverse quantizer, 19: inverse DCT unit,
20: local decoding unit, 21: mismatch control unit, 23, 2
5, 31, 33: adder, 24: motion compensator, 26: forward predicted frame memory, 27: backward predicted frame memory, 28: motion vector detector.

Claims (8)

[Claims] An input image is divided into blocks each having a predetermined number of pixels, and an image signal of the block and difference data of a reference block are orthogonally transformed, and further quantized and encoded. Dequantizes the quantized data,
In an image coding method for performing inverse orthogonal transform on an inversely quantized signal, performing local decoding using the inverse orthogonally transformed signal, and obtaining a signal of the reference block, the orthogonally transformed data from the inversely quantized data And performing a local decoding by performing an inverse orthogonal transform on a result of the subtraction and adding the signal subjected to the inverse orthogonal transform to the difference data. 2. The method according to claim 1, wherein the input image is divided into blocks each having a predetermined number of pixels, and an image signal of the block and difference data of a reference block are orthogonally transformed, and further quantized and encoded. Dequantizes the quantized data,
In an image coding method for performing inverse orthogonal transform on an inversely quantized signal, performing local decoding using the inverse orthogonally transformed signal, and obtaining a signal of the reference block, the orthogonally transformed data from the inversely quantized data And performing a local decoding by performing an inverse orthogonal transform on a result of the subtraction and adding the inversely orthogonal transformed signal and the image signal of the block. 3. The image encoding method according to claim 1, wherein an output of the inverse orthogonal transform with respect to 0 input is set to 0. 4. The image encoding method according to claim 1, wherein a quantization process is controlled so as not to exceed an input bit range of said inverse orthogonal transform. 5. A block division unit for dividing an input image into blocks each having a predetermined number of pixels, an orthogonal transformation unit for orthogonally transforming an image signal of the block, and a quantization unit for quantizing the orthogonally transformed data. A dequantizing unit for dequantizing the quantized data, and an inverse orthogonal transform unit for inversely orthogonally transforming the dequantized data, wherein the inverse quantization A subtractor for subtracting the input of the quantization unit from the output data of the unit; an adder for inputting the output of the subtractor to the inverse orthogonal transform and adding the output of the inverse orthogonal transform unit to the input of the orthogonal transform unit; An image encoding device characterized by the following. 6. A block division unit for dividing an input image into blocks each having a predetermined number of pixels, an orthogonal transformation unit for orthogonally transforming an image signal of the block, and a quantization unit for quantizing the orthogonally transformed data. A dequantizing unit for dequantizing the quantized data, and an inverse orthogonal transform unit for inversely orthogonally transforming the dequantized data, wherein the inverse quantization A subtractor for subtracting the input of the quantization unit from the output data of the unit, and an adder for inputting the output of the subtractor to the inverse orthogonal transform and adding the output of the inverse orthogonal transform unit to the output of the block division unit An image encoding device, comprising: 7. The image coding apparatus according to claim 4, wherein an output of the inverse orthogonal transform unit for 0 input is set to 0. 8. The image coding apparatus according to claim 5, further comprising a control unit for controlling the quantizer so as not to exceed an input bit range of the inverse orthogonal transformer. apparatus.