JPH11284673A - Fsk modulator and transmission device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an output which has a frequency range wider than a conventional range by simple circuit configuration. SOLUTION: This FSK(frequency shift keying) modulator is provided with a waveform-shaped data storage means 3 which is stored with waveform-shaped digital data for a digital input signal, a phase shift value storage means 4 which converts the digital data outputted from this waveform-shaped data storage means 3 to a phase shift value, a DSS7 which converts the phase shift value outputted from the phase shift value storage means 4 to the amplitude value of a digital sine wave, a D/A converting circuit 8 which converts the output of the DSS7 into an analog signal, and a timing circuit which outputs a readout clock for the wavefonn-shaped data storage means 3, a readout clock for the phase shift value storage means, and an operating clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency shift keying (FSK) modulator and a transmitter using the same.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional FSK modulator. In this FSK modulator, a digital input signal arrives at an input terminal 1 and is converted into two parallel signals by a serial / parallel (S / P) converter 10, and one side of the parallel signal is converted to a cosine (COS) signal. Sent to the ROM 11 and the parallel signal on the other side is converted to a sine (SIN) ROM 1
2 is sent. The cosine ROM 11 is a ROM in which data is stored so as to output a corresponding value of the cosine wave according to the value of the input digital signal. For example, each part of the cosine wave is gradually reduced with respect to a digital signal gradually decreasing from one. The output as plotted in is obtained. Also,
The sine ROM 12 is a ROM in which data is stored so as to output a corresponding value of a sine wave in accordance with a value of an input digital signal. The output as plotted in is obtained.

The output of the cosine ROM 11 is sent to a D / A converter 13 and the output of the sine ROM 12 is sent to a D / A converter 14 to be converted into an analog signal.
Further, the signals are transmitted to LPFs (low-pass filters) 15 and 16 in the analog baseband. The LPFs 15 and 16 remove the digital noise component generated by the D / A conversion and limit the band, and output the result to the quadrature modulator 17.

[0004] A quadrature modulator 17 receives a signal from an oscillator 18 for determining a carrier frequency, and converts the signal to 0 and π.
/ 2, a multiplier 17-2 for multiplying the obtained 0 by the output of the LPF 15, and a π / 2 obtained by the distributor 17-1 for the output of the LPF 16. A multiplier 17-3 and an adder 17-4 for adding the output of the multiplier 17-2 and the output of the multiplier 17-3 are provided. The output of the adder 17-4 reaches the output terminal 19 of the FSK modulator.

However, the above-mentioned FSK modulator uses the quadrature modulator 17, and the adder 1 of the quadrature modulator 17
In both inputs 7-4, there is a problem that the phases of the carrier components need to be exactly orthogonal, and high-performance components must be used for the distributor 17-1 and the like. Also, the LPFs 15 and 16 are required to have frequency characteristics free from overshoot and undershoot that cause overmodulation and to have equal delay times for both, but it is difficult to realize such Becomes more complicated,
There was also the problem of inviting higher prices.

[0006]

In order to solve these problems, an FKS modulator having a configuration as shown in FIG. 10 has been developed. That is, the input digital signal arriving at the input terminal 1 is parallelized by the S / P converter 20,
RO storing digital data corresponding to modulation waveform
The signal is sent to M21 to directly obtain digital data of a modulated wave. Then, a configuration is adopted in which the digital data is guided to the D / A converter 22 to be converted into an analog signal and output from the output terminal 26.

However, according to the above configuration, RO
The operating speed of M21 and the number of address pins of ROM 21 are limited, and the carrier frequency of the modulated wave obtained at the output of D / A converter 22 cannot be determined arbitrarily. There is a problem that switching between the FSK and the four-valued FSK requires ROM conversion and complicated adjustment and control.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional FSK modulator, and an object of the present invention is to obtain an output over a wider frequency range than the conventional one while having a simple circuit configuration. Is to provide an FSK modulator that is capable of: It is another object of the present invention to provide an FSK modulator that can easily cope with a change or switching of a frequency transition, an offset frequency, or the like. It is another object of the present invention to provide a transmission device using the FSK modulator.

[0009]

According to a first aspect of the present invention, there is provided an FSK modulator comprising: a waveform shaping data storage means for storing waveform-shaped digital data for a digital input signal; and a waveform shaping data storage means. Phase change value storage means for converting digital data output from the phase change value into a phase change value; a direct digital synthesizer for converting the phase change value output from the phase change value storage means into a digital sine wave amplitude value; This direct
A D / A conversion circuit for converting the output of the digital synthesizer into an analog signal; a timing circuit for outputting a read clock for the waveform shaping data storage means, a read clock for the phase change value storage means, and an operation clock for the direct digital synthesizer And Thus, waveform shaping is performed digitally, overshoot and undershoot can be prevented, and an appropriate digital sine wave can be obtained by a direct digital synthesizer.

In the FSK modulator according to the present invention, the direct digital synthesizer stores the phase change value output from the phase change value storage means as one of the system clocks.
It is characterized by comprising a phase adder that performs cumulative addition for each cycle, and a digital sine wave conversion circuit that converts instantaneous phase data output from the phase adder into a digital sine wave amplitude value. As a result, the phase change value is cumulatively added for each cycle of the system clock, and this phase data is converted into a digital sine wave amplitude value to obtain a digital sine wave.

The FSK modulator according to the present invention is characterized in that the waveform shaping data storage means, the phase change value storage means, and the digital sine wave conversion circuit are each constituted by a ROM. Thereby, appropriate data can be obtained by reading data from the ROM, and
Changes in data contents and the like can be handled by replacing the ROM as necessary.

In the FSK modulator according to a fourth aspect of the present invention, the timing circuit reads the waveform-shaping data from the waveform shaping data storage means using a clock having a period of 1/2 ⁿ (n is an integer) synchronized with the digital input signal. Features. Thereby, appropriate sampling is performed and waveform shaping is performed.

In the FSK modulator according to the present invention, an A / D converter for inputting an analog signal and digitizing the analog signal and an output of the A / D converter are stored in a waveform shaping data storage unit. A delay time compensating circuit for delaying to compensate for a difference between the processing time and a delay time compensating circuit for selecting one of the output of the delay time compensating circuit and the output of the waveform shaping data storage means and sending the output to the phase change value storage means. And a switching circuit. Thereby, it is possible to perform modulation on both the digital input signal and the analog input signal.

According to a sixth aspect of the present invention, in the FSK modulator, an offset frequency of a carrier frequency is associated with an input as a phase value in the phase change value storage means. As a result, an appropriate phase value to which the offset frequency has been added can be obtained.

According to a seventh aspect of the present invention, there is provided a transmitting apparatus, wherein a waveform-shaped data storage means for storing digital data obtained by shaping a waveform with respect to a digital input signal; Phase change value storage means, a direct digital synthesizer for converting the phase change value output from the phase change value storage means to a digital sine wave amplitude value, and an output of the direct digital synthesizer for analog conversion. An FSK modulator comprising: a D / A conversion circuit for converting a signal into a signal; and a timing circuit for outputting a read clock for the waveform shaping data storage means, a read clock for the phase change value storage means, and an operation clock of the direct digital synthesizer. And the output of this FSK modulator And up-converting unit for up-converting to, characterized by including the. As a result, waveform shaping is performed digitally, preventing overshoot and undershoot, obtaining an appropriate digital sine wave by a direct digital synthesizer, and transmitting a signal that is up-converted to a transmission frequency. it can.

According to another aspect of the present invention, there is provided a transmitting apparatus which stores waveform-shaped digital data for a digital input signal and stores the digital data output from the waveform-shaped data storage unit as a phase change value. Phase change value storage means, a direct digital synthesizer for converting the phase change value output from the phase change value storage means to a digital sine wave amplitude value, and an output of the direct digital synthesizer for analog conversion. A D / A conversion circuit for converting the signal into a signal, a read clock for the waveform shaping data storage means, a read clock for the phase change value storage means, a timing circuit for outputting an operation clock of the direct digital synthesizer, and an analog signal A which digitizes this analog signal A D converter, a delay time compensating circuit for delaying the output of the A / D converter to compensate for a difference between the processing time of the waveform shaping data storage means, and an output of the delay time compensating circuit or storing the waveform shaping data. A FSK modulator having a switching circuit for selecting any one of the outputs of the means and transmitting the selected signal to the phase change value storage means.
An up-conversion unit for up-converting the output of the K modulator to a transmission frequency.
As a result, a signal obtained by modulating either the digital input signal or the analog input signal can be up-converted to the transmission frequency and transmitted.

According to a ninth aspect of the present invention, in the transmission apparatus, the timing circuit is configured to supply a clock to the A / D converter and the delay time compensation circuit. This makes it possible to apply a clock to the input of the analog input signal using the same timing circuit as that for the digital input signal.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An FSK modulator and a transmitting apparatus according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In each drawing, the same components are denoted by the same reference numerals, and redundant description will be omitted. FIG. 1 shows an FSK modulator. This FSK modulator has an S / P converter 2,
Waveform shaping data ROM3, phase change value conversion ROM
4, a timing circuit 5, a DSS 7, and a D / A converter 8.

The S / P converter 2 converts a digital input signal (serial data composed of 1 and 0) coming from the input terminal 1 into two systems of serial data and sends it to the waveform shaping data ROM 3. Is what you do. The waveform shaping data ROM 3 stores output data corresponding to input data based on characteristics of a low-pass filter. The phase change value conversion ROM 4 includes a waveform shaping data ROM 3.
The phase change value Δφ necessary to obtain the target frequency corresponding to the data output from is stored.

The DSS 7 includes a phase adder 7-1 and a SIN-
A ROM (digital sine wave conversion circuit) 7-2 is provided. The timing circuit 5 includes an S / P converter 2, a waveform shaping data ROM 3, a phase change value converting ROM 4, a DSS 7,
To the operating clock. The timing circuit 5
The S / P converter 2 is supplied with a frequency clock higher than the speed of the digital input signal to perform sampling. Also, for the waveform shaping data ROM 3, 1/2 ⁿ (n is an integer) of the cycle synchronized with the digital input signal
The reading is performed by applying the system clock Fsys. This system clock Fsys is
The SIN-ROM 7 which is also supplied to the phase change value conversion ROM 4 and the DSS 7, reads the phase change value, and uses the data from the phase adder 7-1 as a sine wave conversion circuit.
-2. Next, the waveform shaping data ROM in the FSK modulator having the above configuration
3. The phase change value conversion ROM 4 will be described in detail.

As described above, the waveform shaping data ROM 3 stores data of low-pass filter characteristics for the purpose of preventing the occupied bandwidth from expanding for all the patterns of the input data. Specifically, in order to reflect the influence of the past data on the current data, for example, a k-stage shift register is arranged at the address port, and the 2-bit input data is sequentially shifted in synchronization with the read clock. To give a k-bit parallel address. For example, M-bit parallel data is stored so that data in which smooth waveform shaping and high-order components of the transmission data rate are suppressed can be read out. Here, when M is 8, 256 data of 00h to FFh can be read. For this reason, it is possible to prevent an increase in bandwidth due to a sudden change in the frequency of the FSK modulated wave. Then, a system clock Fsys of 1/2 ⁿ (n is an integer) of the cycle synchronized with the digital input signal is applied to the waveform shaping data ROM 3 to read data, so that a certain delay time is required. Having a filter.

On the other hand, the phase change value conversion ROM 4 converts the M-bit data transmitted from the waveform shaping data ROM 3 into a frequency shift of the FSK modulated wave, for example, M
When the bit data is all 0, the maximum frequency shift to the negative side (−Δfmax) is obtained. When the M-bit data is all 1, the maximum frequency shift to the positive side (+ Δfmax) is obtained.
) Are stored to obtain the phase change value (Δφ).
Here, assuming that the output frequency is Fout and the frequency of the system clock is Fsys, the phase change value Δφ is determined by Δφ = 2π × (Fout / Fsys).

The phase change value conversion ROM 4 has a configuration example in which an offset frequency of a carrier wave frequency is associated with an input as a phase value, in addition to storing the above phase change value. In such a case, set the offset frequency to foffs
Assuming that et is, for example, when all the M-bit data is 0, the maximum frequency shift to the negative side (−Δfmax + foffset)
And the phase change value (Δφ) is stored so as to obtain the maximum positive frequency shift (+ Δfmax + foffset) when all the M-bit data is 1. Also, RO
Depending on the storage capacity of M, a value corresponding to a plurality of types of offset frequencies is stored, or a value corresponding to each of offset and no offset is stored. Then, the M bits are extended to an address of M + m bits,
The storage data corresponding to any of the offset frequencies is selected by using the necessary upper several bits in the address.

FIG. 5 shows an example of the contents of the ROM 4 for phase change value conversion. That is, the maximum frequency deviation on the negative side (-Δfmax) and the maximum frequency deviation on the positive side (+ Δfmax)
) Is stored in correspondence with each value during (), indicating that each phase change value (Δφ) can be read. In FIG. 5, a phase change value of 5 degrees is added as an offset frequency.

The FSK modulator configured as described above has two
The operation when functioning as a value FSK modulator will be described.
The digital input data (signal) arrives at the input terminal 1 as A, B, C,... As shown in FIG. Here, A, B, C,... Are each 0 or 1. Next, the digital input data is distributed to two systems of data by the S / P converter 2, and in the case of binary FSK, for example, one of the data is A, B, C as shown in FIG. ,..., The other data is all 0s.

The data of the two systems as described above is sent to the waveform shaping data ROM 3, and the data of one time slot is converted into data of four blocks (each of 8 bits) by the address clocks of two kinds of frequencies. That is, the combination of the address clocks of two frequencies with respect to the data of one time slot is (0, 0), (1, 0), (0,
1) and (1, 1), one set of, for example, “one data” and “the other data” is (C, 0) in FIG. 2 corresponding to each combination of the address clocks. Is converted by the waveform shaping data ROM 3 into four blocks of data d0, d1, d2, and d3. At this time, (C, 0) is always given as an address to the waveform shaping data ROM 3, but actually, as described above, a k-bit address is stored in the waveform shaping data ROM 3 by a k-stage shift register. Given to. When the configuration in which k is 4 is adopted, the address is (C, 0, 0, 0) (C, 0, C,
0), (C, 0, C, 0) and (C, 0, C, 0). The output corresponding to each address is d0,
Since they are d1, d2, and d3, except for d0, d1, d2
, D3 are output values of the waveform shaping data ROM 3 corresponding to the same address, and have the same value.

The output of the waveform shaping data ROM 3 is output as an address of the phase change value converting ROM 4. As shown in FIG. 5, the phase change value conversion ROM 4 stores the phase corresponding to each value between the negative maximum frequency shift (−Δfmax) and the positive maximum frequency shift (+ Δfmax). the change value ([Delta] [phi) is stored, the input data _{d 0, d 1, d 2} , d 3 each phase change value [Delta] [phi ₀ stored in correspondence to, [Delta] [phi _1, [Delta] [phi _2, the [Delta] [phi ₃ read It is.

The output Δφ _{0 of} the phase change value conversion ROM 4,
Δφ ₁ , Δφ ₂ , and Δφ ₃ are provided to the phase adder 7-1. The output of the phase adder 7-1 is fed back to another input terminal, and cumulative addition is performed from 0 to 2π every clock of the system clock Fsys sent from the timing circuit 5. That is, initially, 0 is output from the phase adder 7-1 and Δφ _{0 is} read from the phase change value conversion ROM 4.
Is output and added in synchronization with the clock (0 + Δ
φ ₀ ) is output. Next, the ROM 4 for phase change value conversion
When [Delta] [phi ₁ is outputted from, summed in synchronization with a clock (Δφ ₀ + Δφ ₁₎ is output. Thereafter, addition is performed in the same manner, and the result is converted into a range from 0 to 2π.

The output of the phase adder 7-1 is SIN-RO
M7-2, the instantaneous phase data output from the phase adder 7-1 is converted into a digital sine wave amplitude value. That is, the SIN-ROM 7-2 is a ROM in which the values of the sine wave shown on the right side of FIG. 6 are associated with the respective phase values on the circle shown on the left side of FIG.
₁ , (Δφ ₀ + Δφ ₁ ), (Δφ ₀ + Δφ ₁ + Δ
In response to the input of φ ₂ ),..., the corresponding value (digital value) of the sine wave shown on the right side of FIG. 6 is output.
This digital data is sent to the D / A converter 8, and an analog-converted and FSK-modulated signal is output to the output terminal 9.

Next, using more specific input data,
The operation of the value FSK modulator will be described. For example, as shown in FIG. 3, one time slot of input data is T,
When data arrives at (0, 0, 1, 0,...), S
The / P converter 2 outputs the data (0,
, 0, 1, 0,...) Is output as it is, and all 0 data is output to the other of the output terminals. Waveform shaping data R
In the OM3, this is converted into parallel data by a four-stage shift register and given to the address terminal. Therefore, in the time slot T in which “one data” in FIG. 3 is 1, the address is (1, 0, 0, 0), (1,0,1,
0), (1,0,1,0), (1,0,1,0), and the first address of the next time slot T is (0,0,1,0).
0,1,0). Correspondingly, the output of the waveform shaping data ROM 3 is the “waveform shaped data” in FIG.
As shown in, the first address of the time slot T in which “one data” is 1 gives a certain value d ₀ , and the next address gives a full span value d ₁ (= FFh), for example. And in the next address assignment d
₁ equal d _2, further comprising a d ₁ equal d ₃ in the next addressing. Furthermore, the first address of the next time slot T corresponds to (0, 0, 1, 0), and the output at the time of the first address assignment of the time slot T in which “one data” is 1 a d ₀ equal value d _4. Thus, the waveform shaping data ROM 3 realizes a filter having a fixed delay time.

The output of the waveform shaping data ROM 3 obtained as described above shows that d ₋₁ , d ₀ , d ₁ , d ₁ near the time slot T where “one of the data” is “1”.
₂ , d ₃ , d ₄ , d ₅ ,..., Where the actual data value is between the data corresponding to the three levels as indicated by the height in “waveform-shaped data” in FIG. Change. Therefore, the phase change value conversion ROM 4 stores
The data corresponding to the two levels is used as an address, and the output is changed to φ ₋₁ , Δφ ₀ , Δφ ₁ , Δφ ₀ , φ ₋₁ in response to this. Here, in FIG.
_-1 , Δφ ₀ , Δφ ₁ , Δφ ₂ , Δφ ₃ , Δφ ₄ , Δφ ₅
However, Δφ ₂ and Δφ ₃ in FIG. 2 have the same value as Δφ _1, and Δφ ₀ and Δφ _{4 in} FIG. 2 have the same value,
For of phi _-1 and [Delta] [phi ₅ 2 is equal, in Fig. _{3, φ -1, Δφ 0,} Δφ 1, Δφ 0, represents the change in the phi _-1 substantial value.

In the DSS 7, a ROM 4 for phase change value conversion is used.
, The data of the amplitude value of the digital sine wave is output. The amplitude value is Δ Δ as described with reference to FIG.
φ ₁ , (Δφ ₀ + Δφ ₁ ), (Δφ ₀ + Δφ ₁ + Δ
In response to the input of φ ₂ ),..., the corresponding value (digital value) of the sine wave is obtained, but the output frequency does not change if the phase change values are equal. Therefore, in the example of FIG.
A substantial change Δφ ₋₁ of the output of the phase change value conversion ROM 4,
DSS7 corresponding to Δφ ₀ , Δφ ₁ , Δφ ₀ , Δφ _-1
Output frequency f ₁ , f ₀ , f ₁ , f ₀ , f _-1 . Here, if the frequency f _-1 represents data 0,
The frequency f ₁ represents data 1, and the frequency f ₀ is the frequency at the time of transition from data 1 to data 0 or at the time of transition from data 0 to data 1. Thus, the output of the binary FSK modulator is obtained.

Next, the FSK modulator shown in FIG.
The operation when functioning as a K modulator will be described. Digital input data (signal) arrives at the input terminal 1 as A, B, C,... As in the case of the binary FSK modulator in FIG. Here, A, B, C,... Are each 0 or 1. The S / P converter 2 receives this and distributes the digital input data into two systems of data. In the case of binary FSK, the other data is all 0,
In the case of quaternary FSK, quaternary values (that is, (0, 0), (1,
0), (0, 1), (1, 1)), for example, the signals A, B, C,.
Bit-by-bit parallel conversion is performed and output as a 2-bit parallel signal. Therefore, as shown in FIG. 4, the output of the S / P converter 2 is A, C, E ·
.., And the “other data” is B, D, F,.

The data of the two systems as described above is sent to the waveform shaping data ROM 3, and the data of one section is converted into eight blocks of data (each eight bits) by the address clocks of two different frequencies. That is, the combination of address clocks of two kinds of frequencies (0, 0), (1, 0), (0, 1), (1, 1) is
In FIG. 4, for example, 1 (C, D) corresponds to each combination of the address clocks.
D ₀ by delimiter data waveform shaping data _{ROM3 ', d 1', d} 2 ', d 3', d 4 ', d 5', d
₆ ', d _7' are 8 blocks of data called. Here, the binary FSK has four blocks of data, whereas the four-level FSK has eight blocks of data. In the case of binary FSK, the data is “0” and “1”. , While only frequency transition is performed between these two symbols (one round trip), in the case of quaternary FSK, data is (0, 0), (1, 0), (0, 1), (1 ,
This is because the frequency transition is made between any two of the four symbols, and a step is required for the frequency transition between symbols having different frequencies. The combination of “one data” and “the other data” is k
The shift register of the stage makes the address of k bits and gives it to the waveform shaping data ROM 3. If a configuration in which k is 4 is adopted, two address cycles are required until the address becomes stationary in one time slot of data. Therefore, 8 corresponding to one time slot of data
Data d ₀ ′, d ₁ ′, d ₂ ′, d ₃ ′ output from the waveform shaping data ROM 3 in the address cycle,
d ₄ ′, d ₅ ′, d ₆ ′, and d ₇ ′ have the same value except for d ₀ ′.

The output of the waveform shaping data ROM 3 is output as an address of the phase change value converting ROM 4. As shown in FIG. 5, the phase change value conversion ROM 4 stores the phase corresponding to each value between the negative maximum frequency shift (−Δfmax) and the positive maximum frequency shift (+ Δfmax). Since the change value (Δφ) is stored, the input data d ₀ ′, d ₁ ′, d ₂ ′, d ₃ ′, d ₄ ′, d ₅ ′,
Each of the phase change values Δφ ₀ ′, Δφ ₁ ′, Δφ ₂ ′, Δφ ₃ ′, Δφ ₄ ′ stored corresponding to d ₆ ′, d ₇ ′,
Δφ ₅ ′, Δφ ₆ ′, and Δφ ₇ ′ are read.

The output of the phase change value conversion ROM 4 is Δ
φ ₀ ', Δφ ₁ ', Δφ ₂ ', Δφ ₃ ', Δφ ₄ ', Δ
φ ₅ ′, Δφ ₆ ′, Δφ ₇ ′ are provided to the phase adder 7-1. The output of the phase adder 7-1 is fed back to another input terminal, and cumulative addition is performed from 0 to 2π every clock of the system clock Fsys sent from the timing circuit 5. That is, initially, the phase adder 7-1
Is output from the ROM 4 for phase change value conversion.
_{When 0} 'is output, it is added in synchronization with the clock (0
+ Δφ ₀ ′) is output. Next, R for phase change value conversion
When Δφ ₁ ′ is output from OM4, it is added in synchronization with the clock, and (Δφ ₀ ′ + Δφ ₁ ′) is output. Thereafter, addition is performed in the same manner, and the result is converted into a range from 0 to 2π.

The output of the phase adder 7-1 is SIN-RO
M7-2, the instantaneous phase data output from the phase adder 7-1 is converted into a digital sine wave amplitude value. That is, the SIN-ROM 7-2 is a ROM in which the values of the sine wave shown on the right side of FIG. 6 are associated with the respective phase values on the circle shown on the left side of FIG.
₁ ', (Δφ ₀ ' + Δφ ₁ '), (Δφ ₀ ' + Δφ ₁ '
+ Δφ ₂ '),..., A corresponding value (digital value) of a sine wave shown on the right side of FIG. 6 is output. This digital data is sent to the D / A converter 8, and an analog-converted and FSK-modulated signal is output to the output terminal 9.

Next, 4 for more specific input data
Consider the operation of a value FSK modulator. In the case of the binary FSK modulator, as shown in FIG. 3, only “one data” changes between “0” and “1”, but in the four-level FSK modulator, “the other data” also changes. It changes between “0” and “1”.
Therefore, the output of the waveform shaping data ROM 3 corresponds to the fact that the data is (0, 0), (1, 0), (0, 1), (1, 1), The transition is band-limited by the characteristics of the low-pass filter. For example, when the case of transition from (0, 0) to (1, 1) is shown, in this case, since the maximum transition (three stages) is made, basically, as in the waveform shown in FIG. The output of the digital low-pass filter for one pulse is obtained. In addition,
The transition from (0,0) to (0,1) is a one-stage transition, and the transition from (0,0) to (1,0) is a two-stage transition. The waveform shaping data is also stored in the waveform shaping data ROM 3.

The output of the phase change value conversion ROM 4 is represented by symbols (0, 0), (1, 0), (0, 1),
The four types of phase change values corresponding to (1, 1) and the phase change values at the time of transition between them. The output of DSS7 is
Symbols (0,0), (1,0), (0,1), (1,
There are four different frequencies (four values) corresponding to the four types of phase change values output from the phase change value conversion ROM 4 corresponding to 1), and the frequency at the time of transition between these four different frequencies. Thus, the output of the quaternary FSK modulator is obtained.

As described above, the FSK modulator according to the present embodiment is entirely constituted by a digital circuit except for the D / A converter 8, and does not require adjustment. In addition, when changing the filter characteristics, the modulation frequency, the frequency shift, and the offset frequency, it is not necessary to replace the analog parts.
This can be handled by changing the storage means such as the OM, and the characteristics can be easily changed.

Since the filter is constituted by the waveform shaping data ROM 3, overshoot / overshoot of the filtered waveform generated in the analog baseband LPF.
Undershoot can be prevented, and high-accuracy filter characteristics can be realized. The carrier frequency of the signal (modulated signal) output from the D / A converter 8 is determined by the phase change value output from the phase change value conversion ROM 4. The carrier frequency can be increased by increasing the speed of the system clock Fsys applied to the DSS 7 that generates the modulated signal using the phase change value. Further, by shortening the cycle of the data provided to the phase change value conversion ROM 4 (to increase the frequency), finer modulation is possible.

FIG. 7 shows an FSK modulator according to the second embodiment. In this embodiment, an analog input signal can be modulated in addition to the portion for modulating the digital input signal shown in FIG. In this modulator, an analog input signal arrives from an input terminal 23 and is sent to an A / D converter 24. A / D converter 24
In this case, digital data is sampled by a clock supplied to the waveform shaping data ROM 3, and the same clock as that described above is used as a shift clock by a delay time compensation circuit (DLY) 25 which is the same as a digital signal processing system. And is applied to one input terminal of a switching circuit (SEL) 26 for switching between digital and analog.

The output of the waveform shaping data ROM 3 is supplied to the other input terminal of the switching circuit (SEL) 26, and a delay time compensation circuit (DLY) is input by a switching control signal input from a control input terminal 27. 25 or the waveform shaping data ROM 3 is selected and sent to the phase change value converting ROM 4. Note that DSS7
The subsequent configuration is equivalent to the modulator of FIG. Control input terminal 27
Is generated based on the operation of a switch or the like for switching the transmission apparatus between the digital mode and the analog mode.

As a result of the configuration described above, it is possible to perform modulation on both analog signals and digital signals while using the main components of the modulator in common. This is realized by giving the same clock from the timing circuit 5 to both the digital system and the analog system, and keeping the delay times of both systems the same.

FIG. 8 shows a transmitting apparatus configured using the quaternary FSK modulator 10 according to the configuration of FIG. 4
From the modulated signal, which is the output signal of the value FSK modulator 40, a required band component is extracted by the band-pass filter 31 and sent to the multiplier 32. The multiplier 32 includes an oscillator 6
The output of the first oscillator 37 that oscillates the first frequency based on the above is supplied, and the required band component extracted by the band-pass filter 31 is up-converted. Further, the output of the multiplier 32 is sent to a band-pass filter 33, where a required band component is extracted.
The data is sent to the multiplier 34. An output of a second oscillator 38 that oscillates a second frequency based on the oscillator 6 is given to the multiplier 34, and a required band component extracted by the band-pass filter 33 is up-converted to a transmission frequency. .

The output of the multiplier 34 is amplified by an amplifier 35, an unnecessary component is removed by a low-pass filter 36, and sent out from an output terminal 39. A driver and an antenna are provided at the end of the output terminal 39, and transmission is performed.

According to the above transmitting apparatus, since the quaternary FSK modulator 40 is configured as shown in FIG. 7, it is possible to perform modulation on both analog signals and digital signals. Further, the carrier frequency of the signal (modulated signal) output from the D / A converter 8 can be further finely modulated by shortening the period of the signal applied to the phase change value conversion ROM 4 (increasing the frequency). Because it is possible, it has a feature that it is possible to obtain an output in a wider frequency range than in the past, with a simple circuit configuration. In this embodiment, the quaternary FSK modulator is used, but the transmitting device may be constituted by a binary or other FSK modulator. Further, the transmitting apparatus may be configured using an FSK modulator (for example, the configuration shown in FIG. 1) corresponding to only the digital input signal.

[0048]

According to the present invention, as described above, the F
According to the SK modulator, there are provided a waveform shaping data storage means for storing digital data obtained by shaping the waveform of a digital input signal, and a direct digital synthesizer for converting a phase change value into a digital sine wave amplitude value. Waveform shaping is performed digitally, overshoot and undershoot are prevented, and an appropriate digital sine wave can be obtained with a direct digital synthesizer.

As described above, the FS according to claim 2
According to the K modulator, the direct digital synthesizer accumulates and adds the phase change value for each cycle of the system clock, and this phase data is converted into the amplitude value of the digital sine wave. Is obtained.

As described above, the FS according to claim 3
According to the K modulator, since the waveform shaping data, the phase change value, and the digital sine wave are stored in the ROM, appropriate data can be obtained by reading the data from the ROM. The change can be handled by replacing the ROM as necessary.

As described above, the FS according to claim 4
According to the K modulator, the timing circuit reads out the waveform shaping data by a 1/2 ⁿ (n is an integer) clock synchronized with the digital input signal, so that appropriate sampling is performed and waveform shaping is performed.

As described above, the FS according to claim 5
According to the K modulator, an A / D converter for inputting an analog signal and digitizing the analog signal;
A delay time compensating circuit for delaying the output of the converter to compensate for a difference from the processing time by the waveform shaping data storage means;
A switching circuit for selecting either the output of the delay time compensating circuit or the output of the waveform shaping data storage means and sending it to the phase change value storage means. Can be modulated.

As described above, the FS according to claim 6
According to the K modulator, since the offset frequency of the carrier frequency is stored as the phase change value in association with the input, an appropriate phase value can be obtained by adding the offset frequency.

As described above, according to the transmitting apparatus of the seventh aspect, since the waveform shaping is performed digitally, overshoot and undershoot can be prevented, and a digital sine wave can be obtained by a direct digital synthesizer. Since the signal is transmitted after being up-converted to the transmission frequency, the transmission signal of the required carrier frequency can be appropriately transmitted.

As described above, according to the transmitting apparatus of the eighth aspect, since a digital input signal and an analog input signal can be selectively input, modulation is performed on any of these input signals. The signal can be up-converted to the transmission frequency and transmitted.

As described above, according to the transmission apparatus of the ninth aspect, a clock is applied to the input of an analog input signal using the same timing circuit as that of the digital input signal, so that the configuration is shared. It can be simplified.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an FSK modulator according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the binary FSK modulator according to the embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the binary FSK modulator according to the embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the quaternary FSK modulator according to the embodiment of the present invention.

FIG. 5 is a diagram for explaining an operation of conversion into a phase change value in the FSK modulator according to the embodiment of the present invention.

FIG. 6 is a diagram for explaining the operation of the sine wave ROM in the binary FSK modulator according to the embodiment of the present invention.

FIG. 7 is a configuration diagram of an FSK modulator according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of a transmission device according to an embodiment of the present invention.

FIG. 9 is a configuration diagram of a conventional FSK modulator.

FIG. 10 is a configuration diagram of a conventional FSK modulator.

[Explanation of symbols]

1, 23 input terminal 2 S / P converter 3 waveform shaping data ROM 4 phase change value conversion ROM 5 timing circuit 6 oscillator 7 DSS 7-1 phase adder 7-2 digital sine wave conversion circuit 8 D / A conversion Container 9 output terminal 24 A / D
Converter 25 Delay circuit 26 Switching circuit

Claims (9)

[Claims] 1. A waveform shaping data storage means storing waveform-shaped digital data for a digital input signal, and a phase change value storage means for converting digital data output from the waveform shaping data storage means into a phase change value. A direct digital synthesizer for converting the phase change value output from the phase change value storage means to a digital sine wave amplitude value; and a D / A converter for converting the output of the direct digital synthesizer to an analog signal. A read clock for the waveform shaping data storage means, a read clock for the phase change value storage means,
A FSK modulator comprising: a timing circuit that outputs an operation clock of a digital synthesizer. 2. A direct digital synthesizer comprising: a phase adder for cumulatively adding a phase change value output from a phase change value storage means for each cycle of a system clock; and an instantaneous phase data output from the phase adder. 2. The FSK modulator according to claim 1, further comprising: a digital sine wave conversion circuit that converts into a digital sine wave amplitude value. 3. A waveform shaping data storage means, a phase change value storage means, and a digital sine wave conversion circuit are each provided in a ROM.
3. The FSK modulator according to claim 2, comprising: 4. The timing circuit according to claim 2, wherein said waveform shaping data storage means stores a half of a cycle synchronized with the digital input signal.
The FS according to any one of claims 1 to 3, wherein reading is performed by ⁿ (n is an integer) clocks.
K modulator. 5. An A / D converter for inputting an analog signal and digitizing the analog signal, and using an output of the A / D converter to compensate for a difference between the processing time of the waveform shaping data storage means and the processing time. A delay time compensating circuit for delaying, and a switching circuit for selecting either the output of the delay time compensating circuit or the output of the waveform shaping data storage means and transmitting the selected output to the phase change value storage means. The FSK modulator according to any one of claims 1 to 4, wherein 6. The FSK modulator according to claim 1, wherein an offset frequency of a carrier frequency is associated with an input as a phase value in the phase change value storage means. . 7. A waveform shaping data storage means for storing waveform-shaped digital data for a digital input signal, and a phase change value storage means for converting digital data output from the waveform shaping data storage means to a phase change value. A direct digital synthesizer for converting the phase change value output from the phase change value storage means to a digital sine wave amplitude value, and a D / A converter for converting the output of the direct digital synthesizer to an analog signal A FSK modulator comprising a circuit, a read clock for the waveform shaping data storage means, a read clock for the phase change value storage means, and a timing circuit for outputting an operation clock of the direct digital synthesizer; and an output of the FSK modulator. Upconvert to the transmission frequency Transmitting apparatus characterized by comprising a Ppukonbato unit. 8. A waveform shaping data storage means for storing waveform-shaped digital data for a digital input signal, and a phase change value storage means for converting digital data output from the waveform shaping data storage means to a phase change value. A direct digital synthesizer for converting the phase change value output from the phase change value storage means to a digital sine wave amplitude value, and a D / A converter for converting the output of the direct digital synthesizer to an analog signal Circuit, a read clock for the waveform shaping data storage means, a read clock for the phase change value storage means, a timing circuit for outputting an operation clock of the direct digital synthesizer, and an A for inputting an analog signal and digitizing the analog signal / D converter and this A / D converter Delay time compensation circuit for delaying the output of the device to compensate for the difference from the processing time by the waveform shaping data storage means, and selecting either the output of the delay time compensation circuit or the output of the waveform shaping data storage means. A transmission apparatus comprising: an FSK modulator including a switching circuit for transmitting the FSK modulator to a phase change value storage unit; and an up-conversion unit configured to up-convert an output of the FSK modulator to a transmission frequency. 9. The transmission apparatus according to claim 8, wherein the timing circuit is configured to supply a clock to the A / D converter and the delay time compensation circuit.