JPH11282896A - Method, device for coping with timing margin error and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an efficient method for coping with a timing margin error of a semiconductor integrated circuit in which the number of processes is reduced. SOLUTION: An error list consisting of kinds of error and a checking result for plural conditions related to the cause of the error is generated, a problem is extracted by sorting the conditions of the error based on the error list, each stage to decide a method for correcting the error is simultaneously included in the method for coping with the timing margin error in the semiconductor integrated circuit and the method for correcting the error is sorted into net list correction, layout correction and logic collection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for analyzing a semiconductor integrated circuit, and more particularly to a method for dealing with a timing margin error in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, in a highly integrated large-scale semiconductor integrated circuit, a timing verification by a static timing analyzer is performed as a design period is shortened. Conventionally, the method of dealing with timing margin errors by using a static timing analyzer mainly corrects the netlist (information on the connection between circuit elements and circuits), and all errors are taken into account even if the wiring length is not considered in the layout. It was possible to deal with. That is, in a conventional semiconductor integrated circuit,
If the delay and the driving capability of the element were checked, it was possible to control the overall timing.

[0003]

However, as a result of the large-scale and high-integration semiconductor integrated circuits, fine wiring has become possible. As a result, the ratio of the wiring delay to the total delay amount has become larger than the element delay. It is difficult to control overall timing. In addition, even after the circuit design is completed, analysis work of the circuit design may need to be performed again after the layout, and there is a problem that the total number of steps of the system construction increases.

FIG. 13 is a diagram showing an example of a conventional countermeasure for timing error margin. As shown in FIG. 13A, the circuits to be analyzed include flip-flops FF1 and FF2, user logic 200, and AND circuit 20.
1 is included. In this circuit, first, FIG.
Suppose that a setup time error exists on the path A and a hold time error exists on the path B, as shown in FIG.

First, it is determined whether or not a period obtained by subtracting a setup time from a clock cycle (hereinafter referred to as a required value) is as set, that is, whether or not the clock is normally and uniformly supplied. As a result, the required value is assumed to be appropriate. Next, as shown in FIG. 13B, the hold time error of the path B is eliminated by inserting the buffer 202. However, path A setup time errors still exist.

Next, a path analysis is performed to examine the influence of the wiring length from the wiring delay and the element delay. As a result, it is assumed that the wiring delay is small and there is no influence of the wiring length. Next, FIG.
As shown in (C), a cell swap of the user logic 200 is performed. The cell swap is to replace elements constituting a circuit, and generally, it is possible to eliminate a setup time error by increasing the driving capability of the elements. As shown in FIG. 13C, it is assumed that the setup time error in this case has not been eliminated by the cell swap.

Next, as shown in FIG. 13D, the setup time error of the path A is eliminated by moving the buffer 202 to the path B. Even after the movement of the buffer 202, the hold time error of the path B is eliminated. As shown in this example, in the conventional path margin error handling method, since the user attempts to resolve the error by judging the situation one by one and taking appropriate measures, the number of processing steps is large and time is increased. This is also inefficient. In addition, if the process is wrong, the error may not be eliminated.

FIG. 14 is a diagram showing another example of a conventional countermeasure for a timing error margin. As shown in FIG. 14A, the circuit to be analyzed is a flip-flop FF1
And FF2, and user logic 200.
In this circuit, it is assumed that a setup time error exists in path A as shown in FIG.

First, it is determined whether or not the required value is as set, that is, whether or not the clock is normally and uniformly supplied. As a result, the required value is assumed to be appropriate. Next, a path analysis is performed to examine the influence of the wiring length from the wiring delay and the element delay. However, in this case, the wiring delay is small, and there is no influence of the wiring length. However, it is assumed that as a result of the path analysis, the number of circuit element stages is abnormally large, and that this path is a path in which one-bit adders are continuous. Generally, a path in which adders are continuous has a large delay and often causes a setup time error.

Next, as shown in FIG. 14B, a cell swap of the user logic 200 is performed. However, it is assumed that the setup time error of the path A in this case has not been eliminated by the cell swap. next,
By performing layout analysis, it is determined whether the number of branches is large. In general, when the branch of the wiring is large, the driving force of the element tends to decrease and the signal delay tends to increase. However, in this case, it is assumed that the number of branches is not large.

Next, as shown in FIG. 14C, a logic analysis is performed, and the user logic 200 is displayed on the netlist.
Is logically compressed. That is, the circuit configuration is simplified as much as possible so that the number of circuit elements becomes smaller. However, it is assumed that the setup time error of the path A has not been eliminated by this. Next, as shown in FIG. 13D, the RTL of the user logic 200 is corrected and re-synthesized, and the circuit is laid out again. Here, the RTL is an expression of a circuit at a logical level, and specifically corresponds to a logical expression. That is, in this case, the circuit designer corrects the RTL, redesigns it as a more efficient logical configuration, and lays out the circuit again. As a result, the setup time error of the path A is eliminated.

Similar to the example of FIG. 13, in the example of FIG. 14, since the user tries to eliminate the error by judging the situation one by one and taking appropriate measures, the number of processing steps is large and time is increased. This is also inefficient. In addition, if the process is wrong, the error may not be eliminated. Further, in the example of FIG. 14, after laying out the circuit once, the circuit designer analyzes and corrects the circuit design again.

As described above, in the conventional method for dealing with the timing margin error, a problem of the circuit is finally derived after many steps, so that the number of steps is large and it takes time. In addition, various tools are used in each process, and judgment errors easily occur. In addition, the effect could not be obtained by taking measures before the final problem judgment was reached, or the effect was achieved by taking two kinds of measures. There is a high possibility that useless work such as was performed is included, and the efficiency of the entire work is low.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for efficiently coping with a timing margin error of a semiconductor integrated circuit in which the number of steps is reduced.

[0015]

According to the first aspect of the present invention, a method for dealing with a timing margin error in a semiconductor integrated circuit includes a) a type of an error and a check result for a plurality of conditions relating to the cause of the error. Generating an error list, and b) classifying the status of the error based on the error list to extract a problem and determine an error correction method, wherein the error correction method includes a netlist correction and a layout. It is characterized in that it is classified into correction and logical correction.

According to a second aspect of the present invention, in the method for dealing with a timing margin error according to the first aspect, the step a) checks whether a path in which the error has occurred is a hold time error or a setup time error, The method includes the steps of checking whether the required value is appropriate, checking whether the required value is affected by the wiring length, and checking whether the number of stages is abnormally large.

According to the third aspect of the present invention, in the timing margin error handling method according to the second aspect, the step of checking whether or not the number of stages is abnormally large includes determining whether or not 1-bit adders are continuous. The method further comprises the step of checking. In the invention of claim 4,
3. The method according to claim 2, wherein the step (b) further comprises: b1) further checking a plurality of analysis items related to the cause of the error according to the classification result of the error situation; The method may further include each step of determining at least one of the correction methods based on a check result of the plurality of analysis items.

According to a fifth aspect of the present invention, in the method for dealing with a timing margin error according to the fourth aspect, the step b1) determines whether or not the driving capability is appropriate according to the classification result of the error situation. Checking whether there is a routing of wiring, checking whether there is a logical branch, and checking whether the wiring is connected to the vine vine type. .

According to a sixth aspect of the present invention, there is provided a machine-readable storage medium storing a program for causing a computer to deal with a timing margin error in a semiconductor integrated circuit, wherein a plurality of types of errors and a plurality of causes related to the cause of the error are provided. Error list generating means for generating an error list including a check result for a condition; and extracting a problem by classifying the status of the error based on the error list and performing netlist correction, layout correction, and logic correction. An error correction method determining means for determining the classified error correction method is included.

According to a seventh aspect of the present invention, in the machine readable recording medium according to the sixth aspect, the error list generating means checks whether a path in which the error has occurred is a hold time error or a setup time error. Means for checking whether the required value is appropriate, means for checking whether or not the wiring length is affected, and means for checking whether the number of steps is abnormally large. It is characterized by.

In the invention according to claim 8, in the machine-readable recording medium according to claim 7, the means for checking whether or not the number of stages is abnormally large is whether or not 1-bit adders are continuous. Is further included. According to a ninth aspect of the present invention, in the machine readable recording medium according to the seventh aspect, the error correction method determining means includes a plurality of analysis items related to a cause of the error in accordance with a classification result of the error situation. And a means for determining at least one of the correction methods based on a check result of the plurality of analysis items.

According to a tenth aspect of the present invention, in the machine readable recording medium according to the ninth aspect, the analysis item checking means determines whether or not the driving capability is appropriate according to the classification result of the error situation. Means for checking whether or not there is routing of wiring, means for checking whether or not there is a logical branch, and means for checking whether or not wiring is connected to a potato vine. It is characterized by including.

According to the eleventh aspect of the present invention, an apparatus for coping with a timing margin error in a semiconductor integrated circuit generates an error list including a type of an error and a result of checking a plurality of conditions related to the cause of the error. Error list generating means, and an error correction method for classifying the status of the error based on the error list to extract a problem and determine an error correction method classified into netlist correction, layout correction, and logic correction It is characterized by including decision means.

In the twelfth aspect, the eleventh aspect is provided.
The apparatus according to claim 1, wherein the error list generation unit checks a hold time error or a setup time error for the path in which the error has occurred,
means for checking whether the quired value is appropriate, means for checking whether the value is affected by the wiring length,
It is characterized by including means for checking whether or not the number of stages is abnormally large.

According to the thirteenth aspect, in the twelfth aspect,
In the above-described apparatus, the means for checking whether or not the number of stages is abnormally large further includes means for checking whether or not 1-bit adders are continuous.
According to a fourteenth aspect of the present invention, in the device according to the twelfth aspect, the error correction method determining means performs a further check on a plurality of analysis items related to the cause of the error in accordance with the classification result of the error situation. An analysis item check unit to be performed and a unit that determines at least one of the correction methods based on a check result of the plurality of analysis items are further included.

According to the fifteenth aspect, in the fourteenth aspect,
In the apparatus described above, the analysis item checking means checks whether or not the driving capability is appropriate according to the classification result of the error status, and checks whether or not there is wiring routing. And a means for checking whether or not there is a logical branch, and a means for checking whether or not the wiring is connected to the vines.

In the above invention, an error list including check results for a plurality of conditions that may be related to the cause of the error is obtained, and the situation is classified based on the error list, thereby solving the problem of the circuit. It can be clearly shown. Therefore, it is possible to present the problem of the circuit based on the detailed analysis even in the part where the feeling has been conventionally relied on.

Since the correction method is indicated as the error elimination information along with the presentation of the problem, the error can be surely eliminated and unnecessary work can be avoided. Further, a problem in circuit design and a problem in layout are clearly distinguished, and it is clearly shown whether any of netlist correction, layout correction or logic correction is necessary. Therefore, the work sharing between the circuit designer and the layout designer can be reliably distinguished, and the work process of the entire system can be greatly reduced.

[0029]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a flowchart showing a timing margin error handling method according to the present invention. In step S1, a timing margin check is performed.

In step S2, it is checked whether a timing margin error exists. If there is no error, the timing adjustment ends. If an error exists, the process proceeds to step S3. In step S3, an error list is output. As will be described in detail later, the error list includes check results for a plurality of conditions related to the cause of the error and information on the type of the error.

In step S4, problems are extracted by classifying the situation based on the error list. As a result, error elimination information indicating how to resolve the timing margin error can be obtained. In step S5, it is determined whether or not further analysis is necessary to resolve the error. If further analysis is required, the process proceeds to step S6. If unnecessary, the process proceeds to step S7.

In step S6, a more detailed analysis is performed to obtain more detailed error elimination information for eliminating the timing margin error. In step S7, a netlist correction, a layout correction, or an RTL correction is performed according to the obtained error elimination information to eliminate a timing margin error.

According to the timing margin error handling method of the present invention shown in FIG. 1, a check result is obtained for a plurality of conditions that may be related to an error cause from an error list, and a situation is classified based on the check result. By doing so, the problem of the circuit can be clearly shown. Therefore, it is possible to present the problem of the circuit based on the detailed analysis even in the part where the feeling has been conventionally relied on. In addition, since the correction method is indicated as the error elimination information along with the presentation of the problem, the error can be surely eliminated, and unnecessary work can be avoided. In addition, the problem in circuit design and the problem in layout are clearly distinguished, and it is clearly shown whether the netlist correction, the layout correction, or the RTL correction is necessary. Therefore, the work sharing between the circuit designer and the layout designer can be reliably distinguished, and the work process of the entire system can be greatly reduced.

As will be described later, the timing margin error handling method shown in the flowchart of FIG.
Basically, each step can be executed automatically.
That is, the creation of the error list, the extraction of the problem, and the detailed analysis are automatically executed. Regarding the correction work, except for the case where the RTL correction which is a part of the step S37 is complicated, the basic operation is performed. The circuit can be automatically corrected automatically.

Hereinafter, a method for dealing with a timing margin error according to the present invention will be described in detail. FIG. 2 is a diagram showing conditions to be checked when creating an error list and types of errors. For the path that generated the error, by checking the four classification items shown in FIG. 2, for example, “classification item 1: B, classification item 2: B, classification item 3:
An error list, which is a list indicating the classification result for each classification item, such as "B, classification item 4: A", is obtained.
Problems are extracted by classifying the situation based on the classification results for these four classification items.

FIG. 3 shows a diagram for extracting a problem based on the error list (classification result for the classification item) obtained in FIG. FIG. 3 is a table in which error occurrence situations are classified according to the classification results for the four classification items. Using this table, according to the obtained error list, that is, according to the classification results for the four classification items, what kind of problem is caused by the current error situation, and what is the corrective method to solve the problem? Can be known.

For example, as in the above example, "Classification item 1:
B, classification item 2: B, classification item 3: B, classification item 4:
In the case of "A", it can be understood that "there is a problem in logic design or synthesis" as a problem of the circuit. It also indicates that “RTL correction & resynthesis” needs to be executed as a correction method. As for a specific correction method in this case, information indicating a specific required correction operation is registered under a registered name of correction C-1. Similarly, for each correction method, necessary correction work is registered under a registered name such as correction A-2, A-3, or B-3.

Referring again to FIG. 2, in classification item 1, when an error occurs in a certain path, it is determined whether the error is a hold error, a setup error, or both a hold error and a setup error. judge. In FIG. 2, in the case of a path, a path having a common endpoint is treated as one path. That is, for example, in the example as shown in FIG.
And path B have the same end point (D input of flip-flop FF2), so these paths are collectively treated as one path. Therefore, in the example of FIG. 13, since the hold error and the setup error occur in the common path, the check result of the classification item 1 is C.

For classification item 2, it is determined whether the required value is appropriate. FIG. 4 is a diagram illustrating a required value. As shown in FIG. 4A, the circuit includes flip-flops FF1 and FF2, user logic 10,
It is assumed that an AND circuit 11 and a delay element 12 are included. Due to the delay element 12, the clock signal FF1-CK input to the flip-flop FF1 and the flip-flop FF2
As shown in FIG. 4B, there is a skew (timing shift) between the clock signal FF1 and the clock signal FF1-CK.

In FIG. 4B, A is a hold time of an endpoint cell (a cell at an end point, ie, a circuit element), B is a setup time of the endpoint cell, C is a clock skew, and D is an operating frequency.
The required value in the presence of a skew is defined as C + DB in FIG. 4B for the setup time, and FIG. 4B for the hold time.
Is defined as (-A) -C. Ie requir
The ed value is {operation clock cycle−end point cell setup time} for the setup time. The hold time is the hold time of the endpoint cell itself.

Required path indicating a setup error
If the value is within the range of the average clock skew between the last flip-flop of each circuit before and after the normal required value defined above, the required value is considered to be an appropriate path . If outside this range, requ
The ired value is an inappropriate path. If the required value of the path indicating a hold error is within the range of the average clock skew between the last flip-flops of each circuit before and after the normal required value defined above, the required value Is an appropriate path. If it is out of this range, the required value is an inappropriate path.

In the classification item 3, it is determined whether or not the path indicating the error is affected by the wiring length. Specifically, in each stage of the path where an error exists, first, the delay of the wiring and the delay of the cell connected to the wiring are extracted.
Next, for a pair of a certain wiring and a cell connected to the wiring, those having a relation of {wiring delay> cell delay} are extracted. Finally, an error path including the path from which the pair having the above relationship is extracted is detected, and the detected path is determined as a path affected by the wiring length.

In the classification item 4, it is determined whether the path indicating the error is a path having an abnormally large number of stages, a path in which 1-bit adders are continuous, or another path. Specifically, first, the number of stages from the start point to the end point of the error path is detected. The number of stages detected here is ｛(device operation cycle)
/ (Delay of 2-input NAND cell of device × maximum Dma
g value) ｇ, the path is determined to be an abnormally large number of steps. Here, the Dmag value is a ratio with respect to the normal value when the temperature and voltage conditions in the specification are the worst. Also, between the start point and the end point of the error path, a 1-bit adder
If the maximum number of bit adders is -1｝ or more,
It is determined that the 1-bit adder is a continuous path.

Referring again to FIG. 3, depending on the classification result of the error list, there is a case where an analysis step is further required. For example, when the classification items 1 to 4 are B, A, A, and B, it can be seen that there is a problem in the arrangement / wiring as a problem. When there is a problem in the arrangement / wiring, a more detailed analysis process is performed. FIG. 5 is a diagram showing four analysis items to be checked in the analysis process.

By checking the four analysis items shown in FIG. 5 for the path in which the error has been generated, for example, “analysis item 1: B, analysis item 2: B, analysis item 3:
A, analysis item 4: B ", a list showing analysis results for each analysis item is obtained. By classifying the situation based on the analysis results for these four analysis items, a detailed correction method can be obtained.

In the analysis item 1, when the fan-out of the element is larger than 100%, it is determined that the driving capability of the element is not appropriate. In the analysis item 2, first, the actual wiring length and the Manhattan length of a certain wiring are obtained. FIG.
FIG. 3 is a diagram showing an actual wiring length and a Manhattan length. FIG.
, The cell 20 and the cell 21 are connected by wiring. The actual wiring length indicates the actual wiring length, and the Manhattan length is the sum of the vertical and horizontal distances between two points to be connected. That is, in the example of FIG. 6, the actual wiring length is l1 + l2.
+ L3 + l4 + l5, and the Manhattan length is L1 + L
2. When the actual wiring length / Manhattan length is greater than 1.5, it is determined that there is wiring routing.

In the analysis item 3, when the number of wiring branches is one or more, it is determined that a logical branch exists. In the analysis item 4, it is determined whether or not the wiring is connected to the potato vine type. FIG. 7A shows a case where the wiring is connected to a vine-vine type, and FIG. 7B shows a case where the wiring is not a vine-vine type.

The determination as to whether or not it is the potato vine type is made based on the difference between the maximum value and the minimum value of the signal skew (timing shift) at the branch destination. That is, in the example of FIGS. 7A and 7B, the skew that the signal from the cell 22 has at the input positions of the cells 23, 24, and 25 is determined, and the largest skew is obtained. Calculate the difference between and the smallest one. When the difference between the maximum value and the minimum value is 1.5 ns or more, it is determined that the wiring is connected to the potato vine type.

FIG. 8 is a diagram showing a classification table for classifying a situation and obtaining a correction method based on a check result for an analysis item. Based on the classification table, it is possible to know what correction method corresponds to the situation where an error is currently occurring, according to the analysis results for the above four analysis items. For example, in the case of “analysis item 1: B, analysis item 2: B, analysis item 3: A, analysis item 4: B”, it is necessary to “reduce the number of error bus branches” as a correction method. Is shown. As for a specific correction method in this case, information indicating a specific required correction work is registered under a registered name of correction A-4. Similarly, for each correction method, necessary correction work is registered under a registered name such as correction A-1, A-4, or B-1.

The specific contents of each correction method will be described below. The correction methods A-1 to A-4 relate to the correction of the netlist. The correction method A-1 has a fan-out of 1
By performing cell swap so as to be 00% or less, an appropriate driving capability is realized. . The correction method A-2 is for a case where there is a problem such as a short wiring or a too close arrangement, and a buffer is inserted immediately before a designated cell. The cell immediately after this buffer insertion point is specified as follows.

FIGS. 9A and 9B are diagrams for explaining a method of specifying a cell at the time of buffer insertion. The circuits to be analyzed include user logics 31 and 32, cells 33 and 34, and flip-flops FF1, FF2, and FF.
4 inclusive. 9A and 9B, it is assumed that the path A has a setup error, the bus B has a hold error, and the paths C and D have no errors. In FIG. 9A, SP
Is the start point of paths A and B, and EP is the end point of paths A and B. Here, if a buffer is inserted at a point INS immediately before the end point EP in order to avoid a hold error on the path B, the setup error on the path A will be degraded.

Therefore, if there is an error with the same end point, the input to the cell one stage before the end point is set as a new end point. FIG. 9 (B)
In, the input to the cell 33 becomes new endpoints EP1 and EP2. The end point EP1 is an end point of the path A, and the end point EP2 is an end point of the path B. In this case, if a buffer is inserted at the point INS immediately before the end point EP2, the hold error of the path B can be avoided without affecting the path A.

As described above, when there is an error with the same endpoint, the immediately preceding cell is registered as the cell of the endpoint. If this operation is repeated by the end point until the same error disappears, the cell immediately after the buffer insertion point will be specified. The correction method A-3 is a case where there is a problem in the logic design or synthesis, and corrects the logic so as to reduce the number of stages.

The modification method A-4 is modified so as to reduce the number of branches. FIGS. 10A and 10B are diagrams showing a method of reducing the number of branches. As shown here, when considering the path from the buffer 41 to the buffer 42, the number of branches of the target path can be reduced by driving the added buffer 43 except for the target path.

The correction methods B-1 to B-4 relate to layout correction. In the correction method B-1, the wiring is redrawn so that the actual wiring length / Manhattan length> 1.2.
In the correction method B-2, as shown in FIG. 7A, the wiring connected in a vine-like manner is once deleted, and the wiring is redrawn in the same manner as the wiring of the clock signal.

The correction method B-3 is for the case where there is a problem in the clock design, and adjusts the skew at each stage of the clock wiring so as to be 100 ps or less. In each stage of the clock wiring, the delay is adjusted so as to be 100 ps or less. In the modification method B-4, for example, when the cell 1, the cell 2, and the cell 3 are connected in series, the arrangement is moved so that the wiring before and after the cell 2 is even and shortest. Specifically, for example, the coordinates of cell 2 are ({X1 + X3} / 2, {Y1 + Y3} / 2) with respect to the coordinates (X1, Y1) of cell 1 and the coordinates (X3, Y3) of cell 3. I just need.

The correction method C-1 relates to RTL correction and resynthesis. If there is a problem in logic design or synthesis, and particularly when 1-bit adders are continuous for a predetermined number of stages or more, they are replaced with adders that collectively calculate these. FIGS. 11A and 11B are diagrams showing a method of replacing a continuous 1-bit adder with another adder.

As shown in FIG. 11A, consider a circuit in which 1-bit adders 51 to 54 are successively added and bits A1 to A4 are added. In this circuit, FIG.
As shown in (B), by replacing the adder 55 with one 4-bit adder 55, the problem of an abnormally large number of stages can be avoided. In this manner, the timing margin error handling method of the present invention obtains check results for a plurality of conditions that may be related to an error cause from the error list, and classifies the situation based on the check results. The problem of the circuit can be clearly shown. Therefore, it is possible to present the problem of the circuit based on the detailed analysis even in the part where the feeling has been conventionally relied on. In addition, since the correction method is indicated as the error elimination information along with the presentation of the problem, the error can be surely eliminated, and unnecessary work can be avoided. In addition, the problem in circuit design and the problem in layout are clearly distinguished, and it is clearly shown whether the netlist correction, the layout correction, or the RTL correction is necessary. Therefore, the work sharing between the circuit designer and the layout designer can be reliably distinguished, and the work process of the entire system can be greatly reduced.

In the timing margin error handling method of the present invention, a check method is established for the classification item and the analysis item, so that each item can be automatically checked by software. The classification of the situation based on the check result can be automatically performed based on the classification table. That is, creating an error list,
The problem extraction and the detailed analysis are automatically performed, and the circuit can be automatically corrected basically, except for the case where the RTL correction is complicated.

FIG. 12 is a diagram showing a configuration example of a system for realizing the present invention. 12 includes a computer 111, a display device 112 such as a CRT, an input device 113 such as a keyboard and a mouse, a storage device 114, and a modem 115. The computer 111 has a CPU
121, RAM 122, ROM 123, secondary storage 12
4. Includes interface 125.

A program for realizing the method for dealing with a timing margin error according to the present invention includes a floppy disk and a CD.
-Read from a storage medium M such as a ROM into the computer 111 via the storage device 114. Alternatively, communication channel C
External storage device (not shown) at a remote location connected to L
From the computer 111 via the modem 115. The read program is usually stored in the secondary storage 124 which provides a large storage area such as a hard disk. This program is loaded into the memory space of the RAM 122 and executed by the CPU 121.
The RAM 122 also provides a work area when the CPU 121 executes a program. The ROM 123 stores a basic program for controlling the computer 111 and the like.

The user operates the input device 113 to control the operation of the computer 111. Computer 111
Realizes interactive interaction with the user by displaying the operation result on the display device 112. By executing the program stored in the storage medium M or the storage device at a remote location in the general-purpose computer 111 in this manner, the timing margin error handling method of the present invention can be realized.

As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be freely modified and changed within the scope of the appended claims. Things.

[0064]

According to the above invention, an error list including check results for a plurality of conditions that may be related to the cause of an error is obtained, and a situation is classified based on the error list, thereby causing a problem of a circuit. Points can be clearly shown. Therefore, it is possible to present the problem of the circuit based on the detailed analysis even in the part where the feeling has been conventionally relied on.

Since the correction method is indicated as error elimination information together with the presentation of the problem, the error can be surely eliminated and unnecessary work can be avoided. Further, a problem in circuit design and a problem in layout are clearly distinguished, and it is clearly shown whether any of netlist correction, layout correction or logic correction is necessary. Therefore, the work sharing between the circuit designer and the layout designer can be reliably distinguished, and the work process of the entire system can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a timing margin error handling method according to the present invention.

FIG. 2 is a diagram showing conditions and types of errors to be checked when creating an error list.

FIG. 3 is a diagram for extracting a problem based on the error list (classification result for the classification item) obtained in FIG. 2;

FIG. 4 is a diagram illustrating a required value.

FIG. 5 is a diagram showing four analysis items to be checked in an analysis step.

FIG. 6 is a diagram illustrating an actual wiring length and a Manhattan length.

FIG. 7A is a diagram showing a case where the wiring is connected to a vine-vine type, and FIG. 7B is a diagram showing a case where the wiring is not a vine-type.

FIG. 8 is a diagram showing a classification table for classifying a situation and obtaining a correction method based on a check result of an analysis item.

FIGS. 9A and 9B are diagrams illustrating a method of specifying a cell at the time of buffer insertion.

FIGS. 10A and 10B are diagrams showing a method of reducing the number of branches.

FIGS. 11A and 11B are diagrams showing a method of replacing a continuous 1-bit adder with another adder.

FIG. 12 is a diagram showing a configuration example of a system for realizing the present invention.

FIG. 13 is a diagram showing an example of a conventional countermeasure for a timing error margin.

FIG. 14 is a diagram showing another example of a conventional countermeasure for a timing error margin.

[Explanation of symbols]

 110 System 111 Computer 112 Display device such as CRT 113 Input device 114 Storage device 115 Modem 121 CPU 122 RAM 123 ROM 124 Secondary storage 125 Interface

Claims (15)

[Claims] 1. An error list including a type of an error and a check result of a plurality of conditions related to the cause of the error is generated, and b) an error status is classified based on the error list. A method for correcting a timing margin error in a semiconductor integrated circuit, the method including steps of extracting a problem and determining an error correction method, the error correction method being classified into netlist correction, layout correction, and logic correction. . 2. The step a) checks whether a path in which an error has occurred is a hold time error or a setup time error, checks whether a required value is appropriate, and checks the influence of the wiring length. 2. The method according to claim 1, further comprising the step of checking whether or not the number of steps has been received and checking whether or not the number of steps is abnormally large. 3. The timing margin according to claim 2, wherein the step of checking whether the number of stages is abnormally large further includes the step of checking whether one-bit adders are continuous. Error handling method. 4. The step b) includes: b1) performing a further check on a plurality of analysis items related to the cause of the error according to the classification result of the error situation; and b2) checking the plurality of analysis items. 3. The method of claim 2, further comprising determining at least one of the correction methods based on a result. 5. The step b1) checks whether or not the driving capability is appropriate according to the classification result of the error situation, checks whether or not there is wiring routing, and logically branches. 5. The method according to claim 4, further comprising the step of checking whether or not there is a line, and checking whether or not the wiring is connected to the vine. 6. An error list generating means for generating an error list including a type of an error and a check result for a plurality of conditions related to the cause of the error, and classifying the status of the error based on the error list. And a program for causing a computer to deal with a timing margin error in a semiconductor integrated circuit by including error correction method determining means for determining an error correction method classified into netlist correction, layout correction, and logic correction. Machine-readable storage medium on which is recorded. 7. An error list generating means for checking whether a hold time error or a setup time error has occurred for a path in which an error has occurred, and a means for checking whether a required value is appropriate. 7. The machine-readable recording medium according to claim 6, further comprising means for checking whether or not the wiring length is affected, and means for checking whether or not the number of stages is abnormally large. 8. The machine reading device according to claim 7, wherein said means for checking whether or not the number of stages is abnormally large further includes means for checking whether or not 1-bit adders are continuous. Possible recording medium. 9. An analysis item checking means for performing a further check on a plurality of analysis items related to the cause of the error in accordance with a classification result of the error situation, the error correction method determining means, The machine-readable recording medium according to claim 7, further comprising: means for determining at least one of the correction methods based on a check result of an item. 10. An analysis item check means for checking whether or not the drive capability is appropriate according to the classification result of the error situation, and a means for checking whether or not there is wiring routing. 10. The machine-readable recording medium according to claim 9, further comprising: means for checking whether or not a logical branch exists; and means for checking whether or not the wiring is connected in a vine-like manner. 11. An error list generating means for generating an error list including a type of an error and a check result for a plurality of conditions related to the cause of the error, and classifying the status of the error based on the error list. And a timing margin error in the semiconductor integrated circuit, which includes error correction method determination means for determining error correction methods classified into netlist correction, layout correction, and logic correction. apparatus. 12. The error list generating means checks whether a path in which an error has occurred is a hold time error or a setup time error.
a means for checking whether or not the ired value is appropriate; a means for checking whether or not the wiring length is affected; and a means for checking whether the number of stages is abnormally large. An apparatus according to claim 11. 13. The apparatus according to claim 1, wherein said means for checking whether or not the number of stages is abnormally large further includes means for checking whether or not 1-bit adders are continuous.
3. The apparatus according to 2. 14. The error correction method determining means, further comprising: an analysis item checking means for further checking a plurality of analysis items related to the cause of the error in accordance with the classification result of the error situation; 13. The apparatus according to claim 12, further comprising: means for determining at least one of the correction methods based on an item check result. 15. The analysis item checking means includes means for checking whether or not the driving capability is appropriate according to the classification result of the error situation, and means for checking whether or not wiring is routed. 15. The apparatus according to claim 14, further comprising: means for checking whether or not a logical branch exists; and means for checking whether or not wiring is connected in a vine-like manner.