JPH11282886A - System and method for replacing cell and recording medium recording cell replacement program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve low power consumption property without increasing a circuit scale by inputting a cell consisting of a high threshold transistor and low threshold transistor and registered cell information, replacing a cell in a logic circuit and outputting new logic circuit information. SOLUTION: A signal value that is set to each node is calculated. An output of an internal signal calculating means 102, that is, a signal value that is set to each node in the existing logic circuit at the time of standby, an input logic circuit 100 and a leak cut library 103 are inputted to a cell replacing means 104 and the means 104 selects a cell which is for effectively cutting a leak current according to the signal value set to each node in the existing logic circuit from the library 103, replaces a cell, also replaces a pin when necessary and outputs a net list of an output logic circuit 105, that is, a new logic circuit which effectively cuts a leak current at the time of standby.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CAD (Computing) for generating a CMOS logic circuit realizing low power consumption.
er Aided Design) system.

[0002]

2. Description of the Related Art A CMOS logic gate (cell) consumes power only during a logic operation, and has a low power consumption such that a leakage current during a standby (standby) is extremely small. For this reason, a CMOS logic circuit including CMOS logic gates (cells) is a useful LSI for an electronic device that uses a battery as a power source for a long time, such as a mobile terminal or a mobile phone.

However, since the CMOS logic circuit performs a logic operation by charging and discharging the capacitance of the electrodes, if the logic amplitude is equal to the power supply voltage, the power consumption of the entire chip is proportional to the square of the power supply voltage. , And increases in proportion to the number of gates and the operating frequency. Therefore, the power consumption of a chip in which a large number of transistors are integrated by the recent miniaturization technology becomes extremely enormous.

In order to reduce such enormous power consumption, C
A method for reducing the power supply voltage or the logic amplitude of the MOS logic circuit is known. However, such a reduction in the power supply voltage or the logic amplitude causes a decrease in the saturation current of the transistor, and the operation speed of the CMOS logic circuit is greatly increased. To decline. In order to prevent the decrease in the saturation current, in other words, to obtain a large saturation current with a low power supply voltage or a logic amplitude, a method of lowering the threshold value of the transistor is considered.
A decrease in the threshold value of the transistor causes an increase in the leakage current of the transistor when the transistor is turned off (when the transistor is turned off). That is, if a transistor with a high threshold value is used, the operation speed of the circuit is reduced but the leakage current can be suppressed, and if a transistor with a low threshold value is used, the operation speed of the circuit increases but the leakage current increases. .

[0005] In view of this, a method has been conceived in which both the high-threshold transistor and the low-threshold transistor are used to increase the speed of the circuit operation while suppressing the leakage current. Japanese Patent Application Laid-Open No. 9-46212 discloses a method of using both a high-threshold transistor and a low-threshold transistor in order to suppress the power consumption of a chip.

FIG. 16 shows a conventional technique disclosed in Japanese Patent Application Laid-Open No. 9-462.
12 shows a buffer circuit according to a first embodiment (Japanese Patent Laid-Open No. 9-46212, FIG. 1). 9, 10, 11
And 12 are inverters composed of low-threshold MOS transistors, 13 is a high-threshold NMOS transistor, 14
Is a high threshold PMOS transistor and 15 is a low threshold PM
The OS transistor 16 is a high threshold NMOS transistor. When the CL signal is "1" and the CL signal is "0", the transistors 13 and 14 are turned on, and the inverters 9, 10, 11 and 12 are turned on. The operation speed of the inverters 9, 10, 11 and 12 is high because the inverters are constituted by low threshold voltage MOS transistors. Next, when the CL signal is “0” and the CL signal is “1”, the transistors 13 and 14 are turned off, and the inverters 9, 10, 11 and 12 enter the standby state (standby state). Become. In this standby state, the high threshold transistors 13 and 14 are turned off (the high threshold transistors 13 and 14 are turned off).
Is turned off), the inverters 9, 1
Leakage current flowing to GND through 0, 11 and 12 is effectively cut.

[0007]

However, the above-described method of cutting off the leak current by using both the high threshold transistor and the low threshold transistor has the following problems. First, in the buffer circuit shown in FIG. 1 of Japanese Patent Application Laid-Open No. 9-46212 shown in FIG.
It is necessary to optimize according to the size of 10, 11, and 12. This optimization involves a very difficult process of evaluating the characteristics or performance of the buffer circuit. Also, if there is a circuit change such as adding a new inverter,
It is necessary to re-evaluate the characteristics or performance of the circuit to determine the size of the high threshold transistor. Therefore, Japanese Patent Application Laid-Open No. 9-462
According to the technique disclosed in Japanese Patent Application Publication No. 12, it is very difficult to design a circuit using an existing CAD system.

Second, the circuit requires new high-threshold transistors 13 and 14, and new signal lines for connecting the high-threshold transistors 13 and 14 and the inverters 9, 10, 11 and 12. The area increases and the cost of the semiconductor circuit increases. The present invention has the first problem described above, that is, it is very difficult to use an existing CAD system due to a difficult circuit characteristic evaluation process.
Another object of the present invention is to solve the second problem described above, that is, an increase in circuit scale due to the use of new transistors and signal lines.

[0009]

Means for Solving the Problems and Effects thereof [Claim 1] In claim 1, logic circuit information and predetermined signal information are input, and each of the logic circuits is inputted based on the predetermined signal information. A cell in which an internal signal calculating means for calculating a signal value of the node, an internal signal calculated by the internal signal calculating means, the logic circuit information, and a cell including a high threshold transistor and a low threshold transistor are registered. Cell replacement means for receiving information and replacing the cells in the logic circuit and outputting new logic circuit information.

According to the cell replacement system of the first aspect, the function of the existing logic circuit can be maintained the same,
It is possible to design a logic circuit that effectively cuts off leakage current during standby. According to the cell replacement system according to the first aspect, the existing CAD system can be easily used and only the cell replacement is performed (pin replacement is performed as necessary). It is possible to design a semiconductor circuit excellent in low power consumption without increasing the power consumption.

[Claim 2] According to claim 2, the circuit information is described at the transistor level, predetermined signal information, information necessary for logic synthesis, a high threshold transistor and a low threshold transistor. The cell information in which the cell to be registered is registered is input, logic synthesis, internal signal calculation for calculating a signal value of each node of the logic circuit based on the predetermined signal information, and replacement of a cell in the circuit are performed. A cell replacement system is provided, comprising means for performing.

According to the cell replacement system according to the second aspect, the same effect as that of the cell replacement system according to the first aspect can be obtained. According to the cell replacement system according to the second aspect, logic synthesis and cell replacement can be performed simultaneously, and the time required for circuit design can be reduced. [Claim 3] In claim 3, the cell replacement is performed by a pin replacement process.
Alternatively, a cell replacement system according to claim 2 is provided.

According to the cell replacement system according to the third aspect, the same effect as that of the cell replacement system according to the first aspect can be obtained. Further, according to the cell replacement system according to the third aspect, not only the replacement with the cell that effectively cuts the leak current, but also the pin replacement process is performed, so that the leak current can be cut more effectively, and the chip is replaced. Low power consumption can be realized.

[Claim 4] A cell replacement system according to claim 1 or 3, wherein the predetermined signal information is an output signal of a storage element. According to the cell replacement system according to the fourth aspect, the same effect as that of the cell replacement system according to the first aspect can be obtained.

[5] The cell replacement system according to [1] or [3], wherein the predetermined signal information is an output signal of a state holding element. . According to the cell replacement system according to the fifth aspect, the same effect as that of the cell replacement system according to the first aspect can be obtained.

[Claim 6] In claim 6, the predetermined signal information is stored in a memory and sent to each of the chained scan flip-flops. 5. A cell replacement system according to item 5. According to the cell replacement system according to the sixth aspect, the same effect as that of the cell replacement system according to the first aspect can be obtained. Further, according to the cell replacement system according to the sixth aspect, by using the flip-flop with scan, it is possible to easily supply predetermined signal information at the time of standby to an input of a predetermined path.

[Claim 7] In claim 7, in the registered cell information, the first input terminal has a low threshold value of the first input terminal.
A first circuit composed of a transistor of a conductivity type and a second circuit composed of a transistor of a second conductivity type having a low threshold value, wherein a second input terminal is connected to the first circuit and the second circuit; 4. The cell according to claim 1, wherein the circuit is connected to a transistor of the first conductivity type having a high threshold value or a transistor of the second conductivity type having a high threshold value. Provide a replacement system.

According to the cell replacement system according to the seventh aspect, the same effect as that of the cell replacement system according to the first aspect can be obtained. [Claim 8] In claim 8, the registered cell information includes one or more low-threshold transistors provided on the power supply potential side and one or more high-threshold transistors provided on the ground potential side. NAN composed of a threshold transistor
A cell replacement system according to claim 1, 2 or 3, wherein a D gate is included.

According to the cell replacement system of the eighth aspect, the same effect as that of the cell replacement system of the first aspect can be obtained. [Claim 9] In claim 9, the registered cell information includes one or a plurality of high-threshold transistors provided on a power supply potential side and one or a plurality of low-threshold transistors provided on a ground potential side. NAN composed of a threshold transistor
A cell replacement system according to claim 1, 2 or 3, wherein a D gate is included.

According to the cell replacement system of the ninth aspect, the same effect as that of the cell replacement system of the first aspect can be obtained. [Claim 10] The cell replacement system according to claim 1, wherein the registered cell information includes a static logic gate. provide.

According to the cell replacement system of the tenth aspect, the same effect as that of the cell replacement system of the first aspect can be obtained. [Claim 11] In Claim 11, the internal signal calculated by the internal signal calculation means, the circuit information and the registered cell information are input, and the cells in the circuit are obtained from the registered cell information. Means for selecting one or a plurality of cells corresponding to the above, means for selecting one cell from the plurality of selected cells, and replacement of cells in the circuit to obtain new logic circuit information. A cell replacement system according to claim 1 or 3, further comprising a cell replacement unit for outputting.

According to the cell replacement system of the eleventh aspect, the same effect as that of the cell replacement system of the first aspect can be obtained. [Claim 12] In claim 12, in the pin replacement processing, an input pin of the cell connected to each of a plurality of wirings input to a cell realizing a predetermined logic is replaced with another input pin. The cell replacement system according to claim 3, wherein:

According to the cell replacement system of the twelfth aspect, the same effect as that of the cell replacement system of the first aspect can be obtained. [Claim 13] According to claim 13, the registered cell information includes a high-conductivity first-conductivity-type transistor for precharging and a low-threshold second-conductivity transistor connected to one or more input terminals. A cell replacement system according to claim 1, 2 or 3, which includes a cell including a circuit including a transistor of a conductivity type.

According to the cell replacement system of the thirteenth aspect, the same effect as that of the cell replacement system of the first aspect can be obtained. [Claim 14] The cell replacement system according to claim 1, wherein the registered cell information includes a dynamic logic gate. provide.

According to the cell replacement system of the fourteenth aspect, the same effect as that of the cell replacement system of the first aspect can be obtained. According to a fifteenth aspect, the cell replacement system according to the first or third aspect is provided, wherein the predetermined signal information is fixed to a power supply potential or a ground potential.

According to the cell replacement system according to the fifteenth aspect, the same effect as that of the cell replacement system according to the first aspect can be obtained. According to the cell replacement system according to the fourteenth aspect, by using the power supply potential or the ground potential as the predetermined signal information, the node potential in the circuit at the time of standby can be easily fixed. Can be performed stably and effectively.

[Claim 16] In claim 16, the cell registered in the cell information suppresses a leakage current by turning off a high threshold transistor in a standby state. A cell replacement system according to claim 2 or claim 3 is provided.

According to the cell replacement system of the sixteenth aspect, the same effect as that of the cell replacement system of the first aspect can be obtained. [Claim 17] A cell replacement method according to claim 17, which replaces a cell in a circuit and outputs new logic circuit information, wherein the logic circuit information and predetermined signal information are input, and Calculate the signal value of each node of the logic circuit based on the signal information of, the calculated internal signal value,
The logic circuit information and cell information in which a cell including a high threshold transistor and a low threshold transistor are registered are input, and the replacement of cells in the logic circuit to output new logic circuit information is performed. A featured cell replacement method is provided.

According to the cell replacement method of claim 17,
The same effect as the cell replacement system according to claim 1 can be obtained. [Claim 18] A cell replacement method according to claim 18, which performs replacement of cells in a circuit and outputs logic circuit information, wherein the circuit information described at a transistor level, predetermined signal information, and logic Information necessary for synthesis and cell information in which a cell composed of a high threshold transistor and a low threshold transistor are registered are input, and the logic synthesis and each node of the logic circuit are performed based on the predetermined signal information. The cell replacement method is characterized in that the internal signal calculation for calculating the signal value and the replacement of the cells in the circuit are performed.

According to the cell replacement method of the eighteenth aspect,
The same effect as the cell replacement system according to claim 2 can be obtained. [Claim 19] A recording medium according to claim 19, wherein a cell replacement program for replacing cells in a circuit and outputting new logic circuit information is recorded, wherein the logic circuit information and the predetermined signal information are recorded. Is input, a signal value of each node of the logic circuit is calculated based on the predetermined signal information, and the calculated internal signal value, the logic circuit information, and a high threshold transistor and a low threshold transistor are calculated. The present invention provides a recording medium on which a cell replacement program is recorded, in which cell information in which a cell to be configured is registered is input, a cell in a logic circuit is replaced, and new logic circuit information is output.

According to the recording medium in which the cell replacement program according to the nineteenth aspect is recorded, the same effect as the cell replacement system according to the first aspect can be obtained. [Claim 20] A recording medium according to claim 20, wherein a cell replacement program for replacing cells in a circuit and outputting logic circuit information is recorded, the circuit medium being described at a transistor level; Predetermined signal information;
Information required for logic synthesis and cell information in which a cell composed of a high threshold transistor and a low threshold transistor are registered are input, and based on the logic synthesis and the predetermined signal information, Provided is a recording medium on which a cell replacement program is recorded, wherein internal signal calculation for calculating a signal value of a node and replacement of cells in a circuit are performed.

According to the recording medium in which the cell replacement program according to the twentieth aspect is recorded, the same effect as that of the cell replacement system according to the second aspect can be obtained.

[0033]

FIG. 1 shows a first principle diagram of the present invention. FIG. 1 is a flow chart of a CAD system for designing a logic circuit that maintains the same function and effectively cuts a leakage current at the time of standby from an existing logic circuit.

The input logic circuit 100 is a netlist (gate-level logic circuit) of existing circuits. The standby state 101 is predetermined signal information externally supplied at the time of standby.
Is a cell library (cell information) in which cells that effectively cut the leakage current during standby are registered.
The output logic circuit 105 is a netlist of a new logic circuit that has been replaced with a cell that effectively cuts off leakage current during standby.

Input logic circuit 100 and standby state 10
1 is input to the internal signal calculation means 102, and the internal signal calculation means 102 is set to each node in the existing logic circuit when a predetermined signal value from the outside is given to the existing logic circuit. Calculate the signal value. Then, the output of the internal signal calculation means 102, that is, the signal value set for each node in the existing logic circuit during standby, the input logic circuit 100, and the leak cut library 103
The cell replacement means 104 is inputted to the cell replacement means 104
Selects a cell from the leak cut library 103 for effectively cutting a leak current based on a signal value set at each node in an existing logic circuit, and replaces the cell, and replaces a pin when necessary. Also do
The output logic circuit 105 outputs a netlist of a new logic circuit that effectively cuts off leakage current during standby. The cell replacement will be described in detail with reference to FIGS. 4 and 5, and the pin replacement will be described in detail with reference to FIG.

As described above, according to the CAD system shown in FIG. 1, it is possible to obtain a new logic circuit replaced with a cell effective for cutting off a leakage current at the time of standby. FIG. 2 shows a second principle diagram of the present invention. FIG.
Similar to FIG. 1, the flow of the CAD system is to design a circuit that maintains the same function and effectively cuts the leakage current at the time of standby from the existing circuit.
The circuit information input to the CAD system is not a netlist, but RTL (Register Transfer).
(Level) description.

The RTL 106 is an RTL description of the existing circuit. The standby state 101 is predetermined signal information externally supplied in the standby state. A registered cell library (cell information), a timing library 107 is a library in which necessary timing information for performing logic synthesis is registered, and an output logic circuit 105 is a cell that effectively cuts a leak current during standby. Is a netlist of the new circuit composed of.

RTL 106 and standby state 101
, The timing library 107 and the leak cut library 103 are input to the logic circuit synthesizing unit 108, which expands the RTL 106 into a netlist by logic synthesis. Expand into a netlist using current-cut cells. As in the case of the CAD system shown in FIG. 1, the cell is selected based on a signal value set at each node in the logic circuit based on external signal information at the time of standby specified in the standby state 101. This is performed by selecting cells for effective cutting from the leak cut library 103. In addition, when necessary, replacement of pins is performed.

In the flow of the CAD system for inputting the RTL description shown in FIG. 2, logic synthesis and cell replacement can be performed at the same time (pin replacement is performed at the same time as necessary), which is necessary for circuit design. Time can be reduced. As described above, according to the CAD system shown in FIG. 2, a new netlist can be directly obtained from the RTL description by replacing the cell with a cell that effectively cuts off the leakage current during standby.

The cell replacement system shown in FIGS. 1 and 2 has a semiconductor memory (RAM, RO,
M), a floppy disk (FD), a hard disk (HD), an optical disk (CD, DVD), a magneto-optical disk (MO, MD), and a magnetic tape. FIG. 3 shows a first principle diagram of the cell of the present invention. That is, in FIG. 3, the leak cut library 10 which is the cell library (cell information) shown in FIGS.
3 shows a first principle diagram of a cell registered in No. 3 for effectively cutting a leak current.

FIGS. 3A and 3B show a static logic gate (static) having two inputs and one output.
gate). In FIG. 3A, a first input terminal InputA has a first circuit 150 composed of a low-threshold PMOS transistor (pmos Low Vth) and a low-threshold NMOS transistor (nmos).
Low Vth), and the second input terminal InputB is connected to a low threshold PM
A first circuit 150 composed of an OS transistor (pmos Low Vth), a second circuit 151 composed of a low threshold NMOS transistor (nmos Low Vth), and a high threshold NMOS transistor (nmos)
High Vth) 152. Further, the output terminal Output is connected to an output node 153 to which the first circuit 150 and the second circuit 151 are connected.

Here, when the input signal “0” is supplied to the second input terminal InputB, the high-threshold NMOS transistor 152 is cut off (turned off) and the output terminal OutputB is turned off.
Outputs an output signal "1". Since the high-threshold NMOS transistor 152 is cut off (turned off), the leak current in the path from the power supply potential to the ground potential is effectively cut. Thus, the high threshold NMOS transistor 15
If 2 is cut off (off), the leak current is cut off, so that either the “0” or “1” input signal may be supplied to the first input terminal InputA. The first
A plurality of low-threshold PMOS transistors are described in the circuit 150, and a plurality of low-threshold NMOS transistors are described in the second circuit 151. This is because a path from the power supply potential to the high-threshold NMOS transistor 152 is provided. Is not necessarily one. If the high-threshold NMOS transistor 152 is always cut off (turned off) during standby, the leak current is effectively cut off. Therefore, the circuit 150 and the circuit 151 may have any transistor configuration.

In FIG. 3B, the first input terminal I
nputA is a high threshold PMOS transistor (nmos)
High Vth) 154 gate and low threshold PMO
A first circuit 155 composed of an S transistor (pmos Low Vth) and a second circuit 156 composed of a low threshold NMOS transistor (nmos Low Vth) are connected, and the second input terminal InputB is connected to a low threshold. PMOS transistor (pmos Low Vt)
h) and a low threshold NMOS
The second circuit 156 including a transistor (nmos Low Vth) is connected. The output terminal O
input is connected to an output node 157 to which the first circuit 155 and the second circuit 156 are connected.

Here, when the input signal “1” is supplied to the first input terminal InputA, the PMOS transistor 152 having a high threshold value is cut off (turned off), and the output terminal Output is output.
Outputs an output signal "0". Since the PMOS transistor 154 having the high threshold is cut off (turned off), the leak current in the path from the power supply potential to the ground potential is effectively cut. Thus, the high threshold PMOS transistor 15
Since the leakage current is cut off when 4 is cut off (off), either “0” or “1” input signal may be supplied to the second input terminal InputB. The first
A plurality of low-threshold PMOS transistors are described in the circuit 155, and a plurality of low-threshold NMOS transistors are described in the second circuit 156. Is not necessarily one. If the high-threshold PMOS transistor 154 is always cut off (turned off) during standby, the leak current is effectively cut off. Therefore, the circuit 155 and the circuit 156 may have any transistor configuration.

FIG. 4 shows a first embodiment of the present invention and FIG.
FIG. 6 shows a second embodiment of the present invention, and FIG. 6 shows a third embodiment of the present invention. 4, 5, and 6,
The contents of the CAD system shown in FIG. 1 will be described using specific circuits. The logic circuit shown in FIG. 4 includes three D flip-flops 201, 202, and 203 (hereinafter, D flip-flops are referred to as D-FFs) and four NAND gates 2.
04, 205, 206 and 207.
That is, the output of the D-FF 201 and the output of the D-FF 202 are input to the NAND gate 204, and the output of the D-FF 202 and the output of the D-FF 203 are output to the NAND gate 205.
And NAND gate 204 and NAND gate 2
05 is input to the NAND gate 206, and NAN
The output of the D gate 205 and the output of the D-FF 203 are NA
The signal is input to the ND gate 207.

FIG. 4 shows a state of the logic circuit after the replacement of the cell for cutting off the leak current in the standby state. That is, the output values of the D-FFs 201, 202, and 203 correspond to predetermined signal information (standby state 101) externally supplied during standby, and the numbers in parentheses shown in FIG.
It shows the output value of each of the nodes 202 and 203, or the signal value at each node when a "0" signal is given as predetermined signal information (standby state 101) externally given during standby.

Here, the NAND gates 204, 205 and 207 are constituted by first NAND gates,
The D gate 206 is constituted by a second NAND gate. FIG. 5A shows a first NAND gate, and FIG.
(B) shows the second NAND gate. The first NAND gate shown in FIG. 5A includes low-threshold PMOS transistors 207 and 208, a low-threshold NMOS transistor 209, and a high-threshold NMOS transistor 210. The first input terminal A1 is a low threshold PMOS
The second input terminal A is connected to the gate of the transistor 207 and the gate of the NMOS transistor 209 having a low threshold.
2 is connected to the gate of the low threshold PMOS transistor 208 and the gate of the high threshold NMOS transistor 210, and the source or drain of the low threshold PMOS transistor 207 is connected to the drain or source of the low threshold NMOS transistor 209. Node with low threshold PMO
The source or the drain of the S transistor 208 is connected to the output terminal Output.

As described above, the low threshold transistor 207,
208 and 209 are provided on the power supply potential side, and the high threshold transistor 210 is provided on the ground potential side. That is,
The current flowing from the power supply potential side to the ground potential side always passes through the high threshold transistor 210 regardless of which of the low threshold transistors 207, 208 and 209. Such a configuration indicates that if the high threshold transistor 210 provided on the ground potential side is turned off (standby) during standby, a leak current flowing from the power supply potential side to the ground potential side can be effectively cut. In FIG. 5A, at the time of standby, the “0” signal is supplied to the input terminal A2, so that the high threshold transistor 210 is always turned off (off state). Low threshold transistor 207, 208 or 2
09 is a conduction state (ON state) or a cutoff state (OFF state)
The low threshold transistor 20 can be used in any state.
7 and 209 can be set to either a "0" signal or a "1" signal at the input terminal A1.

The second NAND gate shown in FIG. 5B has high threshold PMOS transistors 211 and 212.
And low threshold NMOS transistors 213 and 214. The first input terminal A1 is a high threshold PMOS
The second input terminal A is connected to the gate of the transistor 211 and the gate of the NMOS transistor 213 having a low threshold.
2 is connected to the gate of the high-threshold PMOS transistor 212 and the gate of the low-threshold NMOS transistor 214, and the source or drain of the high-threshold PMOS transistor 211 is connected to the drain or source of the low-threshold NMOS transistor 213. Node with high threshold PMO
The source or drain of the S transistor 212 is connected to the output terminal Output.

As described above, the high threshold transistors 211 and 212 are provided on the power supply potential side, and the low threshold transistors 213 and 214 are provided on the ground potential side. That is, the current flowing from the power supply potential side to the ground potential side always passes through the high threshold transistor 211 or 212. Such a configuration includes the high threshold transistors 211 and 2 provided on the ground potential side during standby.
This indicates that, when both of them are in a cutoff state (off state), a leak current flowing from the power supply potential side to the ground potential side can be effectively cut. In FIG. 5B, during standby, a “1” signal is supplied to the input terminal A1, and “1” is also supplied to the input terminal A2, so that both the high threshold transistors 211 and 212 are always in a cutoff state (off state). State).

Here, the description returns to FIG. In FIG. 4, as described above, the NAND gates 204, 205,
Reference numerals 206 and 207 each include a first NAND gate. Each of the NAND gates 207 includes a second NAND gate. A number in parentheses indicates a signal value of each node during standby. In the NAND gate 204 which is a NAND gate, the output signal “0” of the D-FF 202 is input to the second input terminal A2, so that the high threshold transistor 210 is cut off (turned off) and the leak current is effectively cut. .

Similarly, the first NAND gate NA
In the ND gate 205, the second input terminal A2 has D-
Since the output signal “0” of the FF 203 is input, the high threshold transistor 210 is cut off (turned off), and the leak current is effectively cut. Similarly, in the NAND gate 207, which is the first NAND gate, the second input terminal A2
Is input with the output signal “0” of the D-FF 203,
The high threshold transistor 210 is cut off (turned off), and the leak current is effectively cut.

The output signal "1" of the NAND gate 204 is input to the first input terminal A1 of the NAND gate 206 as the second NAND gate, and the output signal "1" of the NAND gate 205 is input to the second input terminal A2. , Both the high threshold transistors 211 and 212 are cut off (turned off), and the leak current is effectively cut. In FIG. 4, the output value of the D-FF is predetermined signal information (standby state 101) externally supplied in the standby state. Any circuit may be used as long as it is determined in a specific manner.

FIG. 6 shows an embodiment in which an output value of a circuit other than a storage element such as a D-FF is set to predetermined signal information (standby state 101) externally applied during standby. The logic circuit shown in FIG. 6 is obtained by inserting an AND circuit between the D-FF and the NAND gate of the logic circuit shown in FIG. Specifically, the output of the D-FF 201 is input to the AND gate 216, and the AND gate 2
16 is input to the NAND gate 204, and DF
The output of F202 is input to an AND gate 217,
The output of D gate 217 is connected to NAND gate 204 and NAN.
Input to the D-gate 205 and the output of the D-FF 203
The input to the ND gate 218 and the output of the AND gate 218 are input to the NAND gate 205 and the NAND gate 207. The configuration of the NAND gate is exactly the same as in FIG.

The other input terminal of each of the AND gates 216, 217 and 218 has a signal S indicating a standby state.
A tan-by signal is provided. This Stand-b
When the “0” signal is supplied as the y signal,
The output of each of the D gates 216, 217 and 218 is fixed to a "0" signal, and the NAND gates 204 and 2 connected to the outputs of the AND gates 216, 217 and 218 are connected.
05 and 207, that is, predetermined signal information externally given during standby (standby state 10
1) is uniquely held. As described above, by inserting a state holding circuit such as an AND gate, it is possible to easily set predetermined signal information (standby state 101) externally supplied at the time of standby.

FIG. 7 shows a fourth embodiment of the present invention. In FIG. 7, as in FIG. 4, the contents of the CAD system shown in FIG. 1 will be described using specific circuits. The logic circuit shown in FIG. 7 includes three D flip-flops 208 with scan,
209 and 210 (hereinafter, a D flip-flop is referred to as a D-FF with scan), four NAND gates 211, 212, 213 and 214, and a memory 215. The circuit shown in FIG.
Is a D-FF with a scan, and the memory is connected to the D-FF with a scan.

In the logic circuit shown in FIG.
-FFs are connected in a chain. A specific configuration of the logic circuit illustrated in FIG. 7 is described. The output of the D-FF with scan 208 and the output of the D-FF with scan 209 are the first N
D-FF with scan input to AND gate 211
209 and the output of the D-FF with scan 210 are input to the first NAND gate 212, and the first NAN
The outputs of the D gate 211 and the first NAND gate 212 are input to the second NAND gate 213, and the first NAN
The output of the D gate 212 and the output of the D-FF 210 with scan are input to the first NAND gate 214, the memory 215 is connected to the scan-in terminal SI of the D-FF 210 with scan, and the scan-out of the D-FF 210 with scan. The terminal is connected to the scan-in terminal of the D-FF 209 with scan, and the D-FF 209 with scan is connected.
Are connected to the scan-in terminal of the D-FF 208 with scan.

FIG. 7 shows the state of the logic circuit after the replacement of the cell for cutting off the leakage current in the standby state, similarly to FIG. That is, the output values of the D-FFs with scans 208, 209 and 210 correspond to the external input signals during standby, and the numbers in parentheses shown in FIG. 6 are the output values of the D-FFs with scans 208, 209 and 210, respectively. It indicates a signal value at each node when there is a signal or when a "0" signal is given as an external input signal. Here, the difference from FIG. 4 is that the output values of the D-FFs with scans 208, 209 and 210, that is, the predetermined signal information (standby state 101) externally given at the time of standby are output from the memory 215 via the scan path connected in a chain. Is to be given. The memory 215 sends predetermined signal information (standby state 101) externally supplied to the scan-in terminal SI of the D-FF with scan 210 during standby. The D-FF with scan 210 outputs the signal sent to the scan-in terminal SI to the output terminal Q, and outputs the D-FF2 with scan from the scan-out terminal SO.
09 to the scan-in terminal SI. Similarly, the D-FF with scan 209 outputs the signal sent to the scan-in terminal SI to the output terminal Q and sends the signal from the scan-out terminal SO to the scan-in terminal SI of the D-FF with scan 208. Similarly, D-
The FF 208 outputs the signal sent to the scan-in terminal SI to the output terminal Q and outputs the signal to the scan-out terminal SO.
To the scan-in terminal SI of another D-FF with scan (not shown).

As described above, when the D-FF with scan is used, predetermined signal information (externally supplied to the standby state 10) externally supplied to the input of the predetermined path during standby is input.
1) can be easily set. The principle that each high-threshold transistor in each of the NAND gates 211, 212, 213, and 214 shuts off (turns off) at the time of standby to cut a leak current is exactly the same as that described in FIG. I do.

As described above, according to the CAD system shown in FIG. 1 or FIG. 2, the standby system is used by using the cell composed of both the high threshold transistor and the low threshold transistor as shown in FIG. It is possible to design a circuit that can effectively cut the leakage current at the time. FIG.
3 shows a third principle diagram of the present invention.

FIG. 8 shows a detailed flow of the cell replacement means 104 in the CAD system shown in FIG.
Netlist of existing logic circuits (gate-level logic circuits)
And a leak cut library 10 which is a cell library (cell information) in which cells for effectively cutting the leak current during standby are registered.
3 and an internal signal value 109 calculated in the CAD flow shown in FIG. 1 or 2 and set to each node in the existing logic circuit at the time of standby are input to the matching circuit detecting means 110. . Here, the internal signal value 1
Reference numeral 09 denotes information calculated by the internal signal calculation means 102 shown in FIG. 1 or the logic circuit synthesis means 108 shown in FIG. 2 based on the input logic circuit 100 and the standby state 101 as described above. The matching circuit detecting means 110
Based on the internal signal value 109, one or more cells for effectively cutting the leak current are selected from the leak cut library 103 for each existing cell.
Then, the circuit selecting means 111
From among the plurality of cells selected at 0, cells that effectively cut the leak current most are selected in consideration of the entire circuit configuration, cell functions, and the like. When only one cell is selected in the matching circuit detecting means 110,
The process of selecting the best cell in the circuit selecting means 111 is not performed. Next, in the second cell replacement means 112,
The existing cells are replaced with the best cells selected by the circuit selecting means 111, and the pins are replaced if necessary. The process of replacing this pin
This will be described with reference to FIG.

As described above, the cell replacement means 10 shown in FIG.
Reference numeral 4 comprises a matching circuit detecting means 110, a circuit selecting means 111, and a second cell replacing means 112, and outputs an output logic circuit 105 as a new netlist. FIG.
Shows an example of pin replacement according to a fifth embodiment of the present invention. FIG. 9A shows a NAND gate and its equivalent circuit. This NAND gate is the NAN shown in FIG.
It has the same transistor configuration as the D gate, and has a first input terminal A1, a second input terminal A2, and an output terminal Output.
t, and the low-threshold PMOS transistors 207, 2
08, a low threshold NMOS transistor 209, and a high threshold NMOS transistor 210. If the high-threshold transistor 210 provided on the ground potential side is cut off (off) during standby, a leak current flowing from the power supply potential side to the ground potential side can be effectively cut off. It is necessary to always turn off the high threshold transistor 210 so as to apply a signal. Therefore, for example, as shown in FIG. 9B, the first wiring W1 maintained at the signal value “0” in the standby state is connected to the first input terminal A1 of the NAND gate, and the signal value “1” is set. Is kept at the second input terminal A2 of the NAND gate.
Connected to the high threshold transistor 210
Cannot be cut off (off), so that a leak current flowing from the power supply potential side to the ground potential side cannot be effectively cut. On the other hand, two inputs A1 of the NAND gate
And A2 are logically equivalent, and the value of the output signal does not change even if the input signals are exchanged with each other. So, NAN
It is possible to replace the wiring connected to the input terminal of the D gate. Replacing the signal lines connected to these input terminals for such logically equivalent input terminals will be referred to as pin replacement.

FIG. 9C shows the NAND gate after this pin replacement. In FIG. 9C, the second wiring W2 whose state is maintained at the signal value "1" is connected to the first input terminal A1 of the NAND gate, and the second wiring W2 whose state is maintained at the signal value "0". 1 wiring W2 is the second wiring of the NAND gate.
Is connected to the input terminal A2. As described above, in the present invention, not only the replacement with the cell that effectively cuts the leakage current but also the pin replacement processing is performed,
Further, the leakage current is more effectively cut, thereby reducing the power consumption of the chip.

FIGS. 10 and 11 show the second embodiment of the cell of the present invention.
FIG. FIGS. 10 and 11 show a second principle diagram of a cell for effectively cutting the leak current registered in the leak cut library 103 shown in FIGS. 1, 2 and 8. FIG. 9 and 10 show a dynamic logic gate.

In FIG. 10A, the clock terminal C
K is a transistor for precharging, high threshold PM
A low threshold NM used for stabilizing the operation of the gate of the OS transistor 160 and the dynamic logic gate
Are connected to the gate of the OS transistor 162 and have a plurality of input terminals Input1, Input2,.
n (n is a positive integer) is connected to a circuit 161 including low-threshold NMOS transistors 163, 164, and 165 as evaluation transistors, and a high-threshold PMOS transistor 160 as a precharge transistor and a circuit. 161 is connected to the output terminal Output and the charge storage node C
1 is connected. Note that the circuit 161 in FIG.
Inside, three low-threshold transistors 163, 1 for evaluation are used.
Although only 64 and 165 are described, since the transistor configuration of the circuit for evaluation is determined by the function of the gate, the number of transistors is not limited to three and is naturally less than three or four or more. Could be.

The gate configured as shown in FIG. 10A is called a dynamic logic gate. It should be noted that the dynamic logic gate may not include the low threshold NMOS transistor 162 used for stabilizing the gate. The operation of the dynamic logic gate shown in FIG. When the clock signal Φ becomes "0", the high-threshold PMOS transistor 160 connected to the clock terminal CK is turned on, and the charge storage node C1 is charged to the power supply potential or the charge storage node C1 The signal value "1" is output to the output terminal in any case. When the clock signal Φ becomes “1”, the high-threshold PMOS transistor 160 connected to the clock terminal CK is cut off (turned off), and the plurality of input terminals I
... The charge stored in the charge storage node C1 by turning on (turning off) or turning off (turning off) the low-threshold transistor for evaluation in the circuit 161 in accordance with a combination of input signals to ninput1, Input2,. Is stored as it is or discharged to the ground potential.

FIG. 10B is a timing chart showing the operation of the dynamic logic gate shown in FIG. 10A. While the clock signal Φ is "0", the dynamic logic gate is in a precharge phase, in which the charge storage node C1 is charged to the power supply potential or the charge stored in the charge storage node C1 is stored as it is, While the clock signal Φ is "1", it is the phase of evaluation of the dynamic logic gate, and the charge stored in the charge storage node C1 is stored or discharged to the ground potential.

The delay time of the dynamic logic gate shown in FIG. 10A is determined by the speed at which the charge stored in the charge storage node by the evaluation transistor is discharged. Therefore, as shown in FIG. 10 (a), the transistors 163, 164 and 165 for evaluation are
The operation speed can be increased by using a transistor. On the other hand, since the precharging transistor 160 is a PMOS transistor having a high threshold, the clock signal Φ is set to “1” during standby and the precharging transistor 160 is cut off (turned off). Leakage current in a path from a potential to a ground potential can be effectively cut.

In FIG. 11A, the clock terminal C
K is a high-threshold NM which is a transistor for precharging
A low threshold PM used for stabilizing the operation of the gate of the OS transistor 170 and the dynamic logic gate
Are connected to the gate of the OS transistor 172 and have a plurality of input terminals Input1, Input2,.
n (n is a positive integer) is connected to a circuit 171 including low-threshold PMOS transistors 173, 174, and 175 as evaluation transistors, and a high-threshold NMOS transistor 170 as a precharge transistor and a circuit. 171 is connected to the output terminal Output and the charge storage node C
1 is connected. Note that the circuit 171 in FIG.
There are three low-threshold transistors 173, 1 for evaluation.
Although only 74 and 175 are described, the transistor configuration of the circuit for evaluation is determined by the function of the gate. Therefore, the number of transistors is not limited to three, and it is obvious that the number of transistors is less than three or four or more. Could be.

The gate configured as shown in FIG. 11A is a dynamic logic gate like the gate shown in FIG. 11A. As described above, the dynamic logic gate may not include the low threshold PMOS transistor 172 used for stabilizing the gate. The operation of the dynamic logic gate shown in FIG.

When the clock signal Φ becomes "1", the high-threshold NMOS transistor 170 connected to the clock terminal CK becomes conductive (turns on), and the charge stored in the charge storage node C1 is discharged. Alternatively, it is determined whether the discharge state is maintained as it is, and in any case, the signal value “0” is output to the output terminal. When the clock signal Φ becomes “0”, the high-threshold NMOS transistor 170 connected to the clock terminal CK is shut off (turned off), and the plurality of input terminals Input 1 and Input
2... A low-threshold transistor for evaluation in the circuit 171 is turned on (turned on) or turned off (turned off) in accordance with a combination of input signals to Inputn, so that the transistor is charged to the power supply potential or discharged. Is kept as it is.

FIG. 11B is a timing chart showing the operation of the dynamic logic gate shown in FIG. 11A. While the clock signal Φ is "0", it is an evaluation phase of the dynamic logic gate, and is charged up to the power supply potential or the discharge state is held as it is, while the clock signal Φ is "1", This is the precharge phase of the logic gate, and the charge storage node C
It is determined whether the charge charged to 1 is discharged or the discharge state is maintained as it is.

The delay time of the dynamic logic gate shown in FIG. 11A is determined by the speed at which the charge is charged to the charge storage node by the evaluation transistor. Therefore, as shown in FIG. 11A, the operation speed can be increased by configuring the evaluation transistors 173, 174, and 175 with PMOS transistors having a low threshold. On the other hand, the precharge transistor 170
Are high-threshold NMOS transistors, so that the clock signal Φ is set to “0” during standby to shut off (turn off) the transistor 170 for precharging.
By doing so, it is possible to effectively cut the leakage current of the path from the power supply potential to the ground potential.

FIGS. 12 and 13 show a sixth embodiment of the present invention using a dynamic logic gate. 12 and 13 show circuits in which dynamic logic gates are connected in multiple stages. In FIG. 12, the first dynamic logic gate 262 includes an inverter 263
To the second dynamic logic gate 264.

Here, the first dynamic logic gate 262 has the same configuration as the dynamic logic gate shown in FIG. That is, in the first dynamic logic gate 262, the clock terminal CK has a low threshold used for stabilizing the operation of the gate of the high threshold PMOS transistor 250, which is a transistor for precharging, and the dynamic logic gate. Connected to the gate of the NMOS transistor 252 of the
ninput1, Input2,..., where Inputn (n is a positive integer) is a transistor for evaluation, and a low threshold NMO
An output terminal is connected to a node 256 connected to a circuit 251 which is connected to a circuit 251 constituted by S transistors 253, 254 and 255, and is connected to a high-threshold PMOS transistor 250 which is a transistor for precharging, and to charge storage. Node C1 is connected. In addition,
As described above, only three evaluation low-threshold transistors 253, 254, and 255 are described in the circuit 251; however, the transistor configuration of the evaluation circuit is determined by the function of the gate. For this reason, the number is not limited to three, and may naturally be less than three or more than four.

Second dynamic logic gate 264
Also has the same configuration as the dynamic logic gate shown in FIG. A clock terminal CK is connected to the gate of a high-threshold PMOS transistor 259, which is a transistor for precharging, and the gate of a low-threshold NMOS transistor 261 used for stabilizing the operation of a dynamic logic gate (connection line). Are not shown), a plurality of input terminals Input1, Input2,.
Inputn (n is a positive integer) is connected to the circuit 260 including transistors for evaluation, but the charge storage node C1 connected to the output terminal is omitted for simplicity. Although the internal configuration of the circuit 260 is not specified because it is determined by the function of the gate,
It is composed of a low threshold NMOS transistor which is a transistor for evaluation.

The inverter 263 has a low threshold PMOS transistor 257 arranged on the power supply potential side and a high threshold N
MOS transistor 258 is arranged on the ground potential side. The output terminal of the first dynamic logic gate 262 is connected to the input terminal of the inverter 263, and the output terminal of the inverter 263 is connected to the second dynamic logic gate 2
64 input terminals.

The technique of connecting the dynamic logic gates via the inverted CMOS gates as described above is called domino logic. When the dynamic logic gates are directly connected to each other, a signal is input to the next dynamic logic gate after the next dynamic logic gate enters the evaluation phase due to a delay, which causes a malfunction. To prevent this malfunction, domino logic is used.

Here, a low threshold NMOS which is a transistor for evaluation of the first dynamic logic gate 262 is used.
When the circuit 251 including transistors is configured to discharge the charge stored in the charge storage node C1 in the evaluation phase, the first dynamic logic gate 2
The output signal of 62 becomes “0”, and in the inverter 263 connected to the next stage, the low threshold PMOS transistor 257 arranged on the power supply potential side is driven, so that the operation speed is increased. In addition, as described above, in the first dynamic logic gate 262 and the second dynamic logic gate 264, since the evaluation circuits 251 and 260 are both constituted by low-threshold transistors, the operation speed is increased. Can be

On the other hand, at the time of standby, in the first dynamic logic gate 262 and the second dynamic logic gate 264, both the precharge transistors 250 and 259 are PMOS transistors having a high threshold, so that the clock signal Φ By setting "1" to cut off (turn off) the precharge transistors 250 and 259, it is possible to effectively cut the leakage current of the path from the power supply potential to the ground potential.

In the standby mode, the circuit 2 composed of a low threshold NMOS transistor which is a transistor for evaluating the first dynamic logic gate 262
When the circuit 51 is configured to discharge the charge stored in the charge storage node C1 in the evaluation phase,
1 and a plurality of input terminals Input1, Input
When a signal value "1" is given to all of t2... Inputn, its output signal becomes "0", and the inverter 263 connected to the output of the first dynamic logic gate 262 has a ground potential side. Since the disposed high-threshold NMOS transistor 258 is turned off (turned off), the leakage current of the path from the power supply potential to the ground potential can be effectively cut even in the inverter 263. As described above, the leakage current can be effectively cut not only in the dynamic logic gate but also in the inverter inserted by the domino logic, and the low power consumption of the circuit is further spurred.

In FIG. 13, a first dynamic logic gate 282 is connected to a second dynamic logic gate 284 via an inverter 283. Here, the first dynamic logic gate 282 corresponds to FIG.
It has exactly the same configuration as the dynamic logic gate shown in FIG. That is, in the first dynamic logic gate 282, the clock terminal CK has a low threshold used for stabilizing the operation of the gate of the high threshold NMOS transistor 270, which is a transistor for precharging, and the dynamic logic gate. Are connected to the gates of the PMOS transistors 272 and a plurality of input terminals Inpu.
t1, Input2..., where Inputn is a transistor for evaluation, a low threshold PMOS transistor 273;
274 and 275 and is connected to a high threshold N which is a transistor for precharging.
The output terminal is connected to a node 276 where the MOS transistor 270 and the circuit 271 are connected, and the charge storage node C1 is connected. Note that, as described above, the circuit 2
In 71, three evaluation transistors 273, 274
And 275 are described, but since the configuration of the circuit for evaluation is determined by the function of the gate, the configuration is not limited to three and may naturally be less than three or more than four. obtain.

The second dynamic logic gate 284
Also has the same configuration as the dynamic logic gate shown in FIG. The clock terminal CK is connected to the gate of the high-threshold NMOS transistor 279 which is a transistor for precharging and the gate of the low-threshold PMOS transistor 281 used for stabilizing the operation of the dynamic logic gate (the connection line is (Not shown), a plurality of input terminals Input1, Input2,.
Inputn is connected to a circuit 280 composed of a transistor for evaluation, but the charge storage node C1 connected to the output terminal is omitted for simplicity. Although the internal configuration of the circuit 280 is not specified because it is determined by the function of the gate, the circuit 280 is configured by a low-threshold PMOS transistor that is an evaluation transistor.

The inverter 283 has a high threshold PMOS transistor 277 arranged on the power supply potential side, and a low threshold N
MOS transistor 278 is arranged on the ground potential side. The output terminal of the first dynamic logic gate 282 is connected to the input terminal of the inverter 283, and the output terminal of the inverter 283 is connected to the second dynamic logic gate 2
84 input terminals.

The circuit configuration shown in FIG. 13 utilizes the above-described domino logic. 12 is different from FIG.
The dynamic logic gate used in FIG. 10 is a dynamic logic gate shown in FIG. 10, that is, a dynamic logic gate in which a transistor for precharging is a PMOS transistor having a high threshold value, and a dynamic logic gate used in FIG. The dynamic logic gate shown in FIG. 11, that is, the transistor for precharging is a dynamic logic gate which is a high threshold NMOS transistor.

Here, a low threshold PMOS which is a transistor for evaluation of the first dynamic logic gate 282 is used.
When the circuit 271 including transistors is configured to charge the charge storage node C1 in the evaluation phase, the output signal of the first dynamic logic gate 282 becomes “1”, and the inverter 28 connected to the next stage
3, the low threshold NMOS transistor 278 arranged on the ground potential side is driven, so that the operation speed is increased. Further, as described above, since the evaluation circuits 271 and 280 of the first dynamic logic gate 282 and the second dynamic logic gate 284 are both constituted by low-threshold transistors, the operation speed is increased. Can be

On the other hand, at the time of standby, in the first dynamic logic gate 282 and the second dynamic logic gate 284, both the precharging transistors 270 and 279 are high threshold NMOS transistors. If "0" is set to cut off (turn off) the transistors 270 and 279 for precharging, it is possible to effectively cut the leak current in the path from the power supply potential to the ground potential.

In the standby mode, the circuit 2 composed of a low threshold PMOS transistor which is a transistor for evaluating the first dynamic logic gate 282
71 is configured to charge the charge storage node C1 in the evaluation phase, that is, a plurality of input terminals Input1, Input2,.
When a signal value “0” is given to all of Inputn, its output signal becomes “1”, and the inverter 28 connected to the output of the first dynamic logic gate 282
3, the PMOS transistor 277 having the high threshold voltage disposed on the power supply potential side is cut off (turned off), so that the inverter 283 can effectively cut the leakage current of the path from the power supply potential to the ground potential. As described above, the leakage current can be effectively cut not only in the dynamic logic gate but also in the inverter inserted by the domino logic, and the low power consumption of the circuit is further spurred.

FIGS. 14 and 15 show a seventh embodiment of the present invention using a dynamic logic gate. In FIG. 14, an input of a circuit including a dynamic logic gate is selectively connected to an output of a flip-flop or a latch, or to a power supply potential as a sleep signal. Here, the sleep signal means predetermined signal information (standby state 101) externally given to the circuit during standby.

Dynamic logic gates 302 and 30
Reference numerals 3, 304, 305, and 306 denote low-threshold NMOS transistors whose precharging transistors are high-threshold PMOS transistors and whose input terminals are evaluation transistors.
FIG. 10 is input to a circuit composed of transistors.
This is a dynamic logic gate shown in FIG. In FIG. 14, PMOS transistors 307, 308,
Reference numerals 309, 310 and 311 denote high threshold PMOS transistors for precharging the dynamic logic gates 302, 303, 304, 305 and 306, to which a clock signal Φ is supplied.
15 and 316 are dynamic logic gates 302, 3;
This is an evaluation circuit composed of low threshold NMOS transistors 03, 304, 305, and 306.

The output of the dynamic logic gate 302 is connected to the inputs of the dynamic logic gate 303, the dynamic logic gate 304, and the dynamic logic gate 306, and the output of the dynamic logic gate 305 is connected to the input of the dynamic logic gate 306. It is connected. The input of the dynamic logic gate 302 is
Selectively connected to the output of the flip-flop (FF) 300 or the power supply 317, the dynamic logic gate 305
Is selectively connected to the output of the latch (Latch) 301 or the power supply 318.

The inputs of the dynamic logic gate 302 and the dynamic logic gate 305 are respectively connected to a flip-flop (FF) 300 and a latch (Latch) 301 during the operation of the circuit, and to power supplies 317 and 318 during standby. Connected to. The power supplies 317 and 318 are sleep signals and play a role in fixing the node potential of the entire circuit to the power supply potential during standby. Therefore, during standby, the inputs of the dynamic logic gates 302 and 305 are fixed to the power supply potential, that is, during standby, the signal value “1” is supplied to all inputs of the dynamic logic gates 302 and 305. If the clock signal Φ supplied to the transistors for precharging of the dynamic logic gates 302 and 305 is set to “1”, the output signals of the dynamic logic gates 302 and 305 become “0”. Therefore, when an inverter is inserted between dynamic logic gates using domino logic, a signal value “0” is always input to the inverter, and a signal value “1” is always output from the inverter.
The next-stage dynamic logic gate always has a signal value "1"
Will be supplied. In this case, the inverter shown in FIG. 11 is used in which a low threshold NMOS transistor is arranged on the power supply potential side and a high threshold PMOS transistor is arranged on the ground potential side. Therefore, in the standby mode, not only in the dynamic logic gate but also in the inverter inserted between the dynamic logic gates, the high threshold NMOS transistor is cut off (turned off) and the leakage current of the path from the power supply potential to the ground potential is reduced. Can be effectively cut.

As described above, the standby is performed by using the sleep signal as the power supply potential.
The node potential of the entire circuit, that is, the input signal to each dynamic logic gate can be easily fixed, and stable leakage current can be effectively cut. FIG.
14, the input of a circuit constituted by a dynamic logic gate is selectively connected to the output of a flip-flop or a latch, or to a power supply potential as a sleep signal. Here, the sleep signal is, as described above, predetermined signal information (standby state 1) externally given to the circuit during standby.
01).

Dynamic logic gates 322, 32
11, 324, 325 and 326 are all NMOS transistors with a high threshold for precharging and their input terminals are input to a circuit composed of PMOS transistors with a low threshold for evaluation. ) Is a dynamic logic gate. In FIG. 15, PMOS transistors 327, 328, 329, 3
30 and 331 are dynamic logic gates 332, 3
33, 334, 335, and 336 are high-threshold NMOS transistors for precharging, supplied with a clock signal Φ, and circuits 332, 333, 334, and 335.
And 336 are dynamic logic gates 322, 32
3, 324, 325, and 326 are low-threshold PMOS transistors.

The output of the dynamic logic gate 322 is connected to the inputs of the dynamic logic gate 323, the dynamic logic gate 324 and the dynamic logic gate 326, and the output of the dynamic logic gate 325 is connected to the input of the dynamic logic gate 326. It is connected. The input of the dynamic logic gate 322 is
Selectively connected to the output of a flip-flop (FF) 320 or a ground power supply 337,
The input of 25 is selectively connected to the output of a latch 321 or a ground power supply 338.

The inputs of the dynamic logic gate 322 and the dynamic logic gate 325 are connected to a flip-flop (FF) 320 and a latch (Latch) 321, respectively, when the circuit is operating, and to the ground power supply 337 and the latch (Latch) 321 during standby. 338. The ground power supplies 337 and 338 serve to fix the sleep signal, that is, the node potential of the entire circuit at the time of standby to the ground potential. Therefore, at the time of standby, the dynamic logic gates 322 and 32
5 is fixed to the ground potential, that is, the signal value “0” is supplied to the inputs of the dynamic logic gates 322 and 325 in the standby state, so that the transistor 327 for precharging the dynamic logic gates 322 and 325 is supplied. And 330 are set to "0", the output signals 322 and 325 of the dynamic logic gate have the signal value "1". Therefore, when an inverter is inserted between dynamic logic gates using domino logic, a signal value "1" is always input to the inverter, and a signal value "0" is always output from the inverter. The dynamic logic gate of the stage is always supplied with the signal value “0”. In this case,
The inverter shown in FIG. 12 is used in which a high threshold PMOS transistor is disposed on the power supply potential side and a low high threshold NMOS transistor is disposed on the ground potential side. Therefore, not only in the dynamic logic gate but also in the inverter inserted between the dynamic logic gates,
At the time of standby, the PMOS transistor having the high threshold value is cut off (turned off), and the leakage current of the path from the power supply potential to the ground potential can be effectively cut.

As described above, by setting the sleep signal to the ground potential for standby, the node potential of the entire circuit can be easily fixed at the time of standby, and a stable leak current can be effectively cut.

[0098]

As described above, according to the present invention, an existing CAD system can be easily used. Further, since only cell replacement is performed, the circuit scale does not increase. As described above, according to the present invention, it is possible to effectively suppress the leak current at the time of standby without increasing the circuit scale by using the existing CAD system.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first principle diagram of the present invention.

FIG. 2 is a diagram showing a second principle diagram of the present invention.

FIG. 3 is a diagram showing a first principle diagram of the cell of the present invention.

FIG. 4 is a diagram showing a first embodiment of the present invention.

FIG. 5 is a diagram showing a second embodiment of the present invention.

FIG. 6 is a diagram showing a third embodiment of the present invention.

FIG. 7 is a diagram showing a fourth embodiment of the present invention.

FIG. 8 is a diagram showing a third principle diagram of the present invention.

FIG. 9 is a diagram showing a fifth embodiment of the present invention.

FIG. 10 is a diagram showing a second principle diagram of the cell of the present invention.

FIG. 11 is a diagram showing a second principle diagram of the cell of the present invention.

FIG. 12 is a diagram showing a sixth embodiment of the present invention.

FIG. 13 is a diagram showing a sixth embodiment of the present invention.

FIG. 14 is a diagram showing a seventh embodiment of the present invention.

FIG. 15 is a diagram showing a seventh embodiment of the present invention.

FIG. 16 is a diagram showing a conventional technique.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 Netlist of existing circuit 101 Signal information 102 Internal signal setting means 103 Cell library 104 Cell replacement means 105 New netlist 106 RTL description of existing circuit 107 Information necessary for logic synthesis 108 New RTL description 109 Existing logic in standby Signal value set at each node in the circuit 110 Means for selecting a cell 111 Means for selecting the best cell 112 Cell replacement means 150 First circuit composed of low threshold PMOS transistor 151 Low threshold PMOS transistor Second circuit configured 152 High threshold NMOS transistor 153 Output node 154 High threshold PMOS transistor 155 First circuit configured with low threshold NMOS transistor 156 Configured with low threshold NMOS transistor Second circuit 157 Output node 160 High-threshold PMOS transistor 161 Circuit composed of low-threshold NMOS transistor 162 Low-threshold NMOS transistor 163, 164, 165 Low-threshold NMOS transistor 166 Output node 170 High-threshold NMOS transistor 171 Circuit composed of low threshold PMOS transistors 172 Low threshold PMOS transistors 173, 174, 175 Low threshold PMOS transistors 176 Output nodes 201, 202, 203 D flip-flops 204, 205, 207 First NAND gate 206 Second NAND gates 207, 208 Low threshold PMOS transistor 209 Low threshold NMOS transistor 210 High threshold NMOS transistor 211, 212 High threshold PMO Transistors 213, 214 Low threshold NMOS transistors 208, 209, 210 D flip-flops with scan 211, 212, 214 First NAND gate 213 Second NAND gate 215 Memory 250 High threshold PMOS transistor 251 Low threshold NMOS transistor Circuit 252, 253, 254, 255 Low threshold NMOS
Transistor 256 Output node 257 Low threshold PMOS transistor 258 High threshold NMOS transistor 259 High threshold PMOS transistor 260 Circuit composed of low threshold NMOS transistor 261 Low threshold NMOS transistor 262 First dynamic logic gate 263 Inverter 264 Second dynamic logic gate 270 High threshold NMOS transistor 271 Low threshold PMOS transistor circuit 272, 273, 274, 275 Low threshold PMOS
Transistor 276 Output node 277 Low threshold PMOS transistor 278 High threshold NMOS transistor 279 High threshold NMOS transistor 280 Circuit composed of low threshold PMOS transistor 281 Low threshold PMOS transistor 282 First dynamic logic gate 283 Inverter 284 Second dynamic logic gate 300 Flip-flop 301 Latch 302, 303, 304, 305, 306 Dynamic logic gate 307, 308, 309, 310, 311 High threshold PMOS transistors 312, 313, 314, 315, 316 Low threshold 317, 318 Power supply 320 Flip-flop 321 Latch 322, 323, 324, 325, 326 Dyna Click type logic gates 327,328,329,330,331 circuit constituted by PMOS transistor having a high threshold of the NMOS transistors 332,333,334,335,336 low threshold 337, 338 ground power supply

Claims (20)

[Claims] 1. An internal signal calculation means for receiving logic circuit information and predetermined signal information and calculating a signal value of each node of the logic circuit based on the predetermined signal information; The calculated internal signal,
Cell replacement in which the logic circuit information and cell information in which a cell composed of a high-threshold transistor and a low-threshold transistor is registered are input, and cells in the logic circuit are replaced and new logic circuit information is output. Means, comprising: a cell replacement system. 2. Circuit information described at a transistor level, predetermined signal information, information necessary for logic synthesis, and cell information in which a cell composed of a high threshold transistor and a low threshold transistor is registered. And means for performing logic synthesis, calculating an internal signal for calculating a signal value of each node of the logic circuit based on the predetermined signal information, and replacing cells in the circuit. Cell replacement system. 3. The cell replacement system according to claim 1, wherein the cell replacement also includes a pin replacement process. 4. The cell replacement system according to claim 1, wherein said predetermined signal information is an output signal of a storage element. 5. The cell replacement system according to claim 1, wherein the predetermined signal information is an output signal of a state holding element. 6. The cell replacement system according to claim 4, wherein the predetermined signal information is stored in a memory and sent to each of the chained scan flip-flops. 7. The registered cell information includes a first circuit having a first input terminal formed of a low-threshold first conductivity type transistor and a low threshold value of a second conductivity type transistor. A second input terminal is connected to the first circuit, the second circuit, and a high-threshold first-conductivity-type transistor or a high-threshold second-conductivity-type transistor. The cell replacement system according to claim 1, 2 or 3, wherein the cell replacement system includes a plurality of cells. 8. The registered cell information includes one or a plurality of low threshold transistors provided on a power supply potential side and one or a plurality of high threshold transistors provided on a ground potential side. 4. The cell replacement system according to claim 1, further comprising a NAND gate. 9. The registered cell information includes one or more high-threshold transistors provided on a power supply potential side and one or more low-threshold transistors provided on a ground potential side. 4. The cell replacement system according to claim 1, further comprising a NAND gate. 10. The cell replacement system according to claim 1, wherein said registered cell information includes a static logic gate. 11. An internal signal calculated by said internal signal calculating means, said circuit information, and said registered cell information are inputted, and one or a plurality of cells corresponding to cells in said circuit are obtained from said registered cell information. Means for selecting a plurality of cells, means for selecting one cell from the plurality of selected cells, and cell replacement means for replacing cells in a circuit and outputting new logic circuit information. The cell replacement system according to claim 1, comprising: 12. The pin replacement processing according to claim 1, wherein an input pin of the cell connected to each of a plurality of wirings input to a cell realizing a predetermined logic is replaced with another input pin. 4. The cell replacement system according to 3. 13. The registered cell information includes a high threshold first conductivity type transistor for precharging, and a low threshold second conductivity type transistor connected to one or more input terminals.
4. The cell replacement system according to claim 1, further comprising a cell including a circuit including a transistor of a conductivity type. 14. The cell replacement system according to claim 1, wherein said registered cell information includes a dynamic type logic gate. 15. The cell replacement system according to claim 1, wherein said predetermined signal information is fixed to a power supply potential or a ground potential. 16. The cell according to claim 1, wherein the cell registered in the cell information suppresses a leakage current by shutting off a high threshold transistor in a standby state. Cell replacement system. 17. A cell replacement method for replacing a cell in a circuit and outputting new logic circuit information, wherein the logic circuit information and predetermined signal information are input, and based on the predetermined signal information. A signal value of each node of the logic circuit is set, and the set internal signal, the logic circuit information, and cell information in which a cell including a high threshold transistor and a low threshold transistor is registered are input. And replacing the cells in the logic circuit to output new logic circuit information. 18. A cell replacement method for replacing cells in a circuit and outputting logic circuit information, wherein the method is required for performing logic synthesis of circuit information described at a transistor level and predetermined signal information. Information and cell information in which a cell composed of a high-threshold transistor and a low-threshold transistor are registered are input, logic synthesis is performed, and the signal value of each node of the logic circuit is calculated based on the predetermined signal information. A cell replacement method comprising: calculating an internal signal and replacing a cell in a circuit. 19. A recording medium in which a cell replacement program for replacing cells in a circuit and outputting new logic circuit information is recorded, wherein the logic circuit information and predetermined signal information are inputted, A signal value of each node of the logic circuit is calculated based on predetermined signal information, and a cell including the calculated internal signal value, the logic circuit information, a high threshold transistor and a low threshold transistor is registered. And a cell replacement program that receives the input cell information and replaces the cells in the logic circuit to output new logic circuit information. 20. A recording medium on which a cell replacement program for replacing cells in a circuit and outputting logic circuit information is recorded, comprising: circuit information described at a transistor level; predetermined signal information; Information required for logic synthesis and cell information in which a cell composed of a high threshold transistor and a low threshold transistor are registered are input, and based on the logic synthesis and the predetermined signal information, A recording medium storing a cell replacement program, wherein an internal signal calculation for calculating a signal value of a node and replacement of a cell in a circuit are performed.