JPH11282750A - Cache memory device and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable cache data attribute to be set by a fine unit and to enable high-speed and flexible cache data control even in a system without an address conversion function. SOLUTION: A cache memory device has a data RAM having plural cache lines and a tag RAM for holding tag information and attribute information regarding each cache line. The attribute information of the tag RAM has a flag (v) for indicating the validity/nonvalidity of data in the cache line concerned, a flag (u) for indicating a data write system of either write back or write through and a flag (m) for indicating whether or not data are updated. When access performs cache hit, the access concerned is processed on the basis of corresponding attribute information. This attribute information is stored in a corresponding field of the tag RAM when a cache mistake occurs and new data are stored in a cache line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device and a control method particularly suitable for a computer system not using a virtual storage system.

[0002]

2. Description of the Related Art In general, in a computer system, a request for an instruction fetch or a request for data access issued from a CPU (central processing unit) core in a processor is serviced by peripheral parts other than the CPU core. The process is thereby advanced. Here, R, which stores instructions, data, and the like, are stored in peripheral portions other than the CPU core unit.
It includes a memory device such as an OM / RAM, a bus interface unit that interfaces the memory device with the CPU core unit, and the like. In addition, a memory management mechanism (MMU: memory mana
gement unit) or cache memory.

The MMU is a memory management mechanism used in a computer system using a virtual storage system.
When the CPU core issues an instruction fetch request or a data access request, the MMU replaces the logical address (virtual address) issued to indicate the instruction or data to be processed with the instruction on the computer system. And a physical address indicating the actual location of the data. Such a conversion from a virtual address to a physical address is performed by drawing a table generally called an address conversion table with a virtual address. Each entry of the address translation table often includes not only the value of the physical address corresponding to the virtual address but also attribute values such as write-protection and caching enabled / disabled.
In such a computer system, attributes can be checked at the time of address conversion from a virtual address to a physical address. Based on this check, illegal writing can be prevented, and storage in a cache memory can be prevented. Control.

[0004] The cache memory enables high-speed service for instruction fetch requests and data access requests. The cache memory includes a tag array section and a data array section. At the time of access, the issued address is compared with the address stored in its own tag array unit, and if they match (cache hit), the corresponding data stored in the data array unit is used for the access. Service at high speed. If the address comparisons do not match (cache miss), the data containing the data to be accessed from the memory device
Load the block (cache miss processing). At this time, the address of the data block is stored in the corresponding entry of the tag array section.

In the case of a computer system having an MMU and using a virtual storage system, the attribute of the data of the address is checked at the time of address conversion from a virtual address to a physical address. Therefore, when such a computer system includes a cache memory, the attribute obtained at the time of address translation can be used not only for preventing unauthorized access, but also for controlling the cache. For example, the behavior of the cache memory at the time of write access can be finely controlled by allowing each entry of the address translation table to specify a method of updating the data body in the memory device and a write-through / write-back. It is possible to

[0006]

On the other hand, in the case of a small-scale computer system or a special-purpose computer system, a virtual storage system is often not used. In the case of such a computer system, the address translation itself is not required, and there is no need to check the attributes for each access. Therefore, it is difficult to finely control the data unit of the cache memory as described above. For this reason, for example, when data that requires updating of the data body immediately upon write access, such as display data of a display device, is included in the processing data,
The data area is divided into relatively large units, and the attribute of performing / not performing caching is set statically in the relatively large area unit. Caching is performed for an area requiring immediate update. There is no other way than to adopt a method of setting it as impossible or setting the whole processing area as write-through, which sacrifices high speed and flexibility in cache memory control.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and enables a high-speed and flexible cache data control even in a system without an address translation function by enabling the attribute of cache data to be set in small units. And a control method therefor.

[0008] Another object of the present invention is to provide a cache memory.
By providing a field for storing an attribute in each entry of the memory tag array and appropriately setting this attribute field at the time of cache miss processing, even if the computer system does not use a virtual storage system, the cache
An object of the present invention is to make the memory controllable in small units and maintain the high speed and flexibility of the cache system.

[0009]

According to the present invention, there is provided a cache memory device having the following configuration. A data memory having a plurality of cache lines; a field memory having a field for storing attribute information of stored data corresponding to each of the plurality of cache lines; A cache data processing means for performing a process corresponding to the access based on attribute information obtained from a field corresponding to a cache line in which a cache hit has occurred, and selecting an original data to be accessed when the cache miss occurs in the data memory. Stored in the cache line
Storage means for storing attribute information of the original data in a corresponding field of the field memory.

Further, according to the present invention, there is provided a cache memory control method which achieves the above object.

[0011]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIGS. 1A and 1B are block diagrams showing the configuration of a computer system according to this embodiment. In this computer system, a processor unit (10), a main memory unit (11), and an I / O (imput / output) unit (12) are connected to a system control line (1).
6), a system bus composed of a system address line (17) and a system data line (18).

The I / O unit (12) is connected to input / output devices such as a display device (13), a network (14), and a disk drive (15). The system control line (16) is a signal line used for control / response between units. The signal lines of the system control line (16) are as follows.

Sclk (20) is a clock line for synchronizing system bus transactions. sts *
(21) is a signal indicating that the unit that has become the system bus master is currently executing the system bus transaction. sr / w * (22) is a signal indicating the direction (read / write) of the system bus transaction. ssize1-0 (23) is a 2-bit signal indicating the target data size of the system bus transaction. sburst * (24) is a signal for instructing the target unit to perform a burst access when the system bus transaction is related to a cache miss process or a line replacement process. sta * (25) is an acknowledge signal of a system bus transaction, which indicates that valid data is being output on the system data line (18) in the case of reading, and the system data in the case of writing. A signal indicating that data on line (18) has been received. The protocol of the system bus will be described later.

The system control line (16) is provided with other control / response lines necessary for the present system to operate as a computer system. Here, the present embodiment will be described. Shows only necessary signal lines. Also, the system address line (17) and system data line (18) of the present system are 32 bits wide, but this is not a limitation of the present invention.

The interior of the processor unit (10)
CPU core (100), cache memory (10
1) and a bus interface unit (102)
Are connected to each other by a processor internal bus including a control line (103), an address line (104), and a data line (105).

The control line (103) is a CP
Instruction fetch while U core (100) proceeds with processing,
And a signal line used for control / response of a processor internal bus transaction issued for data access. The signals on the control line (103) are as follows.

Bclk (110) is a clock line for synchronizing processor internal transactions. ts *
(111) is a signal indicating that the processor internal bus master is currently executing a processor internal bus transaction. r / w * (112) is a 2-bit signal indicating the target data size of the processor internal bus transaction. ta * (114) is an acknowledgment signal of a processor internal bus transaction, which indicates that valid data is being output on the data line (105) in the case of reading, and the data line (in the case of writing) 105) is a signal indicating that the above data has been received. tma * (115) is a miss acknowledgment signal of a processor internal bus transaction, and is a signal indicating the occurrence of a cache miss in the cache memory (101). tea * (116) is an error acknowledgment signal of a bus transaction inside the processor, and is used to issue a transaction to an invalid address.
Unit (102) is a signal indicating that a transaction error has occurred. miss_op * (117) is a signal indicating that the current processor internal bus transaction is related to cache miss processing. mem_wr
ite * (118) is a signal for instructing the bus interface unit (102) to reflect the current processor internal bus transaction to the unit on the system bus.

The protocol of the processor internal bus will be described later. Also, the address lines (104) and data lines (105) of the present system are 32 bits wide, but this is not a limitation of the present invention.
The processor unit (10) includes signal lines and processing modules required for the present system to operate as a computer system, such as an interrupt line and an interrupt processing module, and the present embodiment will be described here. Only the necessary signal lines and processing modules are shown above.

The cache memory (101) includes a cache control logic (120) for controlling the cache memory (101), a tag RAM (121) for storing tag information, and a comparison for comparing an address field of the tag information. (122), buffer (123) used when writing tag information, data RAM for storing data
(124), and a data buffer (125). The tag RAM (121), the buffer (123), and the data RAM (124) are connected to the ram_ctrl signal line (130) from the cache control logic (120).
Is controlled by The ram_ctrl signal line (130) includes the following signals. That is, en of the buffer (123)
able signal (131), trcs * signal (132) as a chip selection signal of tag RAM (121), troe * signal (133) as an output control signal, trwe * signal (134) as a write control signal, data RAM The data_cs * signal (135), which is the chip selection signal of (124), and the output control signal
data_oe * signal (136), data_w which is a write control signal
e3 * -0 * signal (137). data_we3 * -0 * signal (13
7) is a 4-bit signal, where each bit corresponds to each byte of 4-byte data.

The address is input via a caddr31-2 signal line (140). The tag RAM 121 has taga14-0 (1
42) as addr31 on the address line (104)
-17 part 15 bits are provided to the comparator (122) and the buffer (123) by the addr on the address line (104).
13 bits (141) of the 16-4 portion are stored in the data RAM 124
As the dataa16-0, 17 bits of an address obtained by concatenating the addr31-17 part and the addr3-2 part on the address line (104) are input.

In the tag RAM 121, tagd15-0 (1
50) is input and output. tagd15-0 (150) is divided into a 13-bit tag address field (151) and a 3-bit line status (152), and the tag address field (151) is a comparator (122) and a buffer (123). Connected to the line status (1
52) is the cache control logic (12)
0).

The comparator (122) has a tag RAM (12)
The tag address field (15) output from 1)
1) is compared with the address (141) output from the cache control logic, and the result is compared with cmp_ma
The cache control logic (120) is notified by the tch * signal (153). buff_ctrl signal (161)
Is an enable signal for the data buffer (125), asserts the buff_roe * signal (162) when data is output from the data RAM (124) to the data line (105), and outputs the signal on the cdata31-0 signal line (160). Data is output on the data line (105) and the data RAM (1
05) Output the data on the cdata31-0 signal line (160). The cache control logic (120) has a data port (164).
Data7-0 of the data line (105) is connected.

FIG. 2 is a diagram showing the field structure of the address addr31-0 output on the address line (104). In the cache memory (101), ad
The part of dr31-17 (line selection field) is used for selecting a cache line, the part of addr16-4 (tag field) is used for comparison in the comparator (122), and
The part of dr3-0 (intra block field) is treated as an address in the block indicating which part of the data block stored in the cache line is accessed.

FIG. 3 is a diagram showing a logical configuration of the cache memory (101). In the tag RAM (150),
A v flag indicating whether the cache line is valid, a u flag indicating when to update a data block stored on the cache line,
The m flag indicating whether or not the content of the data block stored on the cache line is different from the content of the original, and the tag field corresponding to the address addr16-4 are included in the cache line # 0. ~ # 327
Up to 67 32k entries are stored. Data R
AM (124) has 16B for each cache line
(Byte) data is stored. The cache memory (101) of the computer system has a 32k entry direct map system and a capacity of 512k bytes (16 bytes x 32k entries), but this structure does not limit the present invention.

Hereinafter, the operation of the present system will be described. FIG.
5 is a flowchart showing processing by the cache control logic when the CPU core issues a processor internal bus transaction for instruction fetch or data access. When the processor internal bus transaction is issued, the cache control logic (120) decodes the address to determine whether or not the transaction should be passed through the cache memory (101) (step S20).
1). Here, the transaction that should not be passed through the cache memory (101) is a transaction that targets the inside of the cache control logic (120) (described later). In the case of such a transaction, a corresponding access operation is performed (step S202), and this processing ends.

On the other hand, if the transaction is a transaction to be performed via the cache memory (101), a cache access operation is performed (step S204). If a cache miss has occurred, the process proceeds from step S205 to step S206, where the transaction is temporarily terminated (step S206), and a cache miss process is performed (step S207). The cache miss processing will be described later with reference to the flowchart of FIG.

If the cache access hits, the flow advances from step S205 to step S209 to determine whether the access is read or write. If the access is read, the process proceeds to step S210, and data is read from the data RAM 124. If the access is a write, the process proceeds to step S212, and it is determined whether the write method of the data block specified by the access is write-through or write-back (tag RAM).
Judgment is made by the flag “u” stored in 121). If it is write-through, step S2
Then, the process proceeds to step 13 to write data to both the data RAM 124 and the main memory unit 11. If the write method is write-back, the data RA
Write data only to M124.

Next, the cache miss processing in step S207 will be described. FIG. 5 is a flowchart illustrating a processing procedure when a cache miss occurs.

In this example, since the direct map method is employed, when a cache miss occurs, it is uniquely determined which cache line stores the data.
In the case of another full associative method or the like, a cache line for storing data is determined by the LRU method or the like.

When a cache miss occurs, it is determined whether or not a cache line for storing new data is empty (step S301). If this cache line is empty, the CPU core (100)
Notifies the cache control logic (120) of the attribute of the new data block to be stored in the cache memory (101) (step S302). Then, a processor internal bus transaction for reading the data block is issued (step S).
303).

The bus interface unit (10
2) issues a system bus transaction on the system bus in the form of an intermediary, and the main memory
Read a data block from unit (11). The cache memory (101) is connected to the processor internal bus 1
6B (byte) data is stored in the data RAM (1
24) (Steps S304 to S30)
7), complete the cache miss process.

FIG. 6 is a timing chart showing the timing of each signal on the processor internal bus and the system bus when a cache miss occurs. Transaction 400 is the transaction that caused the cache miss. The cache memory tma * signal (115) is asserted, terminating transaction 400. The transaction 401 is executed by the CPU core (10
0) is a read transaction for knowing the attribute of a data block newly stored in the cache memory (101) in response to a cache miss, which results in a cache hit and the cache memory (101).
Asserts the ta * signal (114) to service attributes to the CPU core. The attribute data includes a write method (write-through / write-back) when a write transaction is performed on the data block. When a cache miss occurs in the transaction 401, the processing described here is performed in the same manner, and then the processing operation for the cache miss of the transaction 400 is performed.

The transaction 402 is a transaction for the CPU core (100) to transmit the attribute information of the data block obtained in the transaction 401 to the cache control logic (120). Since the cache control logic (120) determines that this transaction is a transaction that does not pass through the cache memory (101), the tag RAM inside the cache memory (101)
(121) and the operation of accessing the data RAM (124) are not performed. Note that the attribute information may be stored in the memory for each successive 16B, but a large amount of memory capacity is required, so that the data attribute from a certain address to a certain address is as follows. It is preferable to use a typical one. In general, in a small-scale system, for example, if the value of the upper 4 bits of the address is 0, the ROM is 1, if the value of the upper 4 bits is the RAM, and if the value of the upper 4 bits is 2, the V is
In the case of the RAM 3, the module is often divided by the upper few bits of the address, such as a serial line. Therefore, by accessing the base address of the attribute table with an address obtained by concatenating the upper few bits of the address for identifying the module, a desired data attribute can be obtained.

The transaction 403 is a transaction for reading the data block from the main memory unit (11). miss_op * signal (11
Since (7) is asserted, the cache memory (101) performs a normal internal access operation (CPU core (1)
00) is not performed.
The bus interface unit (102) has miss_o
Based on the p * signal (117) being asserted,
It mediates transaction 403 and issues transaction 404 on the system bus. In transaction 404, the sburst * signal (24) is asserted.

The main memory unit (11) has 4
B data is serviced four times, for a total of 16 B data to the bus interface unit (102). Data is transferred on the system bus in synchronization with the sclk signal (20). Bus interface unit (102)
Asserts the ta * signal (114) and outputs the data on the data line (105) in synchronism with the bclk signal (110) each time 4B of data is serviced from the system bus. I do. The cache memory (101) takes the data output on the data line (105) into its corresponding cache line.

FIG. 7 is a timing chart showing the timing of signals inside the cache memory (101) when a cache miss occurs. The signals 400 to 400 in FIG.
403 represents the same signals as those of FIG.

When transaction 400 is issued,
The cache control logic (120) is tr
addr31-17 is output to a14-0 (142), and the trcs * signal (1
32) and the troe * signal (133) are asserted, and the tag RA
M (121) is read-accessed. Further, addr16-4 is output to the signal line 141 connected to the comparator. At the same time, addr31-17 and ad are added to dataa16-0 (143).
Outputs the address where dr3-2 is concatenated, data_cs
The * signal (135) and the data_oe * signal (136) are asserted, and the data RAM (124) is read-accessed. From the tag RAM (121), the corresponding cache
The tag information stored in the line is tagd15-0 (150)
Output above.

The tag address field (1
51) are compared on a comparator (122) and
The status (152) is communicated to the cache control logic (120). At this time, the comparator (1
If the cmp_match * signal (153), which is the comparison result of 22), is not asserted, or if the line status (15
A case where the v flag is not set in 2) is a cache miss.

In the case of FIG. 7, the cmp_match * signal is not asserted, and a cache miss has occurred. Therefore, the cache control logic (120) uses tm
Assert the a * signal (115), transaction 40
Terminate 0 and CPU core (100)
Is notified of the occurrence of a cache miss.

CPU detecting occurrence of cache miss
The core (100) issues a transaction 401 to obtain attribute information. The tag RAM is used for the transaction 401 in the same manner as the transaction 400.
(121) and an access operation to the data RAM (124) are performed. In this example, this time the comparator (122)
The comparison result cmp_match * signal (153) is asserted,
There is a cache hit. The cache control logic (120) outputs data on the data line (105) by asserting the biff_roe * signal (162) of the buff_ctrl signal (161).
* Data is being serviced to the CPU core by asserting the signal (114).

For the transaction 402, the cache control logic (120) determines that the transaction does not pass through the cache memory (101), so that the tag RAM (121) and the data RAM (121) are stored inside the cache memory (101). No access operation to the cache control logic (124) is performed, and the cache control logic (120) receives the attribute information from the CPU core and terminates the transaction by asserting the ta * signal (114). Since the miss_op * signal (117) is asserted for the transaction 403, the cache control
Logic (120) detects that the transaction is for reading a data block in which a cache miss has occurred. And the trcs * signal (132) and dat
a_cs * signal (135) is asserted, and the attribute information of the data block obtained by the transaction 402 is output to the line status signal line (152).
Outputs dr16-4 to address line 141. And
The tag information is output on the tagd15-0 signal line (150) by asserting the enable signal (131) of the buffer 123, and the data line (105) is asserted by asserting the buffer_woe * signal (163). Connect the cdata32-0 signal line (160) and wait for the bus interface unit (102) to terminate transaction 403.

The bus interface unit (10
2) sequentially outputs data on the data line (105) by 4B and asserts the ta * signal (114), and the cache control logic (120) executes data_w
Output L pulse to e3 * -0 * signal (137) (data_we3
By asserting the * -0 * signal (137) and then negating), the data is sequentially stored on the corresponding line of the data RAM (124).

When fetching the first 4B data, tr
L pulse is output to we * signal (134) and tag RAM
(121) Tag information is stored on the line. Waiting and storing the assertion of the ta * signal (114) from the bus interface unit (102) is because the transactions 400 and 403 may be transactions for addresses that are not valid. In such a case, the bus interface unit (10
2) asserts the tea * signal (116) without asserting the ta * signal (114), thereby terminating the transaction in error, and the cache control logic (120) stores the new data block. Cancel. The CPU core (100) performs an abort process (steps S304 and S305 in FIG. 5).

Returning to the flow when a cache miss has occurred in FIG. If the cache line is not empty in step S301, step S30
Before entering the processing of the second and subsequent steps, the processing of steps S309 and S310 is executed in order to maintain data consistency.

First, in step S309, it is determined whether or not the content of the data block stored on the cache line is different from the content of the original. If the contents of the data block are different from the contents of the original, the contents of the original need to be updated. Such a situation is caused by the u in the tag information of the data block.
The flag is in write-back mode and its data
Occurs when data is written to a block. Whether or not the data of the data block stored on the cache line is different from the original content can be determined by checking the m flag in the tag information.

Therefore, the data block on the cache line is cached by the write-through method (in this case, the content of the original and the content of the data block on the cache line match) or the content of the original If the state has not changed, the process proceeds from step S309 to step S302. If the content is different from the original, the process proceeds to step S310.
An update operation of the original is performed.

FIG. 8 is a timing chart showing a state transition of the signal lines of the processor internal bus and the system bus when data write back of the cache line is required when a cache miss occurs.

In FIG. 8, transaction 500 is a transaction that caused a cache miss, and the operation is the same as that for transaction 400 described above. The difference is that the cache control logic (120) asserts the tma * signal (115) indicating that a cache miss has occurred, and
asserting the ite * signal (118). tm
Upon detecting the simultaneous assertion of the a * signal (115) and the mem_write * signal (118), the CPU core (100) sets the right to use the processor internal bus to the cache memory (10).
Yield to 1).

The cache control logic (1
20) issues a write transaction 501 in the form of asserting the miss_op * signal (117) and the mem_write * signal (118). Since the miss_op * signal (117) is asserted, the bus interface unit (102) detects that the access is 16B, and
6B data sequentially 4B data lines (105)
And terminates the transaction 501. When the transaction 501 is terminated, the cache control logic (120)
Negates the mem_write * signal (118) and returns the right to use the processor internal bus to the CPU core (110).

On the other hand, on the system bus, the bus interface unit (102) issues the transaction 505 in response to the transaction 501, and the termination operation completes the update operation of the original data block. Hereinafter, transactions 502 and 5
03, 504, and 506 are issued, respectively, for transactions 401, 402, 4
Operations similar to those in steps 03 and 404 are performed, and the cache miss process is completed.

As described above, each cache line in the cache memory (101) stores a data block and its tag information.

FIG. 9 shows that the u flag in the tag information is
The back mode indicates the operation at the time of a write hit to a data block indicating that the m flag is not different from the original content. The cache control logic (120) that has read-accessed the tag RAM (121) and detected the cache hit,
_we3 * -0 * signal (137) is asserted and the tag RAM (1
21) is written to the data block. Further, in this case, after read access to the tag RAM (121), write access to the tag RAM (121) is performed,
The m flag in the tag information of the cache-hit data block in the tag RAM (121) is updated so as to indicate that it is different from the original.

FIG. 10 shows an operation at the time of a write hit to a data block in which the u flag in the tag information is in the write-through mode. The point that the cache control logic (120) writes to the data block in the data RAM (124) is the same as in the write-back mode. However, in this case,
The self-assertion of the ta * signal (114) is not performed.
Asserting the te * signal (118) urges the bus interface unit (102) to perform a write operation on the original data block. The bus interface unit (102) includes a data line (105)
The transaction 601 is terminated by fetching data from above and asserting the ta * signal (114). Continue with the bus interface unit (1
02) is a transaction 601 on the system bus.
Is issued to perform a write operation to the original data block.

As described above, according to the present embodiment, in a computer system using a processor unit having no memory management unit (MMU) in hardware or a computer not using a virtual storage system, Performance can be improved. That is, conventionally, light data such as display data of a display device is used.
When data requiring immediate data update during access is included in the processing data, in a computer system without a virtual storage system, all data stored in the cache memory is handled in the write-through mode or compared. Can be cached for each area divided into large units /
The only option was to set the load statically and run. On the other hand, according to the present embodiment, the cache attribute is registered in the tag information of the cache line in the course of the miss processing performed when a cache miss occurs. , It is possible to finely manage the caching attribute in units of the size of the data blocks stored in the data block, thereby improving the system performance.

The present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), but can be applied to a single device (for example, a copier, a facsimile). Device).

An object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or apparatus, and to provide a computer (or CPU) of the system or apparatus.
And MPU) read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0062]

As described above, according to the present invention,
Even in a system having no address translation function, the attribute of cache data can be set in small units, and high-speed and flexible cache data control can be performed.

According to the present invention, a field for storing an attribute is provided in each entry of the tag array of the cache memory, and this attribute field is appropriately set at the time of cache miss processing. Even if the computer system does not have a cache memory, the cache memory can be controlled in small units, and the high speed and flexibility of the cache system can be maintained.

[0064]

[Brief description of the drawings]

FIG. 1A is a block diagram illustrating a configuration of a computer system according to the present embodiment.

FIG. 1B is a block diagram illustrating a configuration of a computer system according to the present embodiment.

FIG. 2 is a diagram showing a field configuration of an address addr31-0 output on an address line (104).

FIG. 3 is a diagram showing a logical configuration of a cache memory (101).

FIG. 4 is a flowchart showing processing by the cache control logic when the CPU core issues a processor internal bus transaction for instruction fetch or data access.

FIG. 5 is a flowchart illustrating a processing procedure when a cache miss occurs.

FIG. 6 is a timing chart showing timings of signals on a processor internal bus and a system bus when a cache miss occurs.

FIG. 7 is a timing chart showing the timing of signals inside the cache memory when a cache miss occurs.

FIG. 8 is a timing chart showing a state transition of signal lines of a processor internal bus and a system bus when a write back of a cache line is required when a cache miss occurs.

FIG. 9 is a timing chart showing an operation at the time of a write hit to a data block in which the u flag in the tag information indicates the write-back mode and the m flag indicates that the content is not different from the original content. .

FIG. 10 is a timing chart showing an operation at the time of a write hit for a data block in which the u flag in the tag information is in the write-through mode.

Claims (16)

[Claims] 1. A data memory having a plurality of cache lines; a field memory having a field for storing attribute information of stored data corresponding to each of the plurality of cache lines; A cache data processing means for performing a process corresponding to the access based on attribute information obtained from a field corresponding to a cache line in which a cache hit has occurred; and Storage means for storing the attribute information of the original data in a corresponding field of the field memory in a selected cache line of the memory. 2. The cache memory device according to claim 1, wherein the attribute information includes a data update method. 3. The cache memory device according to claim 2, wherein said attribute information indicates one of a write-back method and a write-through method as a data update method. 4. The cache data processing means, when a write occurs to a cache line whose attribute information indicates write-through, writes the data to the cache line and updates the corresponding original data. The cache memory device according to claim 3, wherein the cache memory device performs the operation. 5. The cache memory device according to claim 1, wherein the attribute information includes information indicating whether data stored in a corresponding cache line has been updated by a cache hit. 6. The cache memory device according to claim 1, wherein the attribute information includes information indicating whether data stored in a corresponding cache line is valid or invalid. 7. The storage means, when cache data exists in a cache line in which new original data is to be stored, executing write-back of the cache data based on attribute information corresponding to the cache line. The cache memory device according to claim 1, wherein: 8. A field for storing the attribute information,
2. The cache memory device according to claim 1, wherein a part of the tag data corresponding to the data memory is configured. 9. A cache comprising: a data memory having a plurality of cache lines; and a field memory having a field for storing attribute information of stored data corresponding to each of the plurality of cache lines. A method of controlling a memory device, comprising: a cache data processing step of performing a process corresponding to an access based on attribute information obtained from a field corresponding to a cache line having a cache hit when the access is a cache hit; Storing the original data to be accessed in the selected cache line of the data memory in the case of a mistake, and storing attribute information of the original data in a corresponding field of the field memory. Cache memory control method. 10. The cache memory control method according to claim 9, wherein the attribute information includes a data update method. 11. The cache memory control method according to claim 10, wherein said attribute information indicates one of a write-back method and a write-through method as a data update method. 12. In the cache data processing step, when a write occurs to a cache line in which the attribute information indicates write-through, data is written to the cache line and the corresponding original data is updated. 12. The method according to claim 11, wherein
3. The cache memory control method according to 1. 13. The cache memory control method according to claim 9, wherein said attribute information includes information indicating whether data stored in a corresponding cache line has been updated by a cache hit. 14. The cache memory control method according to claim 9, wherein said attribute information includes information indicating whether data stored in a corresponding cache line is valid or invalid. 15. In the storing step, when cache data exists in a cache line in which new original data is to be stored, write-back of the cache data is executed based on attribute information corresponding to the cache line. 10. The cache memory control method according to claim 9, wherein: 16. The cache memory control method according to claim 9, wherein the field for storing the attribute information forms a part of the tag data corresponding to the data memory.