JPH11282403A - Method for displaying image and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an animation fake contour by means of sub-field display by alternately impressing an N bit gradation frame and an N-1 bit gradation frame. SOLUTION: An analog video signal is converted into an eight-bit gradation digital data, for example, by an A/D converting part 1 and the converted data is converted into a seven-bit gradation being different from the eight-bit one by a data converting part 2. Horizontal synchronizing and vertical synchronizing control signals are inputted to a main control part 4 and the control signals for the timing control of a whole are outputted and supplied to a change-over part 3. Digital data converted into two kinds of bit gradations is inputted to the part 3 and data with one of them are outputted by the signal from the main control part 4. Then, the eight-bit gradation frame and the seven-bit gradation frame are alternately impressed on a PDP display device 8 so that the fake contour is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display method and an image display apparatus in which one frame is composed of a plurality of subfields having different relative ratios of luminance to display a multi-gradation video signal. is there.

[0002]

2. Description of the Related Art PDPs (Plasma Display Panels) and ELs have attracted attention as thin and lightweight image display devices.
An image display method used for an (electroluminescent) display or the like only turns on or off a pixel by a digitized video input signal, that is, only 1 or 0 operation. For this reason, the luminance gradation emitted from the panel surface is determined by the number of bits of a signal to be handled. To change the luminance, it is necessary to change the number of discharges (lighting) per unit time.

Hereinafter, the PDP will be described. Regarding the gradation display in this case, a method of 256 gradations by a separate address / display type has been proposed. The address / display separation type is a method in which n-bit input data is lit at a constant luminance for a weighted time of each bit in one frame.

FIG. 6 shows a panel structure of a PDP 101 described in, for example, Japanese Patent Application Laid-Open No. 7-140922, and a driving sequence and driving waveforms are shown in FIGS. 7 (a) and 7 (b). In FIG. 6, the display glass substrate 1 on the display surface side is shown.
A pair of scanning / sustaining electrodes (hereinafter, referred to as X electrodes) 112 and sustaining electrodes (hereinafter, referred to as Y electrodes) are provided on the lower surface of 11.
113 is formed by a transparent electrode and an auxiliary electrode. In this auxiliary electrode, a bus electrode 123 is formed on a part of the transparent electrode in order to prevent a voltage drop due to the resistance of the transparent electrode. These X electrodes 1
12. A dielectric layer 114 is provided on the Y electrode 113, a stripe-shaped rib 115 is formed thereon to separate coupling between cells, and a protective layer 116 is deposited.

An address electrode 118 is formed on the opposite back glass substrate 117. R (red) phosphor 119, G (green) phosphor 120, and B (blue) phosphor 1 are provided with stripe-shaped ribs 115 between address electrodes 118 so as to cover address electrodes 118.
21 is formed by coating. For example, N
A mixed gas such as e + Xe is sealed.

In FIG. 7A, one frame has a relative luminance ratio of 1, 2, 4, 8, 16, 32, 64, 128.
, And display of 256 gradations is performed by combining the luminances of the eight subfields SF1 to SF8. In FIG. 7B,
Each of the subfields SF1 to SF8 includes an address period for writing data for one screen and a luminance level determination period for determining a luminance level of the subfield.

Next, the operation will be described. In the address period, wall charges are initially formed on each pixel at the same time for the entire screen, and then pulses are applied to the X electrode 112 and the Y electrode 113 to perform display. The brightness of the subfield is proportional to the number of pulses, is set to a predetermined brightness, and 256 gradation display is realized. Thus, as the number of gradations increases,
Since the number of bits in the address period as a preparation period for lighting and emitting a pulse within one frame period increases, the emission period becomes relatively short, and the maximum luminance decreases. Also, the address power increases because the number of addresses increases.

Accordingly, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. Therefore, if the number of bits of the signal to be handled is increased, the image quality is improved, but the emission luminance is reduced and the signal to be handled is conversely. If the number of bits is reduced, the light emission luminance increases, but the gradation display decreases and the image quality deteriorates.

[0009]

The image display method and the image display device of the plasma display, which are examples of the conventional image display device, are configured as described above.
As shown in FIG. 9, when the eye tracks the image 11 in which the gradation changes smoothly from the position A to the position B, FIG.
As shown in FIG. 9, the subfield SF (region R in FIG. 9) in the adjacent field is seen overlapping (interfering) (especially when the subfield of a large bit is switched. There is a problem that the interference 12 (which occurs at the boundary of the key) causes a disturbance 12 called a false contour (which is different from a false contour due to insufficient gradation, which occurs in a low-level signal, that is, in a dark image display, etc.). The mechanism of the generation of the false contour is described in, for example, THE INSTITU issued by the Institute of Electronics, Information and Communication Engineers.
TE OF ELECTRONICS, INFORMA
TION AND COMMUNICATION EN
GINEERS, pp. 67 to 72, “Color Disorder and False in PDP Moving Image Display” and FUJITSU. 4
7.4. (07.1996) Published pages 338 to 3
Page 44, "42-inch color plasma display" and the like.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to provide an image display method and an image display apparatus in which false contours of a moving image are reduced by subfield display.

It is another object of the present invention to provide an image display method and an image display apparatus which reduce false contours of moving images and reduce flicker.

Further, while reducing false contours of moving images,
It is an object of the present invention to obtain an image display method and an image display device with stable luminance.

[0013]

An image display method according to the present invention applies an N-bit gradation frame and an (N-1) -bit gradation frame alternately.

According to the image display method of the present invention, the most significant bit of an N-1 bit gradation frame is divided into two and the most significant bit is divided before and after the scanning order of the subfields constituting the frame. It is.

In the image display method according to the present invention, the number of light emission cycles of the least significant bit of an N-bit gradation frame is represented by a, (N
-1) The value of 2 ^N × a and the value of 2 ^(N−1) × b are substantially equal, where b is the number of light emission cycles of the least significant bit of the frame of the bit gradation.

The image display device according to the present invention is characterized in that the data conversion means converts N-bit grayscale frame data into (N-1) -bit grayscale frame data, and the control signal from the main control means. N-bit gradation data and (N
-1) switching means for alternately outputting bit gradation data, and the frame memory means stores the N-bit gradation data and the (N-1) -bit gradation data output from the switching means. Then, it is supplied to the display driving means.

According to the image display apparatus of the present invention, based on the control signal from the main control means, the sequence of the light emission cycle a of the least significant bit in the frame data of N-bit gradation is
In the frame data of (N-1) -bit gradation, there is provided a sequence generating means for outputting the sequence of the light emission cycle b of the least significant bit to the driving means and the frame memory means.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a PDP display device as an example of a very suitable image display device to which the image display method according to the first embodiment of the present invention is applied.
1 is an A / D (analog / digital) converter for converting an analog video signal (R, G, B) into a digital video signal, and 2 is an 8-bit gray scale digital video signal output from the A / D converter 1 A data conversion unit (data conversion means) for converting the digital video signal into a 7-bit gray-scale digital video signal, and outputs an 8-bit gray-scale digital video signal based on a control signal from a main control unit (main control means) 4. A switching unit (switching unit) that switches between outputting a 7-bit grayscale digital video signal and a sequence generating unit (sequence generating unit) that selects a sequence A and a sequence B based on a control signal from the main control unit 4 ), 6 are frame memories (frame memory means) for storing the outputs of the switching unit 3 and the sequence generation unit 5, and 7 is a PD based on an output signal from the frame memory 6. Driving unit for driving the 8 (driving means)
It is.

Next, the operation will be described. The analog video signal is converted into digital data of, for example, 8-bit gradation by the A / D converter 1 so that the digital data has a maximum of 212 gradations. The obtained 8-bit grayscale digital data is converted by the data converter 2 into bits different from the 8-bit grayscale. In the illustrated example, the 7-bit gradation is used, and linear conversion is performed so that the maximum value 127 of the 7-bit gradation is equal to 212 of the 8-bit gradation.

A control signal such as a horizontal synchronizing signal and a vertical synchronizing signal is input to the main control unit 4 and outputs a control signal for performing overall timing control.
Supplies a control signal for controlling when to output which bit gradation data out of the data converted into two types of bit gradations. The switching unit 3 receives digital data converted into two types of bit gradations and outputs data of one of the bit gradations according to a signal from the main control unit 4.

The sequence generator 5 has a built-in sequence A and a sequence B corresponding to two types of bit gradation conversion, and outputs one of the sequences in accordance with a signal from the main controller 4. FIG. 2 shows sequence A and sequence B
In the sequence A, the number of light emitting cycles of the least significant bit is a = 2 in the 4-bit gray scale, and the sequence B is the number of light emitting cycles of the least significant bit in the sequence B = 5 in the 3-bit gray scale. Here, there is a relationship of a <b.

The frame memory 6 receives and stores a digital video signal from the switching unit 3, and outputs data of individual bit gradations specified by the sequences A and B output from the sequence generation unit 5 to the driving unit. 7 sequentially (this order does not mean the order of the digits, but means that some bits are in the specified order).

The driving section 7 outputs a voltage having a waveform necessary for activating the PDP 8 in response to a sequence signal from the sequence generating section 5 to all terminals of the PDP. At this time, in order to display an image according to the video signal, the PDP 8 is generated based on data sequentially output from the frame memory 6.
A write signal designating ON / OFF for each pixel is output.

As described above, according to the first embodiment, the regularity of the power of 2 is broken, and interference between adjacent subfields at a specific gradation boundary is less likely to occur, so that the line of sight moves on the screen. When tracking an image in which the gradation changes smoothly, even in a situation in which temporally adjacent subfields are superimposed (interfering) with each other, the subfield configuration differs for each frame. It is clearly visible where the subfield switches. That is, an effect is obtained in which false contours generated at the boundary of a specific gradation can be reduced.

Embodiment 2 FIG. 3 is a diagram showing a subfield configuration of 8-bit and 7-bit frames when N = 8 in an N-bit gray scale. The horizontal direction in the figure schematically shows the arrangement of the subfields, and the subfields correspond to the length of the black portion in the horizontal direction in which the weight of the luminance is horizontal. The order of the subfield is the leftmost maximum bit
From the right to the right, the lower bits become one by one. For example, the gradation 15 in the case of 7 bits is 00 in a binary system.
Since it is 01111, the lower 4 bits of the 7 bits are represented by a connected length. In the vertical direction of the figure, all displayable gradations are arranged in ascending order from top to bottom.
Although the figures of 7 bits and 8 bits are shown together, almost the same number of times of light emission, that is, gradations corresponding to almost the same luminance are adjacent to each other. Therefore, when displaying a still image, combinations (frames) of adjacent subfields are alternately displayed. FIG. 4 is an enlarged view of a low gradation portion corresponding to the upper part of FIG. Now,
As described above, when the false contour is reduced by alternately applying the frames of the sequences A and B having different bit gradations from the frame memory 6, when the portion A shown in FIG. 3 is a still image, for example, about 1/60 second In the same state continuously, which may cause flicker. Therefore, in the second embodiment, the most significant bit, that is, SF7 is replaced with SF7-1, SF7-
2 and the scanning order of SF1 to SF7 is S
F7-1, SF1, SF2, SF3, SF4, SF5,
The scene shown in FIG. 2 rearranged like SF6 and SF7-2
In this case, Kens B 'is used. Then, from the sequence generator 5 via the frame memory 6, FIG.
By alternately selecting and outputting the frames of the sequence A and the sequence B 'shown in the above, substantially the same luminance can be stably obtained in any case.

As described above, according to the second embodiment, the uppermost SF8 is divided, the scanning order of SF1 to SF8 is rearranged, and the display state is changed as shown in FIG. For example, for about 60 seconds, the same state is not continuously maintained, and the user turns on and off repeatedly. As a result, an effect is obtained in which false contours are reduced and flicker is also reduced.

Embodiment 3 In the first embodiment, the bit gradation is changed for each frame. However, the luminance of a frame in which the bit gradation is reduced is reduced.
Therefore, in the case of the 7-bit gray scale, the sequence B in which the number of light emission of the least significant bit is “5” is set, and in the case of the 8-bit gray scale, the sequence A in which the number of light emission of the lowest bit is “3”
It is assumed that. As a result, in the case of 7-bit gradation, 1
27 × 5 = 635, 212 × 3 = 8-bit gradation
636, resulting in substantially the same gray scale, with only one difference in the number of times of light emission.

As described above, according to the third embodiment, in order to reduce false contours, even if the bit gradation is changed for each frame, the gradation is made substantially equal, that is, the luminance is made substantially equal. The effect that can be obtained is obtained.

[0029]

As described above, according to the present invention, an N-bit gradation frame and an (N-1) -bit gradation frame are alternately applied, so that a false contour can be reduced. There is an effect that can be.

According to the present invention, the most significant bit of an N-bit gray scale frame is divided into two, and the most significant bit is divided before and after the scanning order of the subfields constituting the frame. There is an effect that the contour can be reduced and the flicker can also be reduced.

According to the present invention, when the number of light emitting cycles of the least significant bit of an N-bit gradation frame is a and the number of light emitting cycles of the least significant bit of a (N-1) bit gradation frame is b, Since the value of 2 ^N × a and the value of 2 ^(N−1) × b are configured to be substantially equal, there is an effect that false contour can be reduced and luminance can be stabilized.

According to the present invention, the data converting means for converting the frame data of the N-bit gradation into the frame data of the (N-1) -bit gradation, and the N-bit gradation based on the control signal from the main control means. Switching means for alternately outputting tone data and (N-1) -bit gradation data, wherein the frame memory means outputs N-bit gradation data and (N-1) -bit data output from the switching means. Since the gradation data is stored and supplied to the driving means of the plasma display, there is an effect that the false contour can be surely reduced by a simple structure.

According to the present invention, based on the control signal from the main control means, in the frame data of the N-bit gradation, the sequence of the light emission cycle number a of the least significant bit is represented by (N-1)
In the frame data of the bit gradation, the sequence of the number of emission cycles b of the least significant bit is provided to the driving means and the sequence generating means for outputting the sequence to the frame memory means. In addition, there is an effect that the luminance can be stabilized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a PDP display device to which a PDP display method according to a first embodiment of the present invention is applied.

FIG. 2 is an explanatory diagram showing an example of a sequence position.

FIG. 3 is a display state diagram according to the first embodiment of the present invention.

FIG. 4 is an enlarged view of a low gradation portion corresponding to an upper part of FIG. 3;

FIG. 5 is a display state diagram according to a second embodiment of the present invention.

FIG. 6 is a panel structure diagram of a PDP.

FIG. 7 is a drive sequence and a drive waveform diagram of the PDP.

FIG. 8 is a diagram illustrating the generation of a false contour.

FIG. 9 is an explanatory diagram of a false contour generated in a display image.

[Explanation of symbols]

2 data conversion unit (data conversion unit), 3 switching unit (switching unit), 4 main control unit (main control unit), 5 sequence generation unit (sequence generation unit), 6 frame memory (frame memory unit), 7 driving unit (Drive means).

Claims (5)

[Claims] In an image display method in which one frame is composed of a plurality of subfields having different relative ratios of luminance and a multi-gradation video signal is projected, an N-bit gradation frame and (N- 1) An image display method characterized by applying frames of bit gradation alternately. 2. The method according to claim 1, wherein the most significant bit of the frame of the N-bit gradation is divided into two, and the divided most significant bit is allocated before and after the scanning order of the subfields constituting the frame. Image display method. 3. When the number of light emitting cycles of the least significant bit of an N-bit gradation frame is a and the number of light emitting cycles of the least significant bit of a (N-1) bit gradation frame is b, 2 ^N × a And a value of 2 ^(N-1) × b are made substantially equal. 4. An N-bit gradation frame data is expressed by (N-
1) Data conversion means for converting to frame data of bit gradation, and the N-bit gradation data and the (N-1) -bit gradation data are alternately output based on a control signal from the main control means. An image display apparatus comprising: a switching unit; and a frame memory unit that stores N-bit gradation data and (N-1) -bit gradation data output from the switching unit and supplies the data to a display driving unit. 5. Based on a control signal from a main control means,
In the frame data of N-bit gradation, the sequence of the emission cycle number a of the least significant bit is used, and in the frame data of (N-1) -bit gradation, the sequence of the emission cycle number b of the least significant bit is used. 5. The image display device according to claim 4, further comprising a sequence generating means for outputting the image data to the image display device.