JPH11275522A - Digital vtr - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously record image information to plural channels without losing the information by reading coded data from each memory by one field at a time in each vertical interval of a synchronizing matching signal in order of different memories and recording coded data for the number of fields which corresponds to the number of channels on a video tape. SOLUTION: 1st/2nd gate arrays 13/23 read coded data for one field which are stored in 1st/2nd memories 14/24 in the first half/the last half of one vertical interval of a synchronizing matching signal. A formatter 4 converts data of 153 packets per one vertical interval of the synchronizing matching signal into a D-VHS format, 76 packets of the first half of the one vertical interval of the synchronizing matching signal is allocated for transfer of 1st channel coded data, the next packet is allocated for insertion of a marker that shows a channel break and 76 packets of the last half are allocated for transfer of 2nd channel coded data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital VTR for simultaneously recording image signals of a plurality of channels on a single video tape.

[0002]

2. Description of the Related Art Images captured by a surveillance camera are
A monitoring device for recording on a video tape by an analog VTR has already been developed. In a monitoring device of this type, when a plurality of monitoring cameras are installed, a plurality of analog VTRs are required to record an image from each monitoring camera.

In order to record images from a plurality of surveillance cameras by an analog VTR, it is conceivable that images from the respective surveillance cameras are time-divided and input to one analog VTR. However, in this case, there is a problem that the amount of recorded information for each camera is reduced.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital VTR capable of simultaneously recording image information for a plurality of channels without losing the information.

[0005]

A first digital VTR according to the present invention is a digital VTR for simultaneously recording image signals of a plurality of channels on a single video tape,
An image compression circuit provided for each channel and compressing an image signal of each channel for each field; a memory provided for each image compression circuit and storing encoded data obtained by each image compression circuit; Within each vertical period of the synchronizing signal having the same period as the vertical synchronizing signal of the image signal, the encoded data is read out from each memory one field at a time in the order of each memory, and the encoding is performed for the number of fields corresponding to the number of channels. It is characterized by comprising means for recording data on a video tape.

A second digital VTR according to the present invention is:
A digital VTR for simultaneously recording image signals of a plurality of channels on a single video tape, wherein each of the image compression circuits is provided for each channel and compresses the image signal of each channel for each field. A memory provided for storing encoded data obtained by each image compression circuit, and less than one field unit from each memory within each vertical period of a synchronization signal having a period equal to the vertical synchronization signal of the input image signal. It is characterized in that a means is provided for reading out the encoded data of the number of fields corresponding to the number of channels on a video tape by repeatedly reading out the unit amount in the order of the memories.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a digital VTR for recording and reproducing two-channel images picked up by two monitoring cameras.
Is shown.

The digital VTR includes signal processing units 1 and 2 for two channels, a switch 3, a formatter 4, and an amplifier unit 5.

The first signal processing unit 1 includes a first A / D converter 11, a first JPEG compression / expansion circuit 12, a first gate array (FPGA) 13, a first memory 14, and a first memory 14. A D / A converter 15 is provided.

The second signal processing unit 2 includes a second A / D converter 21, a second JPEG compression / decompression circuit 22, a second gate array (FPGA) 23, a second memory 24, and a second A D / A converter 25 is provided.

The operation at the time of recording will be described with reference to FIG.

FIG. 2A inputted to the first input terminal 31
The first channel image signal Vin1 shown in FIG.
The image data is converted into digital image data by the / D converter 11. The image data obtained by the A / D converter 11 is compressed by the first JPEG compression / decompression circuit 12 for each field unit and temporarily stored in the first memory 14 as shown in FIG. Is accumulated in

FIG. 2 (c) inputted to the second input terminal 32
The second channel image signal Vin2 shown in FIG.
The data is converted into digital image data by the D converter 21. The image data obtained by the A / D converter 21 is
The data is compressed for each field unit by the second JPEG compression / expansion circuit 22 and temporarily stored in the second memory 24 as shown in FIG.

The reading of the coded data for one field stored in the first memory 14 is performed by the first gate array 1.
3 and stored in the second memory 24.
Reading of the encoded data for the field is controlled by the second gate array 23. First gate array 1
3 performs read control of the first memory 14 based on the synchronization signal sent from the formatter 4, and the second gate array 23 controls the second gate array 23 based on the synchronization signal sent from the formatter 4. The read control of the second memory 24 is performed.

As shown in FIG. 2E, the synchronizing signal has the same cycle as the vertical synchronizing signals of the input image signals Vin1 and Vin2. However, the phase of the synchronization signal lags behind the phase of any of the vertical synchronization signals of the input image signals Vin1 and Vin2.

As shown in FIG. 2F, the first gate array 13 performs the first half of one vertical period of the synchronization signal.
The coded data for one field stored in the memory 14 is read out. Also, the second gate array 23
As shown in FIG. 2F, the coded data for one field stored in the second memory 24 is read in the latter half of one vertical period of the synchronization signal.

Assuming that the formatter 4 is a D-VHS formatter that inputs 153 packets per vertical period of the synchronization signal and 188 bytes of data per packet and converts the data into a D-VHS format. 76 packets in the first half of one vertical period
Allocated for the transfer of the encoded data of the channel, the next one packet is assigned for inserting a marker indicating a channel delimiter, and the latter 76 packets are assigned for the transfer of the encoded data of the second channel.

The encoded data of the first channel read from the first memory 14 is converted into a format that can be input to the formatter 4 by the first gate array 13, and then converted to the formatter 4 via the switch 3. Sent. Similarly, the coded data of the second channel read from the second memory 24 is converted into a format that can be input to the formatter 4 by the second gate array 23, and then converted to the formatter 4 via the switch 3. Sent. Switch 3
Is controlled by the formatter 4.

In the formatter 4, the encoded data of the first channel, the marker and the encoded data of the second channel are converted into a D-VHS format. The data obtained from the formatter 4 is recorded on a video tape via a recording amplifier in the amplifier section 5 and a video head.

At the time of reproduction, the data read by the video head is sent to the switch 3 via the reproduction amplifier in the amplifier section 5 and the formatter 4. Then, data corresponding to the first channel in the first half of the vertical period of the synchronization signal is temporarily stored in the first memory 14 via the switch 3 and the first gate array 13. Also,
Data corresponding to the second channel in the latter half of the vertical period of the synchronization signal is temporarily stored in the second memory 24 via the switch 3 and the second gate array 23.

The encoded data temporarily stored in the first memory 14 is expanded by a first JPEG compression / expansion circuit 12 and then converted by a first D / A converter 15 into an analog image signal. You. And the first output terminal 4
1 to 1 are output as the image signal Vout of the first channel.

The encoded data temporarily stored in the second memory 24 is decompressed by a second JPEG compression / decompression circuit 22 and then converted by a second D / A converter 25 into an analog image signal. You. And the second output terminal 4
2 is output as the image signal Vout of the second channel.

In the above embodiment, at the time of recording, during the first half of one vertical period of the synchronization signal, the encoded data for one field stored in the first memory 14 is read out, and the 1 bit of the synchronization signal is read out. One field of encoded data stored in the second memory 24 is read in the latter half of the vertical period. However, within one vertical period of the synchronization signal, the 1
The coded data for one field and the coded data for one field stored in the second memory 24 may be alternately read in a predetermined unit, for example, for each packet.

In the above embodiment, the case where image signals for two channels are simultaneously recorded has been described. However, the present invention is also applicable to the case where image signals for three or more channels are simultaneously recorded depending on the compression ratio of the compression / expansion circuit. It is possible to apply.

[0026]

According to the present invention, image information for a plurality of channels can be simultaneously recorded without losing the information.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a digital VTR.

FIG. 2 is a time chart for explaining an operation at the time of recording.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st signal processing part 2 2nd signal processing part 3 switch 4 formatter 5 amplifier part 11, 21 A / D converter 12, 22 JPEG compression / expansion circuit 13, 23 gate array (FPGA) 14, 24 memory 15, 25 D / A converter

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[Procedure amendment]

[Submission date] July 13, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005]

A first digital VTR according to the present invention is a digital VTR for simultaneously recording image signals of a plurality of channels on a single video tape,
An image compression circuit that is provided for each channel and compresses the image signal of each channel so that the amount of image data decreases for each field. The image compression circuit is provided for each image compression circuit and is provided by each image compression circuit. The memory for storing the obtained encoded data, and the encoded data are read out from each memory one field at a time in each memory within one vertical period of the synchronization signal having the same period as the vertical synchronization signal of the input image signal. Means for recording encoded data for the number of fields corresponding to the number of channels on a video tape.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

A second digital VTR according to the present invention is:
A digital VTR for simultaneously recording image signals of a plurality of channels on a single video tape, wherein image compression is provided for each channel and compresses the image signal of each channel so that the amount of image data is reduced for each field. A circuit, a memory provided for each image compression circuit and storing encoded data obtained by each image compression circuit, and a synchronization signal having a period equal to that of the vertical synchronization signal of the input image signal. Means are provided for reading out coded data from each memory by a unit amount smaller than one field unit in the order of each memory and repeatedly, and recording the coded data for the number of fields corresponding to the number of channels on the video tape. It is characterized by the following.

Claims (2)

[Claims] 1. A digital VTR for simultaneously recording image signals of a plurality of channels on a single video tape, comprising: an image compression circuit provided for each channel and compressing the image signal of each channel for each field; A memory provided for each image compression circuit and storing encoded data obtained by each image compression circuit; and a memory for synchronizing signals having a period equal to the vertical synchronization signal of the input image signal. Means for reading the encoded data one field at a time in the order of the memories and recording the encoded data for the number of fields corresponding to the number of channels on a video tape. 2. A digital VTR for simultaneously recording image signals of a plurality of channels on a single video tape, comprising: an image compression circuit provided for each channel and compressing the image signal of each channel for each field; A memory provided for each image compression circuit and storing encoded data obtained by each image compression circuit; and a memory for synchronizing signals having a period equal to the vertical synchronization signal of the input image signal. Means for repeatedly reading out the unit amount smaller than one field unit in the order of each memory and recording the coded data for the number of fields corresponding to the number of channels on the video tape.