JPH11274910A - Signal receiver and electronic device provided with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely receive a signal, even when ground potentials between devices differ from each other. SOLUTION: This signal receiver is provided with plural input amplifiers 2, 3, whose operating potentials differ from each other with respect to differential input signals and with a selector 4 that receives digital outputs from the input amplifiers 2, 3 and selects either of them. The receiver receives the signal by allowing the selector 4 to select either of the digital outputs with respect to the same input signals received by the input amplifiers 2, 3. Since the plural input amplifiers 2, 3 whose operating potentials differ receive the input signals, even if the signals having various potentials are inputted, either input amplifier responds to the signal, so that the receiver applies 0/1 discrimination accurately to the input signal by allowing the selector 4 to select the output of the amplifier which responded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal receiving apparatus for receiving an external signal and an electronic apparatus including the same.

[0002]

2. Description of the Related Art Conventionally, as such a signal receiving apparatus, there is an input buffer which is incorporated in an LSI-made receiver chip and receives data from a driver chip provided outside the receiver.

The input buffer is, for example, as shown in FIGS. 7 (a) and 7 (b), a differential amplifier 3 formed of a CMOS transistor.
The differential amplifiers 32 and 42 receive signals by sensing the potential of data differentially transmitted from the driver chip.

As shown in FIGS. 7A and 7B, a differential amplifier is
By sensing the potential difference between data and / data, the data is
When the potential is higher than the data, 1 is output as received data, and when the potential is lower, 0 is output. That is, the input buffer receives data by sensing the data potential with the differential amplifier.

[0005]

By the way, due to recent multimedia, data has been often transmitted between completely different devices such as a PC and a digital camera.

[0006] However, if the ground potentials of the two devices are different, the input buffer of the receiving device may not operate. In other words, if the receiving-side ground potential is higher than the output side, the receiving-side device may recognize only 0.5 V even though the output-side device intends to output 1V. In such a case, for example, in the example shown in FIG. 7A, when the potentials of the data and the / data become lower than Vt of the NMOS (TN1, TN2) of the differential amplifier 32, NMOS (TN
(1, TN2) turns OFF, and data and / data cannot be sensed. Also, if the ground potential on the receiving side is lower than the output side,
In the example shown in FIG. 7B, the data and / data potentials are equal to or higher than the value (VDD-Vt) obtained by subtracting the Vt of the PMOS (TP1, TP2) of the differential amplifier 42 from the power supply potential VDD. If you have both P
MOS (TP1, TP2) is turned off, and data and / data cannot be sensed.

That is, the differential amplifier of the type received by the NMOS shown in FIG. 7A (hereinafter referred to as “NMOS amplifier”) or the differential amplifier of the type received by the PMOS shown in FIG.
"S amplifier". In either case, as shown in FIG. 8, the potential of data and / or data on the receiving side is (V
(Vtp and Vtn are PMO if they are between DD-Vtp) and (Vtn)
Vt of each of S and NMOS. ), PMO with NMOS amplifier
Data can be received with the S amplifier. That is, assuming that the power supply potential is 3.3 V and the Vt of each MOS is 0.5 V, data can be received in the range of 2.8 V to 0.5 V. Therefore, there was no problem even if the ground potential was slightly different from the output side. However, when sending data to battery-powered electronic devices, the power supply potential may be 1.5 V,
In such a case, data cannot be received unless the data potential is between 1 V and 0.5 V. In addition, since a battery-driven device is small and has a weak ground or the like, the difference in ground potential with respect to an output-side device is often large. Therefore, as shown in FIG. 8, in the case of a device using an NMOS amplifier, the input amplifier does not operate if the ground potential is higher than the output side, and in the case of a device using a PMOS amplifier, the ground potential is higher than the output side. If it is too low, the input amplifier will not operate.

As described above, when data cannot be sensed by the differential amplifier, data cannot be received because of the input buffer, and data transmission between devices cannot be realized.

This is particularly noticeable when the receiving device is a battery-driven device and has a low power supply potential.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a signal receiving device capable of reliably receiving a signal even if there is a difference in ground potential between devices, and an electronic device provided with the signal receiving device.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a plurality of input amplifiers having different operating potentials for differentially transmitted input signals, and a digital output from these input amplifiers. And a selector for selecting one of the digital amplifiers and receiving each signal by selecting each digital output corresponding to the same signal received by each input amplifier by the selector.

In the signal receiving apparatus according to the present invention,
Since input signals are received by a plurality of input amplifiers with different operating potentials, even if signals of various potentials arrive, any of the input amplifiers will respond. Signal exactly 0
/ 1 can be determined.

Here, if each input amplifier is formed so as to output 0 when it receives an input signal that deviates from its operating potential, the selector can be formed by an OR circuit. Simple. Further, when each input amplifier is formed so that 1 is output when receiving an input signal that deviates from its operating potential, the selector becomes AND
It becomes a circuit.

When hysteresis is given to the input / output characteristics of the input amplifier, the output value when receiving an input signal outside the operating potential of each input amplifier is determined by setting the transistor size of the input amplifier. Since the output value is hard to change, it is possible to suppress fluttering of the output of the amplifier due to the slight fluctuation of the ground potential on the receiving side while receiving the input signal, making it possible to make the received data more reliable it can.

Further, by connecting a pull-up or pull-down resistor to an appropriate node of the input amplifier so as to obtain an output value when receiving an input signal that is out of the operating potential of the input amplifier, Since the set value of the output value is hard to change, the fluctuation of the output of the amplifier due to the slight fluctuation of the ground potential on the receiving side while receiving an input signal outside the operating potential can be suppressed, so that the received data can be more reliably It can be.

[0016]

Embodiments of the present invention will be described with reference to the accompanying drawings.

The input buffer 1 shown in FIG. 1 comprises a pair of current mirror type differential amplifiers 2 and 3, and an OR circuit 4 receiving digital outputs from the differential amplifiers 2 and 3.

Here, the differential amplifiers 2 and 3 correspond to a plurality of input amplifiers having different operating potentials with respect to input signals transmitted differentially, and the OR circuit 4 receives digital outputs from these input amplifiers and receives any one of them. It is equivalent to a selector for selecting whether or not.

Each of the differential amplifiers 2 and 3 comprises current mirror amplifiers 2a and 3a for receiving data and / or data, and a hysteresis inverter 5 having hysteresis in input / output characteristics.

One current mirror amplifier 2a is a PMOS
(TP1, TP2) receives the differential data / data, and the other current mirror amplifier 3a receives the NMOS (TN1, TN2)
2) Receive differential data and / or data. Therefore, one differential amplifier 2 is a PMOS amplifier, and the other differential amplifier 3 is an NMOS amplifier.

As shown in FIG. 2A, the hysteresis inverter 5 has transistors TPa and TNa for changing the logic threshold of the inverter connected to two nodes of the transistors constituting the first-stage inverter. By turning on / off these transistors TPa and TNa, as shown in FIG. 2 (b), when the input In changes from 0 to 1 more than the logical threshold value Vthl when the input In changes from 1 to 0. The logical threshold value Vtlh is set to be high. Therefore, the differential amplifiers 2 and 3 have hysteresis in the input / output characteristics.

For this reason, once the input In becomes 1,
The output Out is hard to change to 0, and the input In
Once becomes zero, the output Out is difficult to change to 1 easily. Even if the ground on the receiving side fluctuates slightly while receiving input data, the output Out does not flutter. Processing can be reliably performed.

By setting the transistor size of the current amplifiers 2 and 3 to be stronger than that of the PMOS, each of the current amplifiers 2 and 3 has a data and / or data that deviates from the operating potential of the current amplifiers 2 and 3; When both data become (VDD-Vtp) or more, or when both data and / data become less than Vtn in the PMOS amplifier, the output potential is set to be close to the power supply voltage. Therefore, when each of the differential amplifiers 2 and 3 receives an input signal that deviates from its operating potential, 0 is output through the hysteresis inverter 5.

Therefore, the output value of the input buffer 1 with respect to the input signals of the differential amplifiers 2 and 3 is as shown in FIG. Therefore, each differential amplifier 2, 3 (PMOS
By taking the OR of the outputs of the amplifiers and NMOS amplifiers with the OR circuit 4, as shown in FIG. 3 (b), even if the input signal is out of the operation area of each of the amplifiers 2 and 3,
Complete reception of the input signal takes place. That is, by setting the output value outside the operating potential of the differential amplifiers 2 and 3 to 0, the selection of the output value from each of the differential amplifiers 2 and 3 can be correctly performed by the simple OR circuit 4. As shown in FIG. 3B, when the input signal deviates from the operating potentials of both the amplifiers 2 and 3, the signal cannot be received as a matter of course (shown by a circle in FIG. 3B). However, such a case is a very unlikely case and cannot occur in actual use.

In the input buffer 11 shown in FIG. 4, the differential amplifiers 12 and 13 have ordinary inverters 15 instead of the above-mentioned hysteresis inverters.

The differential amplifiers 12, 13 are provided with a pull-up resistor R at a node between the current amplifiers 12a, 13a and the inverter 15, so that when data and / or data are out of the operating potential, the differential amplifiers 12 and 13 can reliably operate. The output value can be set to 0. Therefore, the logic is easy to take in the OR circuit 14, and even if the ground potential on the receiving side fluctuates, it is hardly affected by the fluctuation. Therefore, the logic as shown in FIG. 3 is easy to take, and the data reception is ensured.

In the input buffer 21 shown in FIG. 5, the output value of the differential amplifiers 22 and 23 when the data and / or data is outside the operating potential of the differential amplifiers 22 and 23 is 1 due to the pull-down resistor R. . The logic of each output value is taken by the AND circuit 24.

Here, the differential amplifiers 22 and 23 correspond to a plurality of input amplifiers having different operating potentials with respect to input signals transmitted differentially, and an AND circuit 24 receives digital outputs from these input amplifiers and receives any one of them. It is equivalent to a selector for selecting whether or not. Therefore, the differential amplifiers 22, 23
6 (a), and correct data can be received by taking an AND, as shown in FIG. 6 (b). As in the case shown in FIG. 3B, when the input signal deviates from the operating potentials of both the amplifiers 22 and 23, the signal cannot be received as a matter of course (shown by the circle in FIG. 6B). ). However, such a case is a very unlikely case and cannot occur in actual use.

[0029]

As described above, in this signal receiving apparatus, since the output signals from a plurality of input amplifiers having different operating potentials with respect to the input signal are selected by the selector and correct data is received, the signal receiving apparatus is wide. Data can be received within the range, and reliable digital signal transmission can be realized even if there is a difference in ground potential between the transmitting side and the receiving side.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a signal receiving apparatus according to the present invention.

FIG. 2 is an explanatory diagram of a hysteresis inverter.

FIG. 3 is a diagram showing a logical table of a signal receiving apparatus using OR.

FIG. 4 is a circuit diagram of another embodiment of a signal receiving apparatus using an OR.

FIG. 5 is a circuit diagram of another embodiment of a signal receiving apparatus using AND.

FIG. 6 is a diagram showing a logic table of a signal receiving apparatus using AND;

FIG. 7 is a circuit diagram of a conventional signal receiving device.

FIG. 8 is an explanatory diagram of an operating potential of an input amplifier.

[Explanation of symbols]

1,11,21 Input buffer 2,3,12,13,22,23,31,41 Differential amplifier 4,14 OR circuit 24 AND circuit 5 Hysteresis inverter 15 Inverter

Claims (7)

[Claims] A plurality of input amplifiers having different operating potentials with respect to input signals sent differentially; and a selector for receiving a digital output from the input amplifier and selecting one of the input amplifiers. A signal receiving device for receiving a signal by selecting each digital output for the same signal by the selector. 2. Each of the input amplifiers is formed so as to output 0 when receiving an input signal outside its operating potential.
2. The signal receiving device according to claim 1, wherein said selector is formed by an OR circuit. 3. Each of the input amplifiers is formed so as to output 1 when receiving an input signal outside its operating potential.
The signal receiving device according to claim 1, wherein the selector is formed by an AND circuit. 4. The signal receiving apparatus according to claim 2, wherein the input / output characteristics of the input amplifier have hysteresis. 5. A pull-up or pull-down resistor is connected to an appropriate node of the input amplifier so as to have an output value when receiving an input signal outside the operating potential of the input amplifier. The signal input device according to claim 2. 6. The input amplifier is a pair of current mirror type.
6. The signal receiving device according to claim 1, wherein a CMOS amplifier is formed, one of which is formed to receive an input signal by a PMOS, and the other is formed to receive an input signal by an NMOS. 7. An electronic apparatus comprising the signal input device according to claim 1.