JPH11274497A - Polycrystal semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently make the most of merits of CMP(chemical mechanical polishing) while control precisely a polishing amount irrespective of a shape of a polycrystal film, and also enable the CMP excellent in matching to a post-step. SOLUTION: A first insulation film 2 is formed on a surface of a semiconductor substrate 1, and a polycrystal layer is formed thereon, and an element isolation is made by element isolation layers 20, 21 by LOCOS(selective oxidizing method). Thereafter, amorphous semiconductors are deposited and grown in a solid-phase to form a polycrystal layer. Thereafter, after a CMP processing is performed to flatten a surface of a polycrystal layer 3 by use of the element isolation layers 20, 21 as a stopper, impurities are implanted to form a high resistance semiconductor layer 3 comprising a first high resistance layer 3a and a second high resistance layer 3, and a gate electrode 9 is formed in the upper part via a semiconductor film 8, and the impurities are ion-implanted by use of this gate electrode 9 as a mask, thereby to form a source electrode 10 and a drain electrode 11 to attain a semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline semiconductor device and a method of manufacturing the same, and more particularly, to a method of manufacturing a thin-film polycrystalline semiconductor device having improved control characteristics in a polishing step and a precision controlled semiconductor device manufactured by the method. The present invention relates to a thin-film polycrystalline semiconductor device having a thin film thickness.

[0002]

2. Description of the Related Art When a thin-film polycrystalline semiconductor device is manufactured, for example, polycrystalline silicon or the like or an amorphous semiconductor such as amorphous silicon is deposited and annealed to form a thin film with the polycrystalline silicon. There is a technology to form.

FIG. 7 is a sectional view showing a conventional lateral N-type MOSFET using dielectric isolation. In FIG.
MOSFET is a silicon substrate 101 as a semiconductor substrate
And the insulating film 1 formed on the silicon substrate 101
02, and a p-type semiconductor layer 103 formed of a p-type semiconductor on the insulating film 102. The SOI (Silicon) is formed by the substrate 101, the insulating film 102, and the p-type semiconductor layer 103.
On Insulator) A substrate is formed. On both sides of the p-type semiconductor layer 103 on the insulating film 102, an n-type source layer 104 and an n-type drain layer 105 containing high concentration impurities
Are formed.

The n-type source layer 104 and the n-type drain layer 10
The gate electrode 109 is formed on the p-type semiconductor layer 103 sandwiched between the gate electrode 109 and the gate electrode 109 via the gate oxide film 108.
A source electrode 110 is provided on the n-type source layer 104, and a drain electrode 1 is provided on the n-type drain layer 105.
11 are provided. Further, an interlayer insulating film 112 is formed so as to cover the gate electrode 109, and interlayer insulating films 113 and 114 are formed below the source electrode 110 and the drain electrode 111, respectively. In addition, LOCO is used to laterally separate the semiconductor element from the dielectric.
LOCOS films 120 and 121 formed by S (selective oxidation method—LOCal Oxidation of Silicon—) are formed outside the n-type source layer 104 and the n-type drain layer 105, respectively.

This N-type MOSFET is manufactured as follows. First, the insulating film 102 on the silicon substrate 101
Is formed, for example, by thermally oxidizing the silicon substrate 101. Further, a p-type semiconductor layer 103 is obtained by depositing polycrystalline silicon doped with a p-type impurity. The p-type semiconductor layer 103 may be formed by depositing undoped polycrystalline silicon and then ion-implanting and diffusing p-type impurities.

Next, a LOCOS step for element isolation is performed. After the p-type semiconductor layer 103 is oxidized to form an oxide film and a nitride film is further deposited thereon, the oxide film and the nitride film are removed by etching except for a portion corresponding to an element formation region. By performing oxidation in this state, LOCOS separation can be performed. LO
After the COS separation is performed, the oxide film and the nitride film in the element formation region are peeled off before the element formation step is started.

In the element forming step, the gate oxide film 1
08, a gate electrode 109 is formed of polycrystalline silicon or the like, and then the n-type source layer 104 and the n-type drain layer 1 are formed.
Ion implantation and diffusion are performed to form 05. Finally, after depositing the interlayer insulating films 112, 113 and 114, a contact hole is opened in a portion in contact with the n-type source layer 104 and the n-type drain layer 105. For example, aluminum is deposited to form the source electrode 110 and the drain electrode 111. Form.

The N-type MOSFET having the above structure is formed by the above-described forming method.
In the case of ET, it is only necessary that the semiconductor constituting each layer be configured to have the opposite conductivity type.

In the case of a polycrystalline MOSFET, the p-type semiconductor layer 103 is made of polycrystalline silicon or polycrystalline silicon formed by depositing and annealing amorphous silicon. The characteristics of the polycrystalline silicon layer are affected by the poor surface flatness and the poor gate oxide film quality as compared with the single crystal silicon layer. Therefore, chemical mechanical polishing (hereinafter referred to as CMP-Chemical Mechanical P
It is well known that by performing olishing-) processing, the flatness of the film surface is increased to improve device characteristics.

When the above-mentioned CMP process is performed on a film having uneven steps, polishing is performed after forming an oxide film having a flat surface over the entire surface of the film including the steps. Was like that. When the polishing is performed after forming the oxide film in this manner, it can be considered that the polishing is completed when the convex oxide film is polished, so that the oxide film can be used as a polishing stopper. . Here, if the polycrystalline film is a flat film, the oxide film cannot be used as a stopper. Therefore, since polishing is performed without a physical stopper, it is necessary to perform CMP processing by designating time using a timer or the like.

However, when the polishing is performed by designating a time, it is difficult to perform accurate and precise control unless a detailed time is designated, so that there is a problem that the controllability of the polishing is deteriorated. Since it is difficult to adjust the thickness of the film to be left without being processed, there is a problem that the variation in the wafer surface or between wafers increases.

In a MOSFET formed of a normal thin-film polycrystalline semiconductor, LOCOS is performed after depositing polycrystalline silicon and performing a CMP process. However, in this LOCOS step, the LOCOS step covers an element formation region. Before the nitride film is deposited, a thermal oxidation step is performed, and there is a problem that the surface flatness of the polycrystalline film is impaired due to surface oxidation in the thermal oxidation step.

[0013]

As described above, in order to improve the element characteristics of a polycrystalline semiconductor device, a CMP process for the surface of a polycrystalline film is effective. Is difficult to control, and the process consistency with the subsequent process is not very good.

According to the present invention, in order to fully utilize the advantages of CMP processing, the amount of processing and polishing can be accurately controlled irrespective of the film shape of the polycrystalline film, and a polycrystalline semiconductor device which is excellent in consistency with the subsequent steps. It is intended to provide a manufacturing method thereof.

[0015]

According to another aspect of the present invention, there is provided a polycrystalline semiconductor device, comprising: a semiconductor substrate; a first insulating film formed on the substrate; and a first insulating film. A first high-resistance layer of a first conductivity type formed thereon using a polycrystalline semiconductor, and a second high-resistance layer of a first conductivity type formed on the first high-resistance layer using a polycrystalline semiconductor. A high resistance semiconductor layer including a resistance layer, a second conductivity type source layer formed on the high resistance semiconductor layer, and a high resistance semiconductor layer formed at a position different from a position where the source layer is formed. A drain layer, a second insulating film formed on the high-resistance semiconductor layer, and a second insulating film formed on the high-resistance semiconductor layer sandwiched between the source layer and the drain layer via the second insulating film And a gate electrode.

According to a second aspect of the present invention, in the polycrystalline semiconductor device according to the first aspect, an element isolation layer formed by LOCOS is formed outside the source layer and the drain layer. Features.

Further, in the polycrystalline semiconductor device according to the present invention, in the device according to the first aspect, an element isolation layer formed by trench isolation may be formed outside the source layer and the drain layer. good.

According to a third aspect of the present invention, there is provided a method for manufacturing a polycrystalline semiconductor device, comprising: forming a first insulating film on a semiconductor substrate; and forming a first polycrystalline layer on the first insulating film. Forming an element isolation layer on the first polycrystalline layer; forming a second polycrystalline layer on the first polycrystalline layer and the element isolation layer; Using the layer as a stopper, the second polycrystalline layer
Forming a high-resistance semiconductor layer using the first polycrystalline layer and the second polycrystalline layer as a first conductivity type; forming a high-resistance semiconductor layer on the high-resistance semiconductor layer; Forming a second insulating film, forming a gate electrode on the second insulating film, and forming a drain layer and a second conductivity type source layer on the high-resistance semiconductor layer using the gate electrode as a mask. And forming a source electrode and a drain electrode on the source layer and the drain layer, respectively.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a polycrystalline semiconductor device according to the third aspect, wherein the element isolation layer is formed by LOCOS.

Further, in the method of manufacturing a polycrystalline semiconductor device according to the present invention, the device isolation layer may be formed by trench isolation.

The first polycrystalline layer is formed by depositing a polycrystalline semiconductor, and the second polycrystalline layer is formed by depositing an amorphous semiconductor. Is used, the manufacturing cost can be kept relatively low and the crystallinity of the surface is improved.
In an element such as an FET which forms a channel on the surface, the channel mobility is improved and the element characteristics are improved.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a thin-film polycrystalline semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. As shown in FIG. 1, a polycrystalline semiconductor device according to a first embodiment of the present invention
It has a configuration as an FET. The N-type MOSFET according to the first embodiment performs element isolation by LOCOS. In addition, silicon (Si)
In contrast, boron (B) is used as the p-type impurity, and phosphorus (P) or arsenic (As) is used as the n-type impurity.

As shown in FIG. 1, a MOSFET includes a single crystal silicon substrate 1 as a semiconductor substrate, a first insulating film 2 formed on the substrate 1, and a first insulating film 2 on the first insulating film 2. A first high-resistance layer 3a formed of polycrystalline silicon as a one-conductivity-type (p-type in the first embodiment) polycrystalline semiconductor, and a first-conductivity-type (p-type) polycrystalline semiconductor thereon. And a high-resistance semiconductor layer 3 including a second high-resistance layer 3b laminated with polycrystalline silicon. The silicon substrate 1, the first insulating film 2, and the high-resistance semiconductor layer 3 form an SOI substrate.

A source layer 4 of a second conductivity type (n-type in the first embodiment) is formed on a part of the high-resistance semiconductor layer 3 on the first insulating film 2. At a position away from the source layer 4 of the high-resistance semiconductor layer 3,
A second conductivity type (n-type) drain layer 5 is formed.
A second insulating film 8 is formed on the high-resistance semiconductor layer 3, and a second insulating film 8 is interposed between the source layer 4 and the drain layer 5 and functions as a channel region on the high-resistance semiconductor layer 3. A gate electrode 9 is formed with two insulating films 8 interposed therebetween.

In addition to the above configuration, the high resistance semiconductor layer 3
Are further formed on both sides of the source layer 4 and the drain layer 5 formed on both sides of the substrate for separating elements laterally in the drawing.
Element isolation layers 20 and 21 formed by OCOS are formed. Above these element isolation layers 20 and 21,
Along with an interlayer insulating film 12 formed on the second insulating film 8 so as to cover the gate electrode 9, interlayer insulating films 13 and 1 are formed.
4 are formed. For example, aluminum or the like is formed on the upper side of the interlayer insulating films 13 and 14 so as to cover the interlayer insulating films 13 and 14 and to fill a contact hole opened in a portion in contact with the n-type source layer 4 and the n-type drain layer 5. A source electrode 10 and a drain electrode 11 are formed.

Next, a method for manufacturing a thin-film polycrystalline semiconductor device having the above configuration will be described with reference to the manufacturing process diagram of FIG. 2 and the flowchart of FIG. FIG.
As shown in FIG. 1A, a substrate 1 made of a semiconductor is thermally oxidized to form a first insulating film (oxide film) 2 on the surface of the substrate 1 (step ST1 in FIG. 3). In the next second step ST2, polycrystalline silicon is deposited on the first insulating film 2 to form a polycrystalline layer 3a '.

In the next step ST3, the polycrystalline layer 3
After an oxide film SiO ₂ is formed on a ′ by thermal oxidation, a semiconductor nitride film SiN is deposited on the oxide film SiO ₂ and a part thereof is etched, as shown in FIG. , Leaving only a part of the oxide film. And
After the polycrystalline layer 3a 'is oxidized to selectively oxidize the polycrystalline layer 3a' other than the portion where the oxide film remains, element isolation layers 20 and 21 are formed. As shown in c), the oxide film SiO ₂ and the semiconductor nitride film SiN are removed (step ST4). This step is L
This is an OCOS step.

Next, in step ST5, the oxide film Si
Amorphous silicon 3b 'is deposited over the entire polycrystalline layer 3a' from which O ₂ and the semiconductor nitride film SiN have been removed, and the element isolation layers 20 and 21, and annealing is performed in a nitrogen atmosphere at, for example, 600 ° C. for 8 hours. After a while, this amorphous silicon is polycrystallized by solid-phase growth to form a polycrystalline layer 3b ', and as shown in FIG. 2D, a polycrystalline layer 3' made of a polycrystalline semiconductor is formed. . In general, it is known that when amorphous silicon is grown in a solid layer, a polycrystal having excellent crystallinity can be obtained. In the case of the first embodiment, when the amorphous silicon is grown in a solid layer, the interface between the amorphous silicon and the polycrystalline layer 3a 'starts to crystallize from the polycrystalline layer 3a', but the surface of the film is Can obtain a polycrystalline film having good crystallinity by solid layer growth.

Next, in step ST6, CMP is applied to the entire upper surface of the polycrystalline layer 3 'to form the element isolation layer 2'.
The upper surfaces of the element isolation layers 20 and 21 and the polycrystalline layer 3b 'are polished by using 0 and 21 as stoppers, and FIG.
A flat surface is formed as shown in FIG.

Next, in step ST7, a high-resistance semiconductor layer 3 is formed by implanting a first conductivity type (here, p-type) impurity into the polycrystalline layer 3 '. Next, in Step ST8, after the second insulating film 8 is formed by thermal oxidation, polycrystalline silicon is deposited and then patterned to form the gate electrode 9, and the gate electrode 9 is formed under the gate electrode 9 except for the lower side and the periphery. After the second insulating film 8 is removed, impurities of the second conductivity type (here, n-type) are ion-implanted using the gate electrode 9 as a mask, and as shown in FIG. 3 shows a source layer 4 and a drain layer 5 of the second conductivity type.
Are formed respectively. Since the polycrystal is made amorphous by this ion implantation, in the next step ST9, the source layer 4 and the drain layer 5 are activated and crystallized by, for example, RTA (Rapid Thermal Anneal). The RTA is performed at 900 ° C. for 30 seconds or at 1000 ° C. for about 20 seconds. Finally, step ST10
In this method, after forming interlayer insulating films 12, 13 and 14, a contact hole is formed and aluminum (A) is formed.
1), the source electrode 10 and the drain electrode 11 are formed, and as shown in FIG. 2G, a polycrystalline semiconductor device is completed. This interlayer insulating film is formed by chemical vapor deposition (C
VD-Chemical Vapor Deposition-).

According to the first embodiment, the LOCOS is lower than that of the prior art in which LOCOS is performed after the CMP processing.
After performing S, CMP processing is performed, so LOCOS
Even if surface flatness is impaired by performing
Since the surface is flattened by the P processing, there is an effect that the flatness of the surface of the surface is not impaired. Also, LOC
Since the element isolation layer formed by the OS is used as a stopper, the controllability of the CMP process is improved.

Furthermore, compared to the case where only polycrystalline silicon is deposited, the upper side of the high-resistance polycrystalline layer is formed by solid-phase growth of amorphous silicon and polycrystallized, so that the crystallinity of the surface is reduced. Good, the channel mobility is improved, and as a result, the ON characteristics are also improved.

Next, a thin-film polycrystalline semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. In the thin-film polycrystalline semiconductor device according to the second embodiment shown in FIG. 4, the device according to the first embodiment performs element isolation by LOCOS, but performs isolation by trench grooves. It is characterized by. FIG. 4 is a cross-sectional view of a thin-film polycrystalline semiconductor device in which elements are separated by trench grooves. In FIG. 4, a semiconductor device is formed by thermally oxidizing a single-crystal silicon substrate 1 on a first surface thereof. And a polycrystalline layer 30 formed by depositing polycrystalline silicon on the first insulating film 2 or by depositing amorphous silicon on the first insulating film 2 to form a polycrystalline layer. Isolation layer 31 of oxide film 32 and polycrystalline layer 33 buried in trenches formed by performing reactive ion etching (hereinafter abbreviated as RIE).
And

A high-resistance semiconductor layer 3 functioning as a channel region is formed by injecting a p-type impurity into an element region surrounded by the element isolation layer 31, and an n-type semiconductor layer is formed around the high-resistance layer 3. The source layer 4 and the drain layer 5 are formed by implanting impurities. On the high resistance semiconductor layer 3 sandwiched between the source layer 4 and the drain layer 5, a second insulating film 8 is formed.
The gate electrode 9 is formed with the insulating film 8 interposed therebetween.

In addition to the above structure, on the element isolation layer 31, interlayer insulating films 13 and 14 are formed together with an interlayer insulating film 12 formed on the second insulating film 8 so as to cover the gate electrode 9. For example, aluminum (Al) is formed on the upper side of these interlayer insulating films 13 and 14 so as to cover them and to bury a contact hole opened in a portion in contact with the n-type source layer 4 and the n-type drain layer 5. A source electrode 10 and a drain electrode 11 made of Al) or the like are provided.

A method of manufacturing the thin-film polycrystalline semiconductor device according to the second embodiment having the above configuration will be described with reference to the manufacturing process diagram of FIG. 5 and the flowchart of FIG. First, as shown in FIG. 5A, a silicon substrate 1 is thermally oxidized to form a first insulating film 2 on the surface thereof (step ST1 in FIG. 6), and polycrystalline silicon is further deposited thereon. To form a polycrystalline layer 30 (step ST2). After a trench 31 'as shown in FIG. 5B is formed in the polycrystalline layer 30, an oxide film is further formed on the side wall including the bottom of the trench 31' as shown in FIG. 32,
A polycrystalline layer 33 is formed by embedding polycrystalline silicon therein, and an element isolation layer 31 is formed.
ST14).

Next, in step ST5, after amorphous silicon is deposited and polycrystallized to form a polycrystalline layer 35, a CMP process is performed as shown in FIG. A flat surface can be formed by stopper control using the layer 31 as a stopper (step ST
6). At this time, the upper surface of the polycrystalline layer 30 first deposited by slightly over-etching
It can be. Subsequent steps are the same as in the manufacturing method of the first embodiment.

The above-described manufacturing process will be described in accordance with the flowchart of FIG. 6. A step of forming a first insulating film 2 on a substrate 1 made of a semiconductor such as silicon by thermally oxidizing the substrate 1 ST1, a step ST2 of depositing a polycrystalline semiconductor on the first insulating film 2 to form a polycrystalline layer 30, and forming a trench 31 ′ at a predetermined position of the polycrystalline layer 30 to form a trench 31 ′. 'Oxide film 3 inside
2. Step ST14 of forming the element isolation layer 31 by embedding with the polycrystalline layer 33, and depositing and polycrystallizing amorphous silicon over the entire upper surfaces of the polycrystalline layer 30 and the element isolation layer 31 to form a polycrystalline layer. Step ST5 of forming the layer 35, and forming the upper surfaces of the element isolation layer 31 and the polycrystalline layer 30 on the flat surface 36 by performing CMP processing on the entire upper surface of the polycrystalline layer 35 using the element isolation layer 31 as a stopper. Step ST6, Step ST7 of forming a high-resistance semiconductor layer 3 by injecting impurities of a first conductivity type (here, p-type) into the polycrystalline layer 3A, and forming a second insulating film 8 by thermal oxidation After that, polycrystalline silicon is deposited and then patterned to form a gate electrode 9, and the second insulating film 8 other than the lower side and the periphery of the gate electrode 9 is peeled off. 5 by ion-implanting impurities of the second conductivity type (here, n-type).
(F), a step ST8 of forming a source layer 4 and a drain layer 5 of the second conductivity type in the high-resistance semiconductor layer 3 respectively. Since the polycrystal is made amorphous by the ion implantation, in the next step ST9, the source layer 4 and the drain layer 5 are activated by, for example, RTA (Rapid Thermal Anneal) to be polycrystallized. The RTA is performed at 900 ° C. for 30 seconds or at 1000 ° C. for about 20 seconds. Finally,
In step ST10, the interlayer insulating films 12, 13 and 1
After forming 4, a contact hole is formed, and a source electrode 10 and a drain electrode 11 made of aluminum (Al) or the like are formed. As shown in FIG. 5G, a polycrystalline semiconductor device is completed. This interlayer insulating film is formed by a chemical vapor deposition method (CVD-Chemical Vapor Deposition-).

In the second embodiment described above, the element isolation layer 31 formed by the trench isolation is the same as the L in the first embodiment.
Since the same functions as those of the ideal elements 20 and 21 by the OCOS are performed, the flatness of the surface is not impaired as in the first embodiment, and the controllability of the CMP is improved.

It should be noted that both of the two embodiments described above
Although an example in which the present invention is applied to a p-type MOSFET has been described, the present invention is not limited to this, and the present invention may be applied to a p-type MOSFET and a method of manufacturing the same. In that case, the conductivity type of the semiconductor described in the first and second embodiments may be replaced. Also, the present invention relates to a lightly doped drain (LDD).
-) MOSFETs with regions formed and insulated gate bipolar transistors (IGBT-Insulated Gate Bipola)
It is also possible to apply to r Transistor-) and other bipolar devices.

Further, in the first embodiment, the first
In this example, polycrystalline silicon is deposited as a high-resistance layer, and amorphous silicon is solid-grown as a second high-resistance layer to be polycrystallized to form a high-resistance semiconductor layer having a laminated structure. The present invention is not limited to this. The first high-resistance layer is made of polycrystalline amorphous silicon by polycrystalline growth, and the second high-resistance layer is made of polycrystalline amorphous silicon by polycrystalline growth. And a high-resistance semiconductor layer having a laminated structure may be formed. Alternatively, a high-resistance semiconductor layer in which polycrystalline silicon is stacked may be used as the second high-resistance layer, and a first high-resistance layer in which polycrystalline silicon is deposited may be used.

Further, after forming the first polycrystalline layer 3a 'and the second polycrystalline layer 3b' in which an amorphous silicon layer is grown in a solid layer, impurities are implanted and the p-type high resistance semiconductor layer 3 is formed. However, the present invention is not limited to this, and the high-resistance semiconductor layer 3 may be formed by depositing polycrystalline silicon doped with an impurity. After depositing doped amorphous silicon, the high-resistance semiconductor layer 3 may be formed by solid-phase growth.

[0043]

As described above in detail, according to the polycrystalline semiconductor device and the method of manufacturing the same according to the present invention, the element isolation layer in the thin polycrystalline semiconductor device is used as a stopper during the CMP process. Therefore, it is possible to improve the control characteristics of the CMP process in the case where the surface of the polycrystalline layer in which the channel region is formed is smoothed, and also to maintain good consistency between the post-process and the CMP process. To play.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a polycrystalline semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2G are cross-sectional views illustrating steps of a method for manufacturing a polycrystalline semiconductor device according to the first embodiment. FIGS.

FIG. 3 is a flowchart showing operation steps of a method for manufacturing the polycrystalline semiconductor device according to the first embodiment.

FIG. 4 is a sectional view illustrating a structure of a polycrystalline semiconductor device according to a second embodiment of the present invention.

FIGS. 5A to 5G are cross-sectional views illustrating steps of a method for manufacturing a polycrystalline semiconductor device according to a second embodiment, respectively. FIGS.

FIG. 6 is a flowchart showing operation steps of a method for manufacturing a polycrystalline semiconductor device according to a second embodiment.

FIG. 7 is a sectional view showing a structure of a conventional polycrystalline semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 1st insulating film 3 High resistance semiconductor layer 3a 1st high resistance layer (polycrystalline layer) 3b 2nd high resistance layer (polycrystalline layer) 3a 'polycrystalline layer 3b' polycrystalline layer 4 Source layer Reference Signs List 5 drain layer 8 second insulating film 9 gate electrode 10 source electrode 11 drain electrode 12 interlayer insulating film 13 interlayer insulating film 14 interlayer insulating film 20 element isolation layer 21 element isolation layer 30 polycrystalline layer 31 ′ trench groove 31 element isolation layer 32 oxide film 33 polycrystalline layer

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[Procedure amendment]

[Submission date] March 25, 1998

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

FIG. 2

FIG. 4

FIG. 3

FIG. 7

FIG. 5

FIG. 6

Claims (4)

[Claims] 1. A semiconductor substrate, a first insulating film formed on the substrate, and a first high resistance of a first conductivity type formed on the first insulating film by using a polycrystalline semiconductor. Layer and a first conductivity type second layer formed on the first high resistance layer using a polycrystalline semiconductor.
A high-resistance semiconductor layer including a high-resistance semiconductor layer, a second conductivity type source layer formed on the high-resistance semiconductor layer, and a high-resistance semiconductor layer formed at a position different from a position at which the source layer is formed. Formed on the high-resistance semiconductor layer, a second insulating film formed on the high-resistance semiconductor layer, and formed on the high-resistance semiconductor layer interposed between the source layer and the drain layer with the second insulating film interposed therebetween. A polycrystalline semiconductor device comprising: a gate electrode; 2. The polycrystalline semiconductor device according to claim 1, wherein an element isolation layer formed by LOCOS is formed outside said source layer and said drain layer. Forming a first insulating film on the semiconductor substrate; forming a first polycrystalline layer on the first insulating film; isolating the first polycrystalline layer from the semiconductor substrate; Forming a layer; forming a second polycrystalline layer on the first polycrystalline layer and the element isolation layer; and performing a CMP process on the second polycrystalline layer using the element isolation layer as a stopper. Making the first polycrystalline layer and the second polycrystalline layer a first conductivity type to form a high-resistance semiconductor layer; and forming a second high-resistance semiconductor layer on the high-resistance semiconductor layer. Forming an insulating film; forming a gate electrode on the second insulating film; forming a drain layer and a second conductivity type source layer on the high-resistance semiconductor layer using the gate electrode as a mask. And the source layer and Method for manufacturing a polycrystalline semiconductor device, characterized in that it comprises the steps of forming each of the source electrode and the drain electrode to the rain layer. 4. The method according to claim 3, wherein said element isolation layer is formed by LOCOS.