JPH11273013A - Magnetic disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a magnetic disk device provided with an offset cancel circuit capable of reducing the offset of an automatic gain control(AGC) loop circuit without increasing current consumption and an occupied area. SOLUTION: The magnetic disk device is constituted of a signal processing circuit provided with a reading circuit for amplifying a signal read out by a magnetic head and an AGC loop circuit consisting of a variable gain amplifier 11, a low pass filter(LPF) 12, a post stage amplifier 13, and a gain controlling voltage generation circuit 14 and capable of extracting necessary data based on a signal outputted from the reading circuit and generating a servo signal for a head driving motor and a control circuit for controlling the rotary driving motor. The AGC loop circuit is also provided with an offset cancel circuit 16 consisting of a voltage input/current output type amplifier and capable of adjusting a current drawn out from a current route in the amplifier 11 based on the output voltage of the amplifier 11 or the LPF 12 differently from an offset cancel circuit 15 for the amplifier 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to an offset cancel circuit of a variable gain amplifier, and to a magnetic disk drive including an AGC (automatic gain control) loop circuit for amplifying a read signal from a magnetic head. Regarding effective technology to use.

[0002]

2. Description of the Related Art Conventionally, in a magnetic disk type storage device, writing of data to a magnetic disk as a recording medium and reading of data from the magnetic disk are performed through a magnetic head. A read / write IC (head driver) including a circuit called a read amplifier for reading (detecting and amplifying) data and a write amplifier for writing data is coupled to the magnetic head. The read / write IC has a signal processing circuit including a circuit for extracting necessary data based on a read signal from the read / write IC and a circuit for generating a servo signal of a head drive motor as necessary. Circuit (LS
I) is connected, and this signal processing LS
The read system in I includes a VGA (variable gain amplifier) and read signals Rinx, Rin from the read / write IC.
An AGC (automatic gain control) loop circuit for amplifying y so that the amplitude becomes constant is provided.

FIG. 7 shows a configuration example of a conventional AGC loop circuit. As shown in FIG. 7, the AGC loop circuit includes a variable gain amplifier V to which a read signal is input.
GA, a low-pass filter LPF for removing high-frequency noise components from the read signal, a post-amplifier AMP for further amplifying the read signal, and monitoring the output of the post-amplifier so that its output amplitude is always at a predetermined level. It comprises a gain control voltage forming circuit AGCDET which forms and feeds back a control voltage Vc for controlling the gain of the variable gain amplifier VGA.

[0004] The variable gain amplifier and the latter-stage amplifier are constituted by a differential amplifier circuit, but the differential amplifier circuit has an offset due to imbalance of elements forming a pair. If there is an offset, the center potential of the output signal waveform deviates from a desired potential when the AC input signal is amplified, and accurate data cannot be reproduced. In the magnetic disk storage device, the positioning of the magnetic head is controlled based on a data read signal. Therefore, if there is an offset in the differential amplifier circuit constituting the amplifier for amplifying the data read signal, there is a problem that accurate head positioning cannot be performed.

In a conventional AGC loop circuit, an offset cancel circuit is provided in a post-stage amplifier AMP as shown in FIG. 7 from the viewpoint that it is sufficient to remove an offset from a final output.

[0006]

However, in the conventional AGC loop circuit, the gain of the post-stage amplifier is designed to be 26 dB while the gain of the variable gain amplifier is designed to be -40 to 9 dB. Since the offset of the variable gain amplifier was not canceled, an offset of about 10 mV was generated on the input side (node Na in FIG. 7) on average on the input side (node Na in FIG. 7). The node Nb) has an offset of about 200 mV, which is close to 500 mV at the maximum. To cancel this offset, the dynamic range of the offset cancel circuit had to be expanded. As a result, in the conventional AGC loop circuit, the current consumption of the offset cancel circuit increases, and the occupied area and the generated output noise also increase.

An object of the present invention is to provide a magnetic disk drive having an offset canceling circuit capable of reducing an offset of an AGC loop circuit without increasing current consumption and occupied area.

Another object of the present invention is to reduce output noise in an AGC loop circuit of a magnetic disk drive.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a rotary drive motor for rotating a magnetic disk, a magnetic head for reading data stored on the magnetic disk, a head drive motor for positioning the magnetic head, and a signal read by the magnetic head A signal processing circuit including an AGC loop circuit including a variable gain amplifier, a low-pass filter, a post-stage amplifier, and a gain control voltage generating circuit, amplifying a read signal from the read circuit, and reproducing data. A magnetic disk drive comprising: a control circuit for controlling a rotary drive motor;
The loop circuit includes a voltage input / current output type amplifier separately from the offset canceling circuit of the latter-stage amplifier, and controls the current in the variable gain amplifier so as to cancel the offset based on the output voltage of the variable gain amplifier or the low-pass filter. An offset cancel circuit for adjusting the current drawn from the path is provided.

According to the above-mentioned means, since the offset cancel circuit is also provided on the output side of the variable gain amplifier or the low-pass filter in the AGC loop circuit having the large gain of the latter-stage amplifier, the offset on the input side of the latter-stage amplifier is reduced. As a result, it is not necessary to increase the dynamic range of the offset cancel circuit of the post-stage amplifier, the offset of the AGC loop circuit can be greatly reduced without increasing the current consumption and the occupied area, and the output noise can be reduced. Can be reduced.

Further, the offset canceling circuit includes a first differential amplifier corresponding to a circuit at a next stage, a second differential amplifier having a capacitance for a high-pass filter function, and a second differential amplifier. And a third differential amplifier that outputs a current corresponding to the differential output of the third differential amplifier. This allows
An amplifier having an offset canceling function and having desired gain and frequency characteristics can be easily designed.

Further, the second differential amplifier is provided with the first differential amplifier.
A pair of bipolar differential transistors with the output of the differential amplifier input to the base as a differential signal and the emitter connected via a resistor, and the constant currents connected to the emitter terminals of these differential transistors, respectively Source
A plurality of constant current sources respectively connected to the collector terminals of the differential transistors, and a capacitor connected between the collector terminals of the differential transistors, each having a different resistance value between the emitter terminals of the differential transistors; Are provided in parallel, and any one of the plurality of resistors can be connected by a changeover switch. This allows
For example, the characteristics of the AGC loop circuit can be switched according to a servo control operation mode for positioning the head and a read operation mode for extracting data from a read signal.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a variable gain amplifier having an offset canceling circuit according to the present invention and an AGC loop circuit using the same. The AGC loop circuit according to this embodiment includes a variable gain amplifier 1 for amplifying a read signal Vin.
1, a low-pass filter 12 for removing high-frequency noise components from the read signal Vin, a post-amplifier 13 for further amplifying the read signal, and monitoring the output of the post-amplifier 13 so that the output amplitude becomes a predetermined level. The AGC control voltage forming circuit 14 forms a control voltage Vc to be fed back to the variable gain amplifier 11. The gain variable amplifier 1 is provided separately from the offset cancel circuit 15 for canceling the offset of the subsequent amplifier 13.
An offset cancel circuit 16 for canceling the offset of 1 is provided.

The offset canceling circuit 1 of this embodiment
6 is not particularly limited, but includes three differential amplifiers 61, 6
2 and 63, and constitutes a voltage input / current output type gm amplifier as a whole. The gain is adjusted by adjusting the current drawn from the current path in the variable gain amplifier 11 based on the output voltage of the variable gain amplifier 11. The offset of the variable amplifier 11 is configured to be canceled. In addition,
In the AGC loop circuit of FIG.
1 and the overall gain of the offset cancel circuit 16 is -40 to 9 dB, and the gain of the subsequent-stage amplifier is 26 dB.
B is designed.

FIG. 2 shows the differential amplifiers 61 to 6 constituting the variable gain amplifier 11 and the offset cancel circuit 16.
3 shows a specific example of a circuit.

As shown in FIG. 2, the variable gain amplifier 11 has, for example, a differential signal Vin input to a base, constant current sources I1 and I2 connected to emitter terminals, respectively, and emitters connected via a resistor R0. A pair of connected differential transistors Q1 and Q2 and this transistor Q
The transistors Q3 and Q4, whose emitter terminals and collector terminals are respectively connected to the collector terminals of the power supply voltages Vcc and Q2 and whose bases receive the gain control voltage Vc, are provided in parallel with the transistors Q3 and Q4, respectively. Transistor Q5 connected in series with resistors R1 and R1 between the collector terminals of transistors Q1 and Q2 and power supply voltage Vcc, respectively, and having their bases coupled to each other
And Q6. An output is taken out from the collectors of the transistors Q5 and Q6.

Although the differential amplifiers 61 to 63 constituting the offset cancel circuit 16 are not particularly limited, they are each constituted by a gm amplifier in this embodiment, and are connected to the output terminal of the variable gain amplifier 11 among them. In the first differential amplifier 61, the output voltage of the variable gain amplifier 11 is input to the base as a differential signal, the emitter terminals are connected to constant current sources I11 and I12, respectively, and the emitters are connected via a resistor R10. And a pair of differential transistors Q11 and Q12, and resistors R2 and R2 connected between the collector terminals of the transistors Q11 and Q12 and the power supply voltage Vcc, respectively.
The output is taken out from the collectors of Q1 and Q12.

The offset cancel circuit 16
, The output voltage of the previous-stage differential amplifier 61 is input as a differential signal to the base, the constant current sources I21 and I22 are respectively connected to the emitter terminals, and the resistance between the emitters is A pair of differential transistors Q21 and Q22 connected via R20 and Q2
1, Q22 are composed of constant current sources I23 and I24 connected between the collector terminals of the transistors Q21 and Q22, respectively, and are connected between the collector terminals of the transistors Q21 and Q22. The output is taken from the collector. Capacity C
, The differential amplifier 62 also functions as a high-pass filter that cuts a DC component. The current values of the constant current sources I21 to I24 are all the same.

Further, the offset cancel circuit 1
6 is an n-channel type differential amplifier in which the output voltage of the preceding differential amplifier 62 is input as a differential signal to the gate terminal and the source terminals are coupled to each other.
OSFET Q31, Q32 and this MOSFET Q
The drain terminals of the differential MOSFETs Q31 and Q32 are connected to a pair of output nodes N1 and N2 of the variable gain amplifier 11, and the common source terminal of the variable gain amplifier 11 A part of the current can be extracted from the current path, and the output voltage of the preceding stage amplifier 62, that is, the variable gain amplifier 11
The current to be extracted can be adjusted according to the output voltage.

The third differential amplifier is a MOSF
Instead of the ETs Q31 and Q32, a differential amplifier using bipolar transistors can be used. However, in the case of a differential amplifier using a MOSFET, M
Since the input range can be widened by reducing the element size of the OSFET, there is an advantage that a large dynamic range can be obtained with a smaller occupation area and less current consumption than a differential amplifier using bipolar transistors.

Next, the operation of the circuit shown in FIG. 2 will be described.

It is now assumed that the output Vout1 of the variable gain amplifier 11 is determined by the offset of the variable gain amplifier 11.
Is higher than Vout2 by ΔV. Then, the current i1 flowing through the transistor Q11 of the first differential amplifier 61 configuring the offset cancel circuit 16 is changed to Q12.
And the output Vout12 becomes higher than the output Vout11. As a result, in the second differential amplifier 62, the collector current of the transistor Q21 becomes larger than the collector current of the transistor Q22, and the constant current source I
Insufficient current of the current 23 flows from the capacitor C to the capacitor Q21. Conversely, the excess current of the constant current source I24 flows into the capacitor C as the collector current of the capacitor Q22 decreases. The constant current source I21 of the collector current of the transistor Q21
The current that cannot be drawn by the current flows into the constant current source I22 through the resistor R20, and the constant current source I22
Insufficient collector current is compensated by the current flowing from the resistor R20.

As described above, in the second differential amplifier 62, when the collector current of the transistor Q21 is larger than the collector current of Q22, Vo is higher than the output Vout21.
ut22 is higher. As a result, the third differential amplifier 63
In this case, the MOSFET Q31 is turned on more strongly than Q32, and the extraction current Iout2 from the output node N2 is larger than the extraction current Iout1 from the output node N1 of the variable gain amplifier 11, so that the output Vout2 is reduced to Vou.
Acts to approach t1. In addition, variable gain amplifier 1
When the output Vout1 is lower than Vout2 by ΔV due to the offset, the offset cancel circuit 16 operates in the opposite manner to the above, and the current Iout1 drawn from the output node N1 of the variable gain amplifier 11 is more than the output current Iout1 from the output node N2. Current Iout2 becomes smaller and the output Vout2
And acts to approach Vout1.

In the circuit of this embodiment, the gain of the variable gain amplifier 11 is gm1, the offset cancel circuit 16
The gain of each differential amplifier 61, 62, 63 constituting
2, gm3, gm4, resistors R1,
Assuming that the resistance values of R2 are r1 and r2, the variable gain amplifier 1
1 and the transfer function of the offset cancel circuit 16 are as follows: Vout / Vin = S · gm1 · gm2 · r1 · r2 / (S + gm2 · gm3 · gm4 · r1 ·
r2 / C) Variable gain amplifier 11 and offset cancel circuit 1
The gain G as a whole 6 is as follows: G = gm1 · gm2 · r1 · r2 The cutoff frequency fc is represented by fc = gm2 · gm3 · gm4 · r1 · r2 / 2πC. In the above equation, S is an operator in the Laplace transform.

In the circuit of the embodiment, for example, when the gain G of the variable gain amplifier 11 and the offset cancel circuit 16 is 9 dB and fc is 900 kHz, the offset at the input node Na of the post-stage amplifier 13 is several tens mV in the conventional circuit. Can be reduced to several mV. Therefore, the input dynamic range of the offset cancel circuit 15 provided in the post-stage amplifier 13 required about 380 mV when the offset cancel circuit 16 was not provided. Can be lowered. If the offset cancel circuit 16 of the variable gain amplifier 11 is composed of three gm amplifiers 61, 62, and 63 as shown in FIG. 2, the characteristics of the amplifier are represented by the above equations. The circuit design is extremely easy.

FIG. 3 shows another embodiment of the offset cancel circuit 16. This embodiment is different from the second differential amplifier 62 of the offset cancel circuit 16 in that the resistor R3 having a different resistance value in parallel with the resistor R30 connected between the emitter terminals of the transistors Q21 and Q22.
0 'is provided, and R30 and R30 are set by the changeover switch SW1.
30 'is configured to be connectable. Note that the resistors R30 and R30 'can be configured using the on-resistance of the MOSFET.

In this embodiment, the cutoff frequency fc of the offset cancel circuit 16 can be changed by changing the switch SW1 to change the gain gm2 of the differential amplifier 62. For example, when the switch SW1 is controlled so as to connect a resistor having a larger resistance value, the gain gm2 becomes smaller and the cutoff frequency f
c decreases. Such a circuit is used in a magnetic disk drive to switch the response of an AGC loop circuit between a servo control operation mode for positioning a head and a read mode for reproducing data from a read signal, or to use a type or system of a head to be used. When the specifications (for example, the rotational speed of the magnetic disk) are different, it is effective to amplify the read signal in an optimum state.

FIG. 4 shows another embodiment of the AGC loop circuit. In this embodiment, instead of monitoring the output of the variable gain amplifier 11 and applying feedback, the offset canceling circuit 1 monitors the output of the low-pass filter 12 and applies feedback to the variable gain amplifier 11.
6 ′, and the offset cancel circuit 1
The configuration of 6 'may be similar to that of the circuit shown in FIG. 2, and the operation is almost the same. The offset cancellation circuit 16 'of this embodiment can also cancel the offset generated in the low-pass filter 12, so that the offset on the input side of the post-stage amplifier 13 can be further reduced as compared with the offset cancellation circuit of the first embodiment.

Next, an example of a preferred system using a variable gain amplifier having an offset canceling circuit according to the present invention will be described. FIG. 5 shows a schematic configuration of a hard disk drive, and FIG. 6 shows a configuration of a signal processing circuit (LSI) which configures the hard disk drive. A variable gain amplifier having an offset canceling circuit according to the present invention includes: Used for the AGC loop circuit.

The configuration of the hard disk drive shown in FIG. 5 will be briefly described. 50 is a magnetic disk, 51 is a spindle motor for rotating the magnetic disk, and 52 is a magnetic disk 5
A magnetic head 53 for writing and reading data with respect to 0, a voice coil motor 53 for positioning the magnetic head 52, and a write amplifier 54 for supplying a write current to the magnetic head 52 and an amplifier for amplifying a signal read by the magnetic head 52 / Write I having a read amplifier
C and 55 are signal processing LSIs for forming write signals by adding ID information to write data and extracting data from read signals, 56 is a driver for driving the voice coil motor 53, and 57 is a spindle motor 51. A driving driver 58 is a hard disk controller that controls the entire hard disk device in place of the microprocessor or the like. In the embodiment of FIG.
Although the controller 58 is configured to control the spindle motor 51, a circuit for controlling the spindle motor 51 may be provided separately from the hard disk controller 58.

The signal processing LSI 55 is provided with a read system circuit and a write system circuit. Among them, the read system circuit includes a read signal Rin as shown in FIG.
an AGC loop circuit 501 of the above embodiment for amplifying x and Riny, an AD conversion circuit 503 for converting a signal of a data portion of the read signals Rinx and Riny into a digital signal,
It comprises a servo signal generating circuit 504 for generating a servo signal for head positioning.

VGA constituting AGC loop circuit 501 of the above embodiment for amplifying read signals Rinx and Riny
By applying the offset canceling circuit according to the present invention as the offset canceling circuit of the amplifier, V
The offset of the GA amplifier prevents the center potential of the output signal waveform of the read signal from deviating from a desired potential, thereby enabling accurate data reproduction. In the servo signal generation circuit 504, the AGC loop circuit 501
This prevents the magnetic head from appearing to be deviated from the center of the track on the surface of the magnetic disk due to the offset of the magnetic disk.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the above embodiment, the output of the VGA amplifier or the output of the low-pass filter is monitored and the current in the VGA amplifier is controlled so as to eliminate the offset. In the case where the low-pass filter is constituted by a filter, it is possible to monitor the output of the low-pass filter and control the current in the operational amplifier constituting the low-pass filter so as to eliminate the offset.

In the above embodiment, the three differential amplifiers 61, 62,
Although it has been described that each of the amplifiers 63 is constituted by a gm amplifier, the offset canceling circuit 16 only needs to constitute a voltage input / current output type amplifier as a whole circuit. A voltage output type differential amplifier circuit (for example, a circuit in which the resistor R10 of the differential amplifier 61 in FIG. 2B is omitted and one constant current source is used)
It is also possible to use However, the differential amplifier 61
Is also input to the next-stage circuit, so that the voltage-input / current-output amplifier or the voltage-input / voltage-output amplifier depends on the circuit type of the next-stage low-pass filter 12 or the subsequent-stage amplifier 13. Is selected.

In the above description, the invention made mainly by the present inventor is described in detail in the case where the A in the signal processing circuit (LSI) constituting the hard disk drive, which is the application field in which the invention is based.
Although the present invention has been described for the application to the offset cancellation of the GC loop circuit, the present invention is not limited thereto, and can be widely used for offset cancellation in a differential amplifier circuit. Further, the present invention can be used not only in a hard disk device but also in a read signal amplifier circuit of a floppy disk device, a compact disk device, or the like.

[0039]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the present invention realizes a magnetic disk drive provided with an offset cancel circuit capable of reducing the offset of the AGC loop circuit without increasing current consumption and occupied area, and reduces output noise in the AGC loop circuit. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an AGC loop circuit according to the present invention in which an offset canceling circuit is provided in a variable gain amplifier.

FIG. 2 is a circuit diagram showing a specific example of an offset cancel circuit.

FIG. 3 is a circuit diagram showing another specific example of the differential amplifier constituting the offset cancel circuit.

FIG. 4 is a block diagram showing another embodiment of the AGC loop circuit according to the present invention in which an offset canceling circuit is provided in a variable gain amplifier.

FIG. 5 is a block diagram showing a schematic configuration of a hard disk device as an example of a suitable system using a differential amplifier including an offset correction circuit according to the present invention.

FIG. 6 is a block diagram illustrating a configuration example of a read-related circuit of a signal processing circuit (LSI) included in the hard disk device.

FIG. 7 is a block diagram showing a configuration example of a conventional AGC loop circuit provided with an offset cancel circuit only in a post-stage amplifier.

[Explanation of symbols]

Reference Signs List 11 variable gain amplifier 12 low-pass filter 13 post-stage amplifier 14 AGC control voltage forming circuit 15 offset cancel circuit 16 offset cancel circuit 61, 62, 63 differential amplifier (voltage input / current output type gm amplifier) 50 magnetic disk 51 spindle motor 52 Magnetic head 53 Voice coil motor 54 Read / write IC 55 Signal processing LSI 56 Motor driver 57 Motor driver 58 Hard disk controller 501 AGC loop circuit 503 AD conversion circuit 504 Servo signal generation circuit

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Mamoru Kuraishi 3-1-1, Higashi Koigakubo, Kokubunji-shi, Tokyo Within Hitachi Ultra-LSE Engineering Co., Ltd. (72) Inventor Nobuhiro Fujii Ome-shi, Tokyo 6-16 Shinmachi 3 Device Development Center, Hitachi, Ltd.

Claims (3)

[Claims] 1. A rotary drive motor for rotating a magnetic disk, a magnetic head for reading data stored on the magnetic disk, a head drive motor for positioning the magnetic head, and a signal read by the magnetic head. A signal processing circuit including an AGC loop circuit including a variable gain amplifier, a low-pass filter, a post-stage amplifier, and a gain control voltage generating circuit, amplifying a read signal from the read circuit, and reproducing data. A magnetic disk drive comprising a control circuit for controlling a rotary drive motor, wherein the AGC loop circuit of the signal processing circuit comprises a voltage input / current output amplifier separately from the offset cancellation circuit of the subsequent amplifier. Offset based on output voltage of gain amplifier or low-pass filter Magnetic disk apparatus characterized by comprising an offset canceling circuit for adjusting the current withdrawn from the current path in the variable gain amplifier to the cell. 2. An offset canceling circuit comprising: a first differential amplifier corresponding to a next stage circuit; a second differential amplifier having a capacitance for a high-pass filter function; and a second differential amplifier. Output a current corresponding to the differential output of the third
2. The magnetic disk drive according to claim 1, wherein the magnetic disk drive comprises: 3. A pair of bipolar differential transistors, wherein the output of the first differential amplifier is input to a base as a differential signal and the emitters are connected via a resistor. A constant current source connected to the emitter terminal of each of the differential transistors; a constant current source connected to the collector terminal of the differential transistor; and a capacitor connected between the collector terminals of the differential transistor. A plurality of resistors having different resistance values are provided in parallel between the emitter terminals of the differential transistor, and any one of the plurality of resistors can be connected by a changeover switch. 3. The magnetic disk drive according to claim 2, wherein: