JPH11272480A - On-chip real time os - Google Patents

Abstract

PROBLEM TO BE SOLVED: To construct a real time information processing on an information processing system where loaded memories are considerably few by installing only task management, interruption management and semaphore management as functions for realizing a real time processing. SOLUTION: On-chip real time OS 21 has a task management means 21a, an interruption management means 21b and a semaphore management means 21c. The task management means 21a has a multi-task function being a function which can independently process a plurality of tasks by time multiplex and a preemptive schedule function being a function for preferentially processing the task whose priority is higher than the task whose priority is low in accordance with priority given to a plurality of tasks on CPU 11. The interruption management means 21b has a function receiving an interruption event during the execution of the task of any priority. The semaphore management means 21c has the exclusive control function of information transfer among a plurality of tasks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

More particularly, the present invention relates to an on-chip embedded system on an embedded system constituted by a CPU and dedicated hardware, or by integrating them on a single chip. The present invention relates to an on-chip real-time OS for building real-time information processing on (On Chip Embedded System).

[0002]

2. Description of the Related Art Conventionally, a plurality of tasks (subjects of processing) are
Processing is performed on one CPU (computer) by time multiplexing,
In addition, as a method of realizing a method of configuring an on-chip real-time OS that guarantees calling (starting) of all tasks within a predetermined time, the methods described in the following documents [1] to [4] may be adopted. General.

[0005] Alternatively, an embedded system, which is an information processing apparatus configured by one CPU and dedicated hardware and performing processing while transmitting and receiving information between the CPU and the dedicated hardware. Above, multiple tasks are processed in time multiplex, and
As a method of implementing an on-chip real-time OS that guarantees invocation of all tasks within a predetermined period of time, it is common to employ the methods shown in the following documents [1] to [4].

Further, the configuration of a normal computer system is described in Document [5], and the configuration of an embedded system is
It is described in reference [6].

[1] JLPerterson et al., “The Concept of Operating Systems”, Baifukan, 1987. [2] K. Sakamura ed., “ΜITRON 3.0 Specifi
cation ”, TRON Association. [3] M. Accetta et al.,“ Mach: A New Kernel Founda
tion for UNIX Development ”, Proc. Summer 198
6 USENIX, pp. 93-112, 1986. [4] JKOusterhout et al., “The Sprite Network Ope
rating Syste ”, IEEE Computer, Vol. 21, No. 2, p
p.23-36, 1988. [5] JL Hennessy and DAPatterson, “Computer A
rchitecture: A Quantitative Approach ”, Morgan Kau
fmann Publishers, Inc., 1990. [6] Daniel D. Gaisli, “Specification and Design
of Embedded Systems ”, Prentice Hall, 1994. In addition, embedded system (Embedded System)
It is composed of a CPU and dedicated hardware.
By performing processing while exchanging information between the above software and dedicated hardware, the system combines the "high speed" of dedicated hardware and the "flexibility" of software on a CPU. Furthermore, an on-chip embedded system (On-Chip Embedded System) that integrates them on one chip has been spotlighted as an LSI configuration method for developing large-scale and complex LSIs such as multimedia-related LSIs in a short time. I'm taking a bath.

[0006]

[Problems to be Solved by the Invention] By the way, reference [5]
Or an on-chip embedded system in which the embedded system shown in Reference [6] is integrated on a single chip.
When realizing an on-chip real-time OS using a real-time OS as shown in [4], there are the following problems.

As described above, the embedded system is:
The CPU is composed of a CPU and dedicated hardware.
Software (SW) and dedicated hardware (HW)
The process proceeds while performing information transfer (Interactions) with the server. In general, the interaction between HW and SW is
This operation is performed via registers of more than several tens of HW / SW interfaces.

The following requirements (1) to (4) are required for software on the CPU that controls the HW. (1) Control of a plurality of hardware (HW) resources The target LSI performs overall control by software running on a core CPU. Therefore, the design must be made in consideration of interaction with a plurality of functional components and deadlines. (2) Real-time property In the target LSI, it is necessary to guarantee that the processing is completed within a certain time. Also, the time from the occurrence of an interrupt event until the software accepts the interrupt must be sufficiently short. (3) Exclusive control of resources In order to reduce the cost of an LSI, hardware restrictions such as a memory amount and a gate scale are severe. Exclusive control must share limited resources on-chip. (4) Abnormal processing When the LSI cannot operate normally, processing must be performed so that abnormality can be detected or a normal state can be restored.

In response to these requirements, references [1] to [4]
The real-time OS shown in (1) has, as basic functions, (a) a task management function having a multitasking function and a preemptive scheduling function, (b) an interrupt management function having a function of receiving an interrupt event even during execution of a highest priority task, c) A semaphore management function that performs exclusive control of information exchange between a plurality of tasks, as well as (x1)
It has a memory management function that provides an independent memory space for multiple tasks, and (x2) an inter-task communication function that realizes information exchange between multiple tasks. In addition, using these basic functions, x3) Network function for connecting multiple systems via a network, (x4) I / O / file function for realizing system input / output and files,
(X5) It often provides user interface functions and other advanced application functions.

FIG. 11 is a diagram showing the relationship between the requirements for software and the functions of the real-time OS realizing the requirements.

As shown in FIG. 11, the functions of a real-time OS essential for real-time information processing that essentially satisfy software requirements include (a) task management,
Only (b) interrupt management and (c) semaphore management. However, a real-time OS as described in Documents [1] to [4]
Although it offers a wealth of functions, it requires a huge amount of memory as the dynamic memory at the time of execution, and is possible on-board with a dynamic memory exceeding tens of kilobytes. It is extremely difficult with an on-chip having only a dynamic memory of kB or less.

FIG. 12 is a diagram showing the relationship between the amount of dynamic memory targeted by the on-chip real-time OS of the present invention and the amount of dynamic memory of an existing real-time OS.

As shown in FIG. 12, even the smallest and lightest real-time kernel that can be incorporated on-board requires a memory of several tens kB to several hundreds kB, and a high-performance real-time OS on a pan controller or a workstation further requires several Ms.
B or more memory is required. On the other hand, the dynamic memory amount targeted by the present invention is several kB or less.

As described above, the problems in the conventional on-chip real-time OS on the on-chip embedded system also occur in various embedded systems to be developed. Considering the development of embedded systems that combine "high speed" and "flexibility" from "on-chip" with "high speed" and "flexibility" due to the development of integrated circuit technology typified by "system on silicon", It will become an increasingly serious problem. That is, a new on-chip real-time OS configuration method suitable for an on-chip embedded system is indispensable. However, conventionally, there is a problem that even the smallest and lightest real-time kernel exists only for an on-board which requires a memory of several tens kB to several hundred kB.

On the other hand, a method of reducing the amount of dynamic memory by reducing functions from an existing real-time OS having abundant functions is also conceivable. That is, the application function such as the network function using the basic primitive function, the input / output / file function, and the user interface function can reduce the amount of dynamic memory by selecting necessary functions. For example, as shown in FIG. 12, the difference in the amount of memory between the high-performance real-time OS and the on-board real-time OS largely depends on the function selection. However, from the system consisting of basic functions such as task management, interrupt management, semaphore management, memory management, and inter-task communication, memory management and inter-task communication are further separated and removed to further increase the dynamic memory amount. No attempt has been made to reduce it. In other words, memory management and inter-task communication are tightly coupled to task management and semaphore management in the real-time OS program configuration, and some concepts and attempts have been made to separate them to reduce the amount of dynamic memory. Not only have they been separated, but no means or attempts have been made to separate them.

When a real-time OS of an on-chip embedded system is used, sequence control that guarantees real-time performance while controlling a plurality of HW resources is the most important. Even if the data management of the space is left to the user, it is not a burden on reprogramming.

An object of the present invention is to provide an on-chip real-time OS for constructing real-time information processing on an information processing system having an extremely small amount of mounted memory.

In particular, the present invention provides a method in which a CPU
Build real-time information processing on an embedded system (Embedded System) composed of U and dedicated hardware, or on an on-chip embedded system (On Chip Embedded System) integrating them on one chip It is an object of the present invention to provide an on-chip real-time OS that performs the following.

[0019]

According to the present invention, only task management, interrupt management, and semaphore management are provided as minimum functions essential for realizing real-time processing.

[0020]

FIG. 1 is a diagram showing an on-chip real-time information processing apparatus IS1 including an on-chip real-time OS 21 according to a first embodiment of the present invention.

On-chip real-time information processing system IS
1 has one CPU (computer) 11, an on-chip real-time OS 21, and application software 31.

The on-chip real-time OS 21 has only a task management unit 21a, an interrupt management unit 21b, and a semaphore management unit 21c.

The task management means 21a includes a multi-task function for independently processing a plurality of tasks in a time-multiplexed manner on the CPU 11, and a low-priority function according to the priorities assigned to the plurality of tasks. This is a means having a preemptive scheduling function that is a function of processing tasks with higher priority than tasks.

The interrupt management means 21b has a function of receiving an interrupt event during execution of a task of any priority.

The semaphore management means 21c is a means having an exclusive control function for exchanging information between a plurality of tasks.

FIG. 2 is a diagram showing an on-chip real-time information processing apparatus IS2 including an on-chip real-time OS 22 according to a second embodiment of the present invention.

On-chip real-time information processing system IS
2 is a dedicated hardware 12 and a Core CPU 12
a, on-chip real-time OS 22, HW / SW
An IF (interface between hardware and software) 22I and application software 32 are provided.

The real-time OS 22 includes a task management unit 22a on an embedded system including the dedicated hardware 12 and the Core CPU 12a.
It has only an interrupt management unit 22b and a semaphore management unit 22c.

FIG. 3 shows task management in the above embodiment.
It is a figure which shows 18 system calls which implement | achieve interrupt management and semaphore management.

The task management means 21a and 22a include means for generating a task for realizing task management, means for activating a task, means for ending a task, means for deleting a task, Means for forcibly terminating, means for generating a periodic task that is a task that is started periodically, means for starting the periodic task, means for terminating the periodic task, and means for deleting the periodic task And means for forcibly terminating the other-period task, and means for acquiring the own task ID information.

The interrupt processing means 21b and 22b are provided with means for defining an interrupt handler for realizing interrupt management, means for canceling the definition of the interrupt handler, and means for terminating the interrupt. .

The semaphore management means 21c and 22c include means for generating a semaphore for realizing semaphore management, means for performing a semaphore operation, and means for deleting a semaphore.

The initial setting means 21d and 22d are kernel initial setting means. The kernel initial setting is performed by the respective means provided in the task managing means 21a and 22a and the respective means provided in the interrupt managing means 21b and 22b. Means and an initial setting means for activating the respective means included in the semaphore management means 21c and 22c.

FIG. 4 is a diagram showing an example in which the tasks in the task management means 21a and 22a undergo a state transition in the above embodiment.

The tasks are Non-exist, Exis
It has four states: t, Ready, and Run. FIG. 4 shows a state transition of a task by each system call.

FIG. 5 shows the task management means 21 of the above embodiment.
FIGS. 7A and 7B are diagrams illustrating examples of a multitask function and a scheduling function in FIGS.

The multitask function can realize desired processing by using a plurality of independent tasks. The function of determining the execution order of each task is the scheduling function. The scheduling function is a scheduling method that executes tasks in descending order of priority according to the priorities assigned at the time of task generation. If a high-priority task is waiting to be executed during execution, as shown in FIG. 5, the executing task is preempted (interrupted) and the high-priority task is executed.

FIG. 6 is a diagram specifically showing the interrupt processing means 21b and 22b in the above embodiment.

The interrupt processing means 21b and 22b implement an interrupt management function for performing strict real-time processing and performing abnormal processing. As shown in FIG. 6, even when a task having the highest priority is being processed, the registered interrupt handler is immediately activated when an interrupt occurs.

FIG. 7 is a diagram specifically showing the semaphore management means 21c and 22c in the above embodiment.

Exclusive control of resources is realized by semaphore management. Each task can secure and release resources by issuing a semaphore operation system call. As shown in FIG. 7, by using semaphore control, resources that can be commonly used are exclusively controlled (access of resources being used by one task to other tasks is prohibited), and resources are shared between tasks. Can be.

FIG. 8 is a diagram showing an on-chip real-time information processing apparatus IS3 including an on-chip real-time OS 23 according to a third embodiment of the present invention.

On-chip real-time information processing device IS
Reference numeral 3 denotes an MUX (MPEG2 multiplexing) LSI 13, an on-chip real-time OS 23, and an HW / SW IF (interface between hardware and software) 23I.
And application software 33. MUX
The LSI 13 includes MUX hardware and a Core CP.
U13a.

The real-time OS 23 is a MUX LSI
13, a task management unit 23a and an interruption management unit 23
b and only the semaphore management unit 23c.

The application software 33 is Video
o process 33a, Audio process 33b, User process 33c, PCR (time stamp for performing system time management) process 33d, and PSI (environment information) process 33
e is realized as an independent task.

That is, the on-chip real-time information processing apparatus IS3 is capable of transmitting / receiving video / video data defined by the MPEG2 system.
This is an example of a case where the present invention is applied to multiplexing of audio / user streams (called Multiplexer: MUX).

As described in Japanese Patent Application No. 8-75346, the MUX includes an MPEG2-compliant video stream as a plurality of input streams.
It handles audio streams and user streams, and handles streams such as transport streams or program streams as a plurality of output streams.
The MUX is a protocol processing device that multiplexes three streams of video, audio, and user (called “elementary streams”) and outputs one transport or program stream.

FIG. 9 shows the third embodiment according to the MPEG2
FIG. 9 is a diagram showing a specific example when applied to a system.

As an independent task configuration of the MUX 13,
It shows the relationship between detailed tasks such as Video, PCR, and PSI and their priorities.

FIG. 10 shows an example in which the third embodiment is implemented by using MPEG.
FIG. 14 is a diagram showing a specific example when applied to two systems.

In the actual processing of the transport stream, the execution process of each task for starting Video, PCR, PSI, etc., the execution ratio of each task, and the like are shown. The actual prescribed rate is Video: 5.0 Mbp.
s, PCR: 1 per 100 msec, PSI: 1 sec
And the overall TS rate is 6.144 Mb
ps, and the activation ratio of each task shown in FIG. 10 is in accordance with these prescribed rates. FIG. 9 shows the correspondence between task priorities and specific tasks.

The above-described embodiment provides only the minimum functions essential for realizing the real-time processing, such as evening management, interrupt management, and semaphore management. , MPEG
It is possible to realize an on-chip real-time OS suitable for constructing real-time information processing such as two-system applications. In the application to the MUX shown in FIG. 8, the on-chip real-time OS according to the embodiment of the present invention has a portion of about 2 kB and a MUX composed of a plurality of tasks.
Application part is about 2 kB or less, and a real-time OS can be implemented with an extremely small dynamic memory amount of 4 kB in total, and the MUX application can be operated.

The above-mentioned embodiment provides an information processing system with a very small amount of mounted memory by providing only evening management, interruption management, and semaphore management as the minimum functions indispensable for realizing real-time processing. Another object of the present invention is to provide an on-chip real-time OS suitable for building real-time information processing. In particular, real-time information processing on an embedded system (Embedded System) composed of a CPU and dedicated hardware, or an on-chip embedded system (On Chip Embedded System) integrating them on one chip On-chip real-time OS suitable for building
Is to provide. For this reason, the type of application, the configuration method using the task of the application, and the like are not particularly specified here. In addition, the configuration method of a computer (CPU) which is hardware or an embedded system composed of a CPU and dedicated hardware, or an on-chip embedded system integrated on one chip is also specified in particular herein. It is not where to do.

In other words, the on-chip real-time OS according to the above-described embodiment can provide extremely effective means for the following items which are requirements for software that is becoming larger and more complicated in on-chip embedded systems. it can.

Control of a plurality of hardware resources A plurality of hardware resources can be controlled using the multitask function. It is possible to independently design tasks for different processing units. Each task can be designed without considering the dependency on other tasks by the multitask function provided by the on-chip real-time OS.

Real-time performance Scheduling is performed by an on-chip real-time OS, and real-time performance is guaranteed. Therefore, it is not necessary to design software in consideration of deadlines between different processes. Also, the interrupt management is excellent in the responsiveness of the interrupt.

Resource Exclusive Control Resources can be easily shared between tasks using system calls provided by the on-chip real-time OS.

Anomaly processing With the support of interrupt management, an abnormality can be immediately detected and appropriate abnormality processing can be performed.

Further, the above-described embodiment is applied to the multiplexing (MU) of video / audio / user streams defined by the MPEG2 system.
X) When applied to the processing, when the protocol processing device disclosed in Japanese Patent Application No. 8-75346 is applied as hardware, and when the above-described embodiment is used as the software, it is extremely easy to perform the indispensable in the MUX processing. Since complex real-time processing can be realized, the conventional MU
It is possible to easily change or add functions, which are difficult with the X software.

The protocol processing apparatus disclosed in Japanese Patent Application No. 8-75346 converts data in a plurality of input streams input from a plurality of input ports according to a predetermined syntax into data assembling data. Disassembly, insertion,
In a protocol processing device that performs processes such as deletion, processing, rearrangement, and outputs as a plurality of output streams to a plurality of output ports, a buffer memory configured with a two-port memory and storing a part of an input / output stream; A write control unit that controls an operation of writing a plurality of input streams to a first port of the buffer memory; a read control unit that controls an operation of reading a plurality of output streams from a second port of the buffer memory; A data memory that is configured with a memory and temporarily stores work data in order to execute syntax processing, refers to data in the buffer memory, reads the data, and implements the syntax processing using the data memory. A program that implements a process of writing the syntax-processed data to the buffer memory. And a Gram possible syntax processing control unit is a device which realizes a predetermined protocol processing. The protocol processing in the protocol processing device may be executed as the predetermined real-time processing.

Further, application of the on-chip real-time OS according to the above-described embodiment simplifies the design of an application (application software) in the on-chip embedded system, and can shorten the TAT of software development. Further, as a task, by making software into components for each of a plurality of functions, not only can functions be easily changed or added, but also the reuse of software functional components is easy. Thereby, for example, a video encoder, a video decoder, an audio encoder, an audio decoder compliant with MPEG2, multiplexing (MUX) processing and demultiplexing (Demultip) defined by the MPEG2 system are performed.
It is also possible to configure processes and the like as individual software functional components, and to execute them at the same time by using an on-chip real-time OS in a time-division manner and with a guaranteed real-time property.

Since the on-chip system is expected to continue to increase in scale and complexity with the advance of integrated circuit technology, mounting the on-chip real-time OS according to the above-described embodiment in an on-chip embedded system requires: This is extremely effective for improving the efficiency of complex software development.

As described above, in the multimedia era based on the future network technology, the role of the new on-chip real-time OS capable of realizing the small size, economy, and VLSI provided by the above embodiment is invaluable. .

In the above-described embodiment, an on-chip system in which the CPU and dedicated hardware are used or an integrated system in which the CPU and dedicated hardware are integrated on a single chip is used.
On-chip real-time O on embedded system
S21, 22, and 23 are mounted, but one C
On-chip real-time OS 21, 22, 2 on PU
3 may be implemented.

[0065]

According to the present invention, real-time information processing can be built on an information processing system having a very small amount of installed memory, and therefore, a new on-chip realizing a smaller and more economical than conventional on-chip real-time OS. A chip real-time OS can be realized. In particular, an on-chip real-time OS is an embedded system composed of a CPU and dedicated hardware.
On-chip embedded system (On Chip Embedded System)
tem) on the order of several kB, so that the on-chip real-time OS can be reduced in size, economical, and VLSI.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an on-chip real-time information processing apparatus IS1 including an on-chip real-time OS 21 according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an on-chip real-time information processing apparatus IS2 including an on-chip real-time OS 22 according to a second embodiment of the present invention.

FIG. 3 is a diagram showing 18 system calls for implementing task management, interrupt management, and semaphore management in the embodiment.

FIG. 4 is a block diagram showing a task management unit 21a according to the embodiment;
It is a figure which shows the example in which the task in 22a changes state.

FIG. 5 is a diagram showing an example of a multitask function and a scheduling function in the task management means 21a and 22a of the embodiment.

FIG. 6 shows interrupt processing means 21b and 22 in the embodiment.
It is a figure which shows b specifically.

FIG. 7 illustrates a semaphore management unit 21c according to the embodiment.
It is a figure which shows 22c specifically.

FIG. 8 is a diagram illustrating an on-chip real-time information processing apparatus IS3 including an on-chip real-time OS 23 according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a specific example in a case where the third embodiment is applied to an MPEG2 system.

FIG. 10 is a diagram showing a specific example in a case where the third embodiment is applied to an MPEG2 system.

FIG. 11 is a diagram illustrating a relationship between software requirements and functions of a real-time OS realizing the requirements.

FIG. 12 is a diagram illustrating a relationship between a dynamic memory amount targeted by the on-chip real-time OS of the present invention and a dynamic memory amount of an existing real-time OS.

[Explanation of symbols]

IS1, IS2, IS3: On-chip real-time information processing device, 11: CPU, 12: Dedicated hardware, 12a, 13a: Core CPU, 13: MUX LSI, 21, 22, 23: On-chip real-time OS, 21a, 22a, 23a: task management means, 21b, 22b, 23b: interrupt processing means, 21c, 22c, 23c: semaphore management means, 31, 32, 33: application.

Claims (5)

[Claims] 1. An on-chip real-time OS that processes a plurality of tasks on a single CPU in a time multiplex manner and guarantees that all tasks are called within a predetermined time. A task having a multitasking function that is a function of processing a task with high priority and a preemptive scheduling function that is a function of processing a task with a higher priority with priority over a task with a lower priority assigned to each of the tasks. Management means; interrupt management means having a function of receiving an interrupt event during execution of a task of any priority; and semaphore management means having an exclusive control function of information exchange between a plurality of tasks. And realizing predetermined real-time information processing.
S. 2. An embedded system, which is an information processing device configured by one CPU and dedicated hardware and performing processing while exchanging information between the CPU and the dedicated hardware. In an on-chip real-time OS that processes a plurality of tasks in a time-multiplexed manner and guarantees that all tasks are called within a predetermined time, a multi-function is a function that independently processes a plurality of tasks in a time-multiplexed manner. Task management means having a task function and a preemptive scheduling function for processing the higher priority task preferentially over a lower priority task assigned to a plurality of tasks; Interrupt management means having a function of receiving an interrupt event even during execution of a task; A semaphore management means having an exclusive control function of the information exchange between disk;
And an on-chip real-time OS that realizes predetermined real-time information processing. 3. The task management device according to claim 1, wherein the task management means includes: a means for generating the task; a means for activating the task; a means for ending the task; Means for deleting, means for forcibly terminating other tasks,
A means for generating a periodic task that is a task that is started periodically, a means for starting the periodic task, a means for terminating the periodic task, a means for deleting the periodic task, and the cycle Means for forcibly terminating other periodic tasks other than tasks, and means for acquiring own task ID information, wherein the interrupt management means includes means for defining an interrupt handler, and cancellation of the interrupt handler definition. Semaphore management means, a semaphore generation means, a semaphore operation means, and a semaphore deletion means. Each of the above means provided in the management means,
On-chip real-time processing, comprising: initialization means for activating each of the means provided in the interrupt management means and each of the means provided in the semaphore management means to realize predetermined real-time information processing. OS. 4. The on-chip real-time OS according to claim 1, wherein the on-chip real-time OS is configured on a single chip to realize predetermined real-time information processing. OS. 5. The method according to claim 1, wherein data in a plurality of input streams input from a plurality of input ports is assembled, decomposed, inserted, and processed according to a predetermined syntax. In a protocol processing device that performs processes such as deletion, processing, rearrangement, and outputs as a plurality of output streams to a plurality of output ports, a buffer memory configured with a two-port memory and storing a part of an input / output stream; A write control unit that controls an operation of writing a plurality of input streams to a first port of the buffer memory; a read control unit that controls an operation of reading a plurality of output streams from a second port of the buffer memory; A data memory configured to temporarily store work data to execute syntax processing, and A programmable syntax processing control unit that references and reads data in the buffer memory, implements the syntax processing using the data memory, and writes the syntax-processed data to the buffer memory. An on-chip real-time OS, comprising: executing a protocol process for realizing a predetermined protocol process as the predetermined real-time process.