JPH1127157A - Fast trellis coding and decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a device for constructing a fast trellis code for PSK(phase shift keying) modulation which is encoded and decoded by using an encoder and a decoder for punctured convolutional coding of 1/2 coding rate and to design trellis encoder and decoder for 8-PSK, specially for coding in 5/6 coding rate. SOLUTION: One set on N input data bits is received by a decoder 1. Input bits i1 ,..., ik of the encoder 1 are convolutionally encoded by using an encoder with k/(k+1) coding rate based on a punctured coding rate 1/2 convolutional encoder 1. Coded signals a1 , a2 ,..., ak and ak+1 are supplied to a multiplexer 2 together with residual input bits ik+1 , ik+2 ,..., iN. The multiplexer 2 connects a coded signal with residual input data bits and supplies a set of data to an M element modulator 3. Each set consists of log2 M elements and is continuously supplied to the modulator 3 for transmission.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to data communication. In particular, the invention relates to a new and improved method for encoding and decoding trellis modulated data based on previous punctured codes.

[0002]

2. Description of the Related Art In the field of data communication, limited SN
There is an interest in improving the data throughput of transmission systems having a ratio (SNR). System trade-off by using error correction circuit configuration such as Viterbi complex
(tradeoffs) with a lower SNR and a higher data rate at the same bit error rate (BE
R). The required reduction in SNR is
Generally referred to as coding gain. The coding gain can be determined from a similar bit error performance curve. In the graph of a similar bit error performance curve, the BER of the uncoded data and of the various information rate data is plotted against Eb / No. Where Eb is the energy per bit and No is the Gaussian white noise energy per bit. The coding gain at any point along the bit error performance curve for a particular BER level is determined by subtracting the coded Eb / No from the uncoded Eb / No. Published in October 1971, Bulletin on IEEE Communication Technology, VOL.
COM-19, 835-848; A. Helle
r. M. A similar detailed result for various decoding devices is reported in the book "Viterbi Coding for Satellite and Space Communications" by Jacobs. Coding rate
(coding rate) and constraint length are used to define a Viterbi decoder. The coding rate (m / n) corresponds to the number (n) of coding symbols created for a given number of input bits (m). A coding rate of 1/2 is one of the most common coding rates, but other coding rates are also commonly used. One class of codes with m ≠ 1 is called punctured codes and is created by removing, or erasing, symbols from a code 1 / n code. The constraint length (K) is the length of a convolutional code used for encoding data. A constraint length of K = 7 is typical in convolutional coding schemes. The convolutional encoder can be thought of as a finite impulse response (FIR) filter with binary coefficients and length K-1.

[0003] The basic subject of the Viterbi algorithm is to employ a convolutionally encoded data stream transmitted on the noise channel, and to determine the transmitted bit stream by using a convolutional code. The use of characteristics. The Viterbi algorithm is an effective way for computers to update the conditional probabilities of all 2K ^-1 states. To calculate this probability, all 2 ^K-1 conditional probabilities for each bit must be calculated. The result of each of these calculations is stored as a single bit in the path memory.

[0004] A chainback operation, the inverse of the encoding operation, is performed, where the p · 2 ^K-1 decision bits are used to select the output bits. Where p is the path memory depth. After many situations, the most probable path is selected with high certainty. The path memory depth must be long enough to allow this possibility to approach 1. Coding rate 1
For a code of / 2, an exemplary path memory depth is about (5
K) or 35 states. For 7/8 punctured codes, the optimal depth increases to 96 states.

[0005] A constraint length of K less than 5 is too small to provide any substantial coding gain, and systems with a K of greater than 7 are typical for implementation as a parallel architecture on a single VLSI device. Too complicated. As the constraint length increases, the number of interconnections in the fully parallel computing section increases as a function of (2 ^K-1 · L). Where L is the state metric calculation (the sta
The number of bits related to accuracy in te metric computations). Therefore, where K is greater than 7, serial computing devices are commonly used, which use large external random access memories (RAMs).

Processing in IEEE Information Theory published in January 1982, VOL. IT-28, pp. 55-67, di.
G. Ungerboeck, "Channel Coding with Multilevel / Phase Signals (Channel Coding wi
th Multilevel / Phase Signal) "describes trellis code modulation (TCM). In Ungelboeck, within a given spectral bandwidth, (n-
1) The asymptotic coding gain can be increased to 6 dB by using a / n rate convolutional code and doubling the signal set. Disadvantageously for each modulation technique and for each bit rate, again maximum coding is achieved with different convolutional codes. In addition, some rate and modulation techniques and search results for all convolutional codes for the best code presented are disclosed.

[0007] IEEE Communication Magazine, July 11th, pp. 11-19, A.I. Jei. Viterbi, Jei. Kei. Wolf, A. Zehavey and Earl. A practical approach to trellis code modulation (PTCM) is disclosed in the book "A Practical Approach to Trellis Code Modulation" by Padbaani. Trellis coding is an attractive coding technique because it has aspects that other coding techniques lack. The power of trellis coding lies in the fact that the decoder can provide error correction on all bits, even if no obvious coding operation is performed on other bits than the least significant digit of the input data . In general, the use of TCM techniques to achieve efficient use of power bandwidth resources has been limited to low speed applications in digital signal processor implementations. PTCM
Using the technology allows VLSI implementations of the encoder / decoder to operate at high speeds. Decoders using PTCM are binary PSK (BPSK), orthogonal PSK
Different modulation techniques can be handled, such as M-ary phase shift keying (M-ary PSK), including (QPSK), 8-PSK and 16-PSK.

In the document "Development of Variable Speed Viterbi Decoder and Its Operating Characteristics" at the 6th International Conference on Digital Satellite Communications in Oenix, Arizona, 1983,
Y. Yasuda, Y. Hirata, K. Nakamura and S.M. Otani is a class of fast binary convolutional codes
We discussed a method that can be constructed from a single low-speed binary convolutional code. The advantage of a punctured code for binary transmission is that the encoder and decoder for the entire class of codes is a single code for the rate 1/2 binary convolutional code from which the fast punctured code is derived. Can be easily configured by changing the encoder and decoder. A recent invention was the de-facto,
(A de facto industry standard) A (m-1) / m rate binary convolutional code (m is a positive number of 3 or more) formed by puncturing a specific coding rate 1/2 convolutional code that becomes a standard. ). This code has a constraint length of 7 and a generator polynomial G1 (D) = 1 + D
² + D ³ + D ⁵ + D ⁶ and G 2 (D) = 1 + D ² + D ³ +
Having a D ^6. In fact, many commercial VLSI convolutional encoder and decoder chips (including devices marketed by Calcom of San Diego, Calif. Under Part No. Q1875) have implemented the rate-1 / 2 code of this de facto standard. It has an encoder and a decoder for the punctured binary code to be used.

[0009]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a novel method and circuitry for encoding and decoding trellis data using a punctured code rate 1/2 convolutional encoder. That is.

[0010]

SUMMARY OF THE INVENTION The present invention relates to a new and improved method and apparatus for encoding and decoding trellis modulated data based on a punctured code rate 1/2 convolutional code.

In accordance with the present invention, a trellis encoder and decoder are disclosed, in which a punctured code rate of 1
A decoding and decoding circuit based on / 2 convolutional coding is provided. In a coding rate 5/6 punctured trellis encoder for 8-PSK modulation, each input data bit set is composed of 5 bits. Code rate 7/8
In a 16-PSK modulation scheme that utilizes encoding, each set of input data bits consists of 7 bits. In a general M-PSK modulation scheme using (log ₂ M-1) / log ₂ M coding rate,
Each set of input data bits consists of log ₂ M-1 bits. The encoder receives a set of input data bits of a continuous set of input data bits, encodes a subset of the input data bits according to a punctured convolutional code, and groups the output symbols. Typically a group of 3 or 4 bits then passes through an 8 or 16 element modulator.

The combiner uses a Viterbi combiner to generate an error-corrected estimate of the original data. The Viterbi demultiplexer uses branch metrics in the demultiplexing process developed from information included in the phase of the received signal. The Viterbi decoder output symbols are convolutionally encoded to produce corresponding recoded symbols used in the recovery of the uncoded symbols. The re-encoded symbols from the convolutional encoder are provided to error correction logic with an uncorrected estimate of the transmitted data based solely on the received phase of the modulated data. Error correction logic checks according to the re-encoded bits, and an uncorrected initial estimate of the transmitted data provides a corrected estimate of the transmitted data.

In an alternative and improved implementation, additional circuitry is provided to resolve phase ambiguities that are not resolvable in previous Viterbi combiner implementations. In this alternative and improved implementation, each uncoded input data bit is coded differentially by convolutionally coded bits by a punctured convolutional coder.

In an improved implementation, the complex requires additional circuitry to resolve phase ambiguity. This additional circuit has a differentiator and a data buffer. The derivative combiner differentially combines the unprotected data bits with respect to the protected bits.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

[0016] The features, objects and advantages of the present invention will become more apparent from the detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals are used to identify like parts throughout the drawings. . Puncturing (puncturin) for binary transmission
g) is a method capable of forming a high coding rate binary convolutional code from a single low coding rate binary convolutional code. The advantage of the punctured code for binary transmission is that the encoder and decoder for all classes of codes is a single unit for the rate 1/2 convolutional code where the high rate punctured code is the source. Can be easily configured by changing the encoder and decoder. In the present invention, a typical embodiment is a coding rate (m-1) / m2 formed by puncturing a coding rate 1/2 specific convolutional code, which has become a de facto standard in the communication industry.
The original convolution code (m is a positive integer of 3 or more) is used.
In an exemplary embodiment, reference numeral generating polynomial constraint length 7 G1 (D) = 1 + D 2 + D 3 + D 5 + D 6 and G2 (D) =
And a ^{1 + D + D 2 + D} 3 + D 6. In fact, many commercial VLSI convolutional encoder and decoder chips (including the aforementioned Q1875 from Calcom)
Has an encoder and a decoder for punctured binary encoding using a coding rate 1/2 of this de facto standard.

A high code rate punctured code has a smaller free Hamming distance than the original non-punctured code. For example, the constraint length 7 code described above has a free Hamming distance equal to 10. When punctured to form a higher code rate code, the minimum free Hamming distance is reduced as shown in Table 1 below.

[0018]

[Table 1] In an alternative embodiment, the puncturing-free rate-1 / 2 convolutional encoder and decoder is an engine for configuring a high-rate trellis encoder and decoder for PSK trellis-coded modulation. Can be used. Recent inventions include the basic building block (bui
high coding rate P using a punctured encoder and decoder for a coding rate 1/2 convolutional code as a coding block)
It shows how to configure the encoder and decoder for SK trellis coding. The implementation of those codes is superior to the codes in alternative embodiments for wide range code rates. A comparison of the codes formed from the two techniques for trellis coded 8-PSK and 16PSK modulation is shown in Table 2 below.

[0019]

[Table 2] A comparison of some executions of those codes with known codes is given in Table 3 below.

[0020]

[Table 3] Another measure of trellis code quality, where the encoder and decoder use a binary convolutional encoder and a matched Viterbi decoder as their authority, is the maximum bit rate (bits / second) that can be supported by a single chip. ). Coding rate 1/20 at 20Mbit / s (in case of Q1875 chip)
A comparison of the maximum bit rate achieved using a single chip capable of decoding two binary convolutional codes is given in Table IV below. From the table, it can be seen that the codes discussed in the present invention have better free square Euclidean distances than the alternative embodiment codes, but have lower maximum transmission rates than those codes for single chip implementation. Can be seen. Table 4 shows 20 codes for a code rate 1/2 convolutional code.
Consider the case for maximum transmission rates for trellis coded 8-PSK and 16-PSK modulation assuming megabits / second.

[Table 4] A typical series of implementations is 8-PSK and 16-PSK based on a punctured code rate 1/2 binary convolutional code.
Presented for trellis coded modulation. Assume that through all zeros, the phase of the PSK carrier is exactly known to the receiver, and that the only perturbation is additive white Gaussian noise. Improvements to mitigate phase ambiguity are described at the end of the description of the detailed embodiment.

In FIG. 1, a set of N input data bits is received at encoder 1. K of encoder 1 (bit i1,
..., ik) are convolutionally coded using a coding rate k / k + 1 coder based on a punctured coding rate 1/2 convolutional coder 1. The encoded symbols (a1, a2,..., Ak, ak + 1) are supplied to the multiplexer 2 together with the remaining input bits (ik + 1, ik + 2,... IN). Multiplexer 2 combines the encoded symbol with the remaining input data bits and provides an M-ary modulator 3 with a data set. Each set is composed of log ₂ M elements and is continuously supplied to the M-ary modulator 3 for transmission.

In the exemplary embodiment shown in the remaining figures, a specific mapping between the binary bits and the phase of the PSK signal
(mapping) is assumed. For 8-PSK, this mapping is 0 ^o = 000,45 ^o = 001,90 ^o = 0
10,135 ^o = 011,180 ^o = 100,225 ^o
= 101, 270 ^o = 110, and 315 ^o = 111. For 16-PSK, this mapping is 0 ^°
= 000,22.5 ^o = 0001,45 ^o = 0011,
67.5 ^o = 0010, 90 ^o = 0100,112.5
^o = 0101,135 ^o = 0111,157.5 ^o = 0
110,180 ^o = 100,202.5 ^o = 1101,
225 ^o = 1111,247.5 ^o = 1110,270
^o = 1000,292.5 ^o = 1001,315 ^o = 1
011, and 337.5 ^o = 1010. An array of mappings can easily be created for a high code rate M-ary modulation scheme using this scheme. Modulated giray (G
Although the (ray) coding scheme is illustrated using examples in this mapping, it is not critical to the invention so that other mapping schemes can be devised.

Referring to FIG. 2, the codes (i1, i2, i3, i4,
Five input lines labeled i5) are provided to the encoding circuit. These lines are two single lines i1 and i2, and 3
It is organized by a bundle of book lines (i3, i4, and i5). Three lines
(i3, i4 and i5) are used as inputs to the punctured coding rate 1/2 convolutional encoder 11. For example, puncturing, after input i3, taken from coder 11 both outputs convolution (shown as a and b), after the input i4 (polynomial G1 (D) = 1 + D 2 + D 3 + D ⁵ +
Corresponding to D ⁶⁾ only one output is taken out (shown as c) and after the input i5 (polynomial G2 (D)
The other output (corresponding to = 1 + D + D ² + D ³ + D ⁶ ) is taken (shown as d). Two lines i1 and i2
Is said to carry "uncoded" binary digits, while the three lines i3, i4 and i5 are said to carry "coded" binary digits. Four binary digits a, b,
c and d are grouped with uncoded binary digits as shown to provide 6 binary digits at the output on the 6 mains. These lines are the three lines ((i1,
a, b) and (i2, c, d). The three bits in each bundle should be considered a three-bit octal number, where i1 and i2 are the most significant digits in each of the three-bit numbers.

Each of the two sets is provided to a multiplexer 12, which is connected to an eight-way
Provides a bit octal number. Each octal number has two trellis coded modulators 13 for each 5-bit input.
Mapped to one 8-PSK signal so that K can be generated. The code is called a code rate 5/6 trellis code for 8-PSK modulation. Uncoded 8-PSK
Assuming that can transmit information at 3 bits / Hz, this code will transmit information at 2.5 bits / Hz.

For each transmission phase, the receiver processes the received waveform and outputs a pair of real numbers (or one complex number) denoted by "I" or "Q". These two complex numbers (corresponding to the receiver output for the two transmission phases) are then used as inputs to the decoder for trellis coding. It is assumed that this decoder uses a Viterbi decoder matched to a punctured code rate 1/2 convolutional code as an engine. The branches of the trellis on which the Viterbi decoder operates are labeled by pairs (a, b), (c, x) and (x, d). Here, x indicates an erasure symbol. Thus, prior to Viterbi decoding, appropriate branch metrics for each (a, b), (c, x) or (x, d) value must be calculated. The first pair of complex numbers is 4 for (a, b)
The next pair of complex numbers is used to obtain two branch metrics for (c, x) and (x,
Used to obtain two branch metrics for d), and then the process is repeated. (A, b)
The calculation of the branch metric for is performed in the usual way.
That is, for each of the four values that (a, b) can assume, the squared Euclidean distance to the two nearest signal points corresponding to the value of (a, b) is calculated. To calculate the distance for the value (c, x) at c = 0 and c = 1, the squared Euclidean distance to the four nearest signal points compatible with the value of c is calculated. The same is done for the distance for (x, d), using the same complex numbers. The above discussion is in Q187
In the case for 5 chips, it is assumed that the externally generated branch metrics can be used by the decoder.
If this is not the case, it is instead pre-distorted by a number in order to artificially obtain the desired branch metric.

At this point in the decoding algorithm, since it is not known which branch is selected by the Viterbi decoder, the information required to select the best value for the uncoded digits is obtained. Must accumulate. There are several ways to store this information. The most obvious way is to store two (I, Q) pairs. A more effective storage method is (j-1) (360 °) for each (I, Q) pair.
/ 8) <tan ^-1 (Q / I) <j (360 ° / 8). This requires 3 bits for each (I, Q) pair. The value of "j" is referred to as "sector-information." Two values of "j" and (a, b) or (c,
Given the value of d), the best choice for two uncoded binary digits can be determined.

The Viterbi decoder then operates in the usual way to select the best path with a rate 1/2 code trellis. The output of this decoder is the bits estimated on lines i3, i4 and i5. This bit stream is then re-encoded by the trellis to produce a continuous best estimate of (a, b), (c, x) and (x, d) corresponding to the best path. . As mentioned earlier, this information along with the sector information is sufficient to provide an uncoded bit stream.

The PSK signal is a unit circle.
Assuming that it is positioned above, the least square Euclidean distance between parallel transitions is 4.0. Since the code rate 3/4 punctured code used has a free Hamming distance of 5, the trellis code must be at least 5
^* (2 ^* sin (22.5 °)) ² = Free square Euclidean distance of 2.929. This is the case due to the particular mapping chosen to map the three binary digits to the phase of the 8-PSK signal. In particular, if the two least significant figures differ at one location, the corresponding squared Euclidean distance between the phases is at least (2
^* Sin (22.5 °)) ² . However, if the two least significant figures differ at the two positions, the squared Euclidean distance between the phases is at least 2 ^* sin
(45 °) ² > 2 (2 ^* sin (22.5 °) ^2. Thus, the free Hamming distance 5 for the coding rate 3/4 convolutional code is 5 ^* (2 ^* sin (22. sin). 5 °))
² = 2.929 free square Euclidean distance. If a rate 3/4 punctured code is used, whose free Hamming distance is at least 7, then 7 ^* (2 ^* sin (22.5 °)) ² > 4
, The parallel transition dominates. The operation of a code rate 7/8 punctured trellis code for 16-PSK is similar to a 5/6 punctured code with grouping as shown in FIG. The operation of this encoder is similar to that for the encoder of FIG. 2 now having seven input bits. The encoder 21 is, as discussed with reference to FIG.
Generate 4 symbols from input bits. The two uncoded input bits are paired with the two coded bits from encoder 21 to form two 4-symbol groups that are provided to multiplexer 22. Multiplexer 22 continuously provides the 16-symbol modulator 23 with four groups of symbols. To generate two 16PSK signals for each 7-bit input, modulator 23
The hex number is mapped to a 16PSK signal.

Assuming that the PSK signal is located on a unit circle, the least square Euclidean distance between parallel transitions is 2.00. Due to the similarity to that given in the previous example, the trellis code is at least 5 ^* (2 ^*
sin (11.25 °)) ² = 0.761 free squared Euclidean distance. If a rate 3/4 punctured code whose free Hamming distance is at least 14 is used, then 14 ^* (2 ^* si
n (11.25 °)) ² > 2, so the parallel transition dominates.

The encoding circuit of FIG. 4 maps eight input bits to three 8PSK signals. There is a bundle of three signal lines i1, i2 and i3 and five lines (i4, i5, i6, i7 and i8) to the coding circuit.
The bundle of five lines (i4, i5, i6, i7 and i8) is supplied to a punctured code rate 1/2 convolutional encoder 31. The puncturing consists in that, with an input i4, both outputs are obtained from the convolutional encoder (indicated by a and b), by an input i5 only a first output is obtained (indicated by c) The input i6 provides a second output (denoted as d) and the input i7
Again yields only the first output (denoted as e), and the input i8 yields only the second output (denoted as f). The three lines i1, i2 and i3 are said to carry "uncoded" binary digits, but the five lines i4, i5, i6, i7 and
i8 is said to carry "coded" binary digits.

Six binary digits a, b, c, d, e
And f are grouped together with uncoded binary digits in the manner shown to produce nine binary digits as output on nine lines. These lines are divided into three bundles each consisting of three lines ((i1, a, b), (i2, c, d), and (i3, e, f)). The bundles are connected to a multiplexer 32 and continuously feed the data to the octal modulator 33 by way of those lines. The three bits in each bundle are considered to be a three-bit octal number, where i1, i2 and
The bit labeled i3 is a 3-bit number (3-bit n
umbers). Each octal number is one 8-bit signal such that the trellis coded modulator generates three 8-PSK signals for each 8-bit input.
Maps to a PSK signal. The code is called an 8/9 trellis code for 8-PSK modulation. Uncoded 8-PS
Assuming that K can transmit information at 3 bits / Hz, this code transmits information at 2.67 bits / Hz.

For each transmission phase, the receiver processes the received wave and outputs a pair of real numbers (or one complex number) indicated by "I" and "Q". Those complex numbers (3
(Corresponding to the receiver output for the transmission phase) is then used as input to the decoder for trellis coding.
This decoder is assumed to be used as a Viterbi decoder and engine matched to a punctured code rate 1/2 convolutional code. The branches of the trellis on which the Viterbi decoder operates are labeled by pairs (a, b), (c, x), (x, d), (e, x) and (x, f). Here, x indicates an erasure symbol. Thus, before Viterbi decoding, (a, b),
The appropriate branch metric for each of the (c, x), (x, d), (e, x) or (x, f) values must be calculated. That is, the first pair of complex numbers is used to obtain a four-branch metric for (a, b). The next pair of complex numbers are (c, x) and (x,
d) is used to obtain a two-branch metric for, and the next pair of complex numbers is used to obtain a two-branch metric for (e, x) and (x, f), then the process is Repeated. Again, for the case of the Q1875 chip, it is assumed that the externally generated branch metrics can be utilized by the decoder, or that their inputs can be pre-distorted to provide the desired branch metrics. You.

At this point in the decoding algorithm, since it is not known which branch is selected by the Viterbi decoder, the information required to select the best value for the uncoded digits is obtained. Must accumulate. There are several ways to store this information. The most obvious way is to store two (I, Q) pairs. A more effective storage method is (j-j) for each (I, Q) pair.
1) To determine the value of j so that (360 ° / 16) <tan ^-1 (Q / I) <j (360 ° / 16). This is for each (I, Q)
Requires 4 bits per pair. The value of "j" is referred to as "sector-information." Three values of "j" and (a, b), (c, d)
Or, given the value of (e, f), the best choice for uncoded binary digits can be determined. The Viterbi decoder then operates in the usual way to select the best path with a rate 1/2 code trellis.
The output of this decoder is the bits estimated on lines i3, i4, i5, i6, i7 and i8. This bit strium is then trellised into the sequence (a, b, c, d,
e, f) is re-encoded to make the best estimate. As mentioned earlier, this information along with the sector information is sufficient to provide an uncoded bit stream.

Assuming that the PSK signal is located on a unit circle, the least square Euclidean distance between parallel transitions is 4.0. Since the code rate 5/6 punctured code used has a free Hamming distance of 4, the trellis code must be at least 4 ^* (2 ^* s).
in (22.5 °) ² = 2.343. If a rate 3/4 punctured code with a free Hamming distance of at least 7 is used, then the parallel transition dominates.

Referring to FIG. 5, the operation of a code rate 11/12 punctured trellis code is similar to a code rate 8/9 punctured code with groups as shown in FIG. The operation of this encoder is similar to that for the decoder of FIG. 4 now with 12 input bits. Encoder 41 produces six symbols from the five input bits as discussed with reference to FIG. The two uncoded input bits are paired with the two coded bits from encoder 21 and
Form three four symbols that are subjected to two. Multiplexer 42 provides the 16 symbol modulator 43 with four consecutive symbols.
Each six number is mapped to a 16-PSK signal such that modulator 23 generates three 16-PSK signals for each 11-bit input.

Assuming that the PSK signal is located on a unit circle, the least square Euclidean distance between parallel transitions is 2.00. Since the coding rate 5/6 punctured code used has a free Hamming distance of 4, the trellis code must be at least 4 ^* (2 ^* si
n (11.25 °)) ² = 0.609. If a code rate 5/6 punctured code is used, whose free Hamming distance is at least 14, then the parallel transition dominates.

The examples for 8-PSK and 16-PSK described in the previous section were aligned as a punctured binary code rate 1/2 convolutional encoder and its basic building block (building bl0ck). Use a Viterbi decoder. However, the basic approach is used with any punctured code convolutional code and any modulation scheme. How to construct a trellis code for 2 ^k-ary PSK modulation (k> 3) based on any punctured convolutional code is described below. Since high code rate codes are a fundamental concern, the description only concerns the construction of code rate (km-1) / km trellis codes. Here, m is an integer greater than 2.

The coding rate exceeding 2 ^k source (km-1) / km of PS
The K-modulation trellis code encodes (km-1) binary digits from 2 ^k-ary PSK modulation to m symbols. If one uncoded binary digit is used for each 2 ^k-ary symbol, then m uncoded inputs and ((km-1) -m) = ((k-1) m-1) code It is the sum of the conversion inputs. This is the coding rate ((k-1) m-1) / (k-1) m
Means a person using a punctured convolutional code. The (k-1) m outputs of the binary convolutional encoder are distributed to m groups. Each of the m groups has (k-1) binary digits. The (k-1) binary digits from each group are combined with one uncoded digit (with the unsigned digit being the k most significant digit). The result is a bundle of m, which is then mapped to m2 ^k-ary symbols. Since the uncoded digits represent parallel transitions in the decoder trellis for the trellis code, the least squares Euclidean distance between the parallel transitions is equal to 4 (PSK signals are equally aligned on the unit circle and the maximum effective Assume that the signal, which differs only in numbers, is on the diameter of the circle). If the coding rate ((k-1) m-1) / (k-1)
m punctured convolutional code is free hamming distance d1
, The free squared Euclidean distance of the trellis code is equal to 4 and the minimum number of d1 (2 ^* sin (360 ° / ^{2k + 1} )) ² .

However, consider that two uncoded binary digits are used for each of the m2 ^k-ary symbols.
Then, 2m coded input and ((km-1) -2m) = ((k-2) m-
1) There will be a sum of the coded inputs. This is the coding rate
This means using a punctured convolutional code for ((k-2) m-1) / (k-2) m. Binary convolutional encoder (k-
2) m outputs are distributed to m groups. Each of the m groups has (k-2) binary digits. The (k-2) binary digits from each group are combined with the two uncoded digits (with the two most significant unsigned digits of the K digits) to form a bundle of K binary digits. You. The result is a bundle of m, which is then mapped to m2 ^k-ary symbols. Since the uncoded digits represent parallel transitions in the decoder trellis for the trellis code, the least square Euclidean distance between the parallel transitions is equal to 2 (PSK
The signals are arranged equally on the unit circle, and the signals differing only within the two largest effective numbers are 90 ° or 18 °.
Assume that they are separated by any of 0 °). If the coding rate ((k-2) m- 1 / (k-2) if m punctured convolutional sign of having a free Hamming distance d2, then the free squared Euclidean distance of the trellis signs 2 and d ₂ ( 2 ^* sin (360 ° / 2 ^{k + 1} )) Equal to the minimum number of ² .

It can be envisaged to have more than two uncoded bits for each of the m2 ^k elementary symbols. It is conceivable that simply on the basis of obtaining a trellis code together with the maximum free square Euclidean distance, the number of uncoded bits per 2 ^k elementary symbol should be chosen. However,
The choice of the number of uncoded bits per 2 ^k source symbol also affects the maximum transmission rate in a single-chip implementation.
For example, assume that P uncoded bits are used for each of the m2 ^k elementary symbols, so that a code rate ((kp) m-1) / (kp) m punctured convolutional code is required. Assume. Assume that this code is formed by puncturing a rate 1/2 convolutional code. Here, puncturing is such that one pair of outputs is obtained from the encoder and one of the two outputs for the next (kP) m-2 input is punctured. If the chip implementing this punctured code can operate at a maximum information rate of 20 Mbit / s, then a single chip implementing the trellis code would be 20 ^* km
It can operate at a maximum information rate of / ((kp) -1) megabits / second. Note that this maximum rate is a monotonically decreasing function of p, so that p = 1 gives the maximum information rate for a single-chip implementation.

In the detailed description of the exemplary embodiment, it has been assumed to the end that the receiver has complete knowledge of the phase of the transmitted carrier. Means can be described that can relax this assumption in an improved implementation. The discussion is in Example 1 (code rate 5 / for 8-PSK modulation).
(6 trellis codes), but the technique can be used for any of the codes described in the description.

The mapping for 8-PSK modulation is: 0 ° = 0
00, 45 ° = 001, 90 ° = 010, 135 ° = 0
11,180 ° = 100,225 ° = 101,270 °
Recall that = 110, 315 ° = 111. For a phase shift of 45 °, 135 °, 225 ° and 315 °, exactly one of the two least significant numbers is complemented. The effect is as if 2
It is as if the original digits were transmitted over a binary symmetric channel with an error rate of 50%. A Viterbi decoder trying to decode those digits will see a very rapid growth of all its path metrics. The effect is to greatly increase the frequency of this normalization, which can be detected, since their path metrics must be normalized whenever they are too large. Whenever this occurs, the phase reference is 45 °
It can be increased or decreased.

However, 90 °, 180 °, and 270 °
In the case of the phase ambiguities of, for the hypothesized mapping, this set of phase shifts will be either one of the two least significant complements, or the two most significant complements It doesn't matter. Coding rate 1/2, constraint length 7,
(Defact standard) Convolutional codes have the property that the complement of a codeword is a codeword. Thus, in the absence of other errors, if both of the two least significant numbers are complemented, a Viterbi decoder for convolutional code will produce the correct information sequence complement. . Thus, if the initial input to the convolutional decoder is 1 / (1 + D) (mod2)
If differentially coded using, then, after differential decoding at the receiver, the correct sequence of information for the coded bits will be obtained. Uncoded bits (ie, the largest significant number in the phase mapping)
Challenges remain.

Phase shift 90 °, 180 ° and 270 °
For a set consisting of two vectors, if the binary vector is divided into two sets according to whether their middle bits are 0 or 1, then in each set the maximum significant number is complemented or not is there. this is,
It suggests that the control bits use a controlled differential decoder for uncoded bits that are middle bits in the mapping. Such a controlled differential decoder is shown in FIG. More details on this encoder and its application in trellis coded modulation can be found in US patent application Ser. No. 07/6, filed May 3, 1991, assigned to the assignee of the present invention.
No. 95,397, issued Aug. 3, 1993 in U.S. Pat. No. 5,233,630. The title "Method and apparatus for improving phase ambiguity in trellis coded modulation data" is disclosed. Referring to FIG. 6, the input / output of encoder 50 is a binary stirrer.
ream). If the control signal is 1 (0), the input is directed directly to the upper (lower) differential encoder 52 (53) by the multiplexer 51, and the output from the upper (lower) differential encoder 52 (53) is output by the multiplexer 54. can get. The controlled differential decoder has the same form except that the 1 / (1 + D) circuit is replaced by a (1 + D) circuit.

Referring to FIGS. 7 and 8, there is shown an encoder and decoder for a 5/6 code rate PSK system. In FIG. 7, information bits i1, i2, i3, i4
And i5 are available at the input to the encoder 67. As shown, i1 is the input to the controlled differential decoder 63 and i2 is the controlled differential decoder 64.
And i3, i4 and i5 are 1 / (1+
D). Inputs i3, i4 and i5 produce outputs j3, j4 and j5 in a conventional manner for a 1 / (1 + D) differential decoder well known in the art. An equation describing the output of this differential encoder in terms of input is given by equation (1) below.

(Equation 1) The input j3 is a coding rate 3/4 which produces a pair of outputs a and b.
It is input to a punctured convolutional encoder 62. The pair of outputs (a, b) are bundled together with the output j1 of the controlled differential encoder 63 to be mapped to one of the eight phases.
This is because the multiplexer 65 bundles (j1,
a, b).

We now explain how the output j1 is produced by the controlled differential encoder 63. Line a
The upper signal is a controlled differential encoder 50 shown in FIG.
Control signal. In this example, the input to this circuit on the line labeled "INPUT" entering multiplexer 51 is information bit i1. If the control bit is equal to zero, input i1 is directed by multiplexer 51 to the upper differential encoder circuit labeled 52. Multiplexer 54 then directs the output of upper differential encoder 52 to the output line to form j1. If the control bit is equal to one, input i1 is directed by multiplexer 51 to lower differential encoder 53, and output multiplexer 54 directs the output of lower differential encoder 53 to the output line, forming j1. Two differential encoders 5
The inputs and outputs of 2 and 53 are the same as described above.

We add the following input j4 to the code rate 3/4 punctured convolutional encoder 62: This forms a pair (c, x), as explained earlier. Here, c indicates one of the outputs of 62, and x indicates a punctured bit not shown because this bit is suppressed. Coding rate 3/4 punctured convolutional encoder 6
The next input j5 to 2 forms the output (x, d). Here, d is shown as one of the outputs of 62 and x is another punctured bit that is suppressed and thus not shown as one of the outputs of encoder 62. The pair (c,
d) is now bundled with the output j2 of the controlled differential encoder 64 and mapped to the other of the eight phases. This is because the multiplexer 65 converts the bundle (j2, a, b) into an octal modulator 66.
Occurs when passing through.

The output j2 is formed by the controlled differential encoder 64 in the following manner. The signal on line "a" is the control input to a circuit which is now another copy of circuit 50 shown in FIG. In this example, the input to this circuit (shown as a right-pointing arrow toward device 51) is information bit i2. If the control bit "c" is "0"
If it is equal to, input i1 is directed by multiplexer 51 to upper differential encoder 52, and output multiplexer 54 directs the output of upper differential encoder 52 to the output line, forming j2. If control bit "c" “GA” 1
If it is equal to "", the input i1 is directed by the multiplexer 51 to the lower differential encoder 53 and the output multiplexer 54 directs the output of the lower differential encoder 53 to the output line, forming j2. The equations for the input and output of are the same as described previously.Figure 8 shows a typical decoder for trellis coded modulation of the type discussed herein. 8 exemplary decoders are arranged for decoded 8-PSK modulated data for a rate 5/6 punctured trellis code, but other code rates and modulation types can be easily derived therefrom. It should be understood that

The decoder in FIG. 8 is an extension of a trellis decoder built into a Q1875 chip with additional circuitry for additional uncoded bits.
n). In FIG. 8, an 8-ary PSK demodulator 71 has I
And Q, two sets of phase data, eg (I1, Q1) and (I2, Q2),
And one for each received encoded group for 5/6 encoded data. Both examples (I1, Q1) and (I2, Q2) are provided to a metric calculator 73 for calculating metrics associated with each set of I and Q phase data. The calculated branch metrics are provided to a Viterbi decoder 72 for forming an estimate of the data bits j3, j4, and j5. The bits j3, j4 and j5 are used to form an estimate of the bits i3, i4 and i5 by the differential decoder 82 ((1
+ D).

The examples of (I1, Q1) and (I2, Q2) are supplied to sector calculators 75 and 79, respectively, where a 3-bit sector corresponding to the reception phase of the signal is formed. These sector values are hard decisions (h
ard decison) is an estimate. The values are provided to buffers 76 and 80, respectively, and then to logic 77 and 78.

Bits j3 and j4 are output to the output of the Viterbi decoder 72.
And j5 are also provided to a convolutional encoder 74 for re-encoding the bits in the same manner as they were encoded for transmission. The estimation of j3 is
It is applied to a rate 3/4 punctured convolutional encoder 74, which forms a pair of outputs (a, b). The signal on line "a" is a control bit to the controlled differential decoder 78, shown as 100 in FIG. The input to this circuit on line 105 is an estimate of j1. If the control bit "a" is equal to 0, the input j1 is directed by multiplexer 101 to the upper (1 + D) differential decoder 102 and the output multiplexer 104 is switched to the upper (1
+ D) directs the output of differential decoder 102 to output line 106,
Form an estimate of I. If the control bit is equal to one, the input j1 is lower (1+
D) is directed to differential decoder 103, and output multiplexer 104 directs the output of lower (1 + D) differential decoder 103 to output line 106, forming an estimate of I1.

The equations for the inputs and outputs of the two (1 + D) differential decoders are:

(Equation 2) We must then input the estimate of j4 to the rate 3/4 punctured convolutional encoder 74. As mentioned above, this gives rise to (c, x) where c is 7
4 shows one of the outputs, where x represents a punctured bit not shown because this bit is suppressed. The next input to the rate 3/4 convolutional encoder 74 is an estimate of j5. This produces the output (x, d).
Here, d is shown as one of the outputs of 74, and x is another punctured bit suppressed, and is therefore not shown. The controlled differential decoder 83k output j2 is generated in a manner similar to that generated by j1 controlled differential decoder 78, but the control bit is now the bit on line c.

We will explain the details of this operation with reference to FIG. The input to differential decoder 100 on line 105 is
j2, and the control bit is "c".
If the control bit "c" is equal to "0", the input j
2 is directed by a multiplexer 101 to an upper (1 + D) differential decoder 102 and to an output multiplexer 10
4 is the output of the upper (1 + D) differential decoder 102 on output line 1
Towards 06, form an estimate of i2. If the control bit "c" is equal to "1", the input j2 is directed by the multiplexer 101 to the lower (1 + D) differential decoder 103 and the output multiplexer 104 is switched to the lower (1+
D) Direct the output of the differential decoder to output line 106 to form an estimate of i2.

The outputs from encoder 74 are symbol estimates a, b, c, and d. The symbol estimates a and b are provided to logic 77, while the symbol estimates c and d are provided to logic 81.
These estimates are used by logic 77 and 81 to correct errors in the uncoded bits represented in the transmitted 3-bit value. It should be noted that in each sector value provided to logic 77 and 81, two bits are hard decision estimates of a and b transmitted bits. The remaining bits in each sector value are hard decision estimates of the uncoded bits j1 or j2. For details on this correction, see 1
Filed September 27, 991, titled "VITERBI DECODER BIT
EFFICIENT CHAINBACK MEMORY METHOD AND DECODER INCO
Further details are disclosed in co-pending U.S. application Ser. No. 07 / 695,397, assigned to the assignee of the present invention in RPORATING SAME. Controlled differential decoder 7
8 and 83. Decoders 78 and 83 receive symbol estimates a and c, respectively, as control inputs for controlling the multiplexed differential decoding of bit estimates j1 and j2.
As a result of the decoding of decoders 78 and 83, the bit estimate i
1 and i2 are formed. The foregoing description of the preferred embodiment is provided to enable any person skilled in the art to make or use the present invention. Various modifications to those embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without the use of inventive capabilities.
Thus, the present invention is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view showing an information recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is an enlarged perspective view showing a part of the apparatus shown in FIG. 1;

FIG. 3 is a block diagram of an exemplary 7/8 rate punctured trellis encoder for 8-PSK modulation.

FIG. 4 is a block diagram of an exemplary 8/9 rate punctured trellis encoder for 8-PSK modulation.

FIG. 5 is a block diagram of an exemplary 11/12 rate punctured trellis encoder for 8-PSK modulation.

FIG. 6 is a block diagram of an exemplary controlled differential encoder.

FIG. 7 is a block diagram of an exemplary 5/6 rate punctured trellis encoder for 8-PSK modulation with precoding.

FIG. 8 is a block diagram of an exemplary 5/6 rate punctured trellis decoder for 8-PSK modulation with precoding.

FIG. 9 is a block diagram of an exemplary controlled differential decoder.

[Explanation of symbols]

1: coding rate 1/2 punctured to coding rate k / k + 1
Encoder, 2, multiplexer, 3 M modulator, 50
... Controlled differential encoder, 52 ... Top differential encoder, 53
... Lower differential encoder, 61 ... 1 / (1 + D) differential decoder,
100 differential decoder, 102 upper (1 + D) differential decoder, 103 lower (1 + D) differential decoder

Claims (1)

[Claims] 1. Receiving n input data bits; encoding a k-bit subset of the n input bits according to a first encoding mode and providing as a first set of symbols; , Combining the symbols of the first set and the remaining nk input data bits to provide a transmission set, wherein each of the transmission sets includes a log ₂ M portion. Trellis coding method for transmission using 8-ary PSK modulation.