JPH1127141A - Charge pump circuit and pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a filter capacitor to reach a desired voltage in a short time at rising of the system consisting of the charge pump circuits and the PLL circuit in the system consisting of an auxiliary charge pump circuit that activates a 2nd charge pump while the current charging voltage is low to conduct high speed charging by comparing the current charging voltage with an object voltage. SOLUTION: A filter capacitor CF is not charged at all at rising of the system consisting of the charge pump circuits and the PLL circuit. A charging MOSFET Qp1 being a component of a 1st charge pump is conductive by an input of an UP signal UP and then the filter capacitor CF is gradually charged. On the other hand, an output of a differential amplifier AMP is at a low level because the charging voltage is lower at first than a reference voltage Vref to turn on a charging MOSFET Qp2 being a component of a 2nd charge pump and then hence to quickly charge the filter capacitor CF. When the charging voltage of the filter capacitor CF reaches the reference voltage Vref after that, the charging MOSFET Qp2 is turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit and a technique effective for a PLL (Phase Locked Loop) circuit using the same.

[0002]

2. Description of the Related Art In recent years, data communication LSIs have been used to reproduce a timing clock from a received signal, and have a logical L level.
In SI, PLL circuits are used for multiplication and frequency division of a clock that gives operation timing of a latch circuit and the like. The present inventor has proposed a P for generating such a clock.
Regarding the LL circuit, a study was made on realizing a faster lock-up operation.

As shown in FIG. 4, the basic configuration of a PLL circuit is to compare the phase of an input reference clock CKin with the phase of a feedback clock CKf. If the phase of the feedback clock CKf is delayed, an up signal UP is output. When the phase of CKf is advanced, a phase comparison circuit PCD that outputs a down signal DWN, a charge pump CP and a filter capacitor CF that generate a voltage corresponding to the detected phase difference, and a voltage that oscillates at a frequency corresponding to the control voltage It is a control oscillation circuit VCO.

FIG. 5 shows a configuration of a conventional general charge pump circuit. As shown in the figure, the charge pump circuit includes a MOSFET Qp connected between the power supply voltage Vcc and the output node Nc, and a MOSFET Qn connected between the output node Nc and the power supply voltage Vss. The up signal UP from the phase comparison circuit is input to the gate terminal of Qp, and the down signal DWN from the phase comparison circuit is input to the gate terminal of Qn.
Is low level, MOSFET Qp turns on,
The filter capacitor CF connected between the output node Nc and the power supply voltage Vss is charged, and when the down signal DWN is at a high level, the MOSFET Qn is turned on to discharge the filter capacitor CF. Then, the charging voltage of the filter capacitor CF is supplied to the voltage controlled oscillation circuit VCO as the oscillation control voltage Vc.

[0005]

In recent years, a PLL circuit used for a communication LSI or the like has been desired to lock up at a high speed as the system speeds up. However, in the PLL circuit using the charge pump circuit shown in FIG. 5, when the desired oscillation frequency is high, that is, when the control voltage Vc is high, particularly when the system starts up, the filter is charged from the ground level. There is a problem that it takes time to charge up CF to a desired potential. For this reason, the charge-up time of the filter capacitance by the charge pump circuit is a factor that hinders the speed-up of the lock-up of the PLL circuit.

An object of the present invention is to provide a charge pump circuit which can reach a desired voltage in a short time when the system starts up.

Another object of the present invention is to charge up a filter capacitance in a short time at the time of system startup and to increase the PL.
It is an object of the present invention to provide a charge pump circuit that can speed up lock-up of an L circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, in addition to the charge pump circuit for charging / discharging the filter capacitance in response to the up signal and the down signal, the current charge voltage is compared with the target voltage, and the second charge voltage is used as long as the current charge voltage is low. An auxiliary charge pump circuit for operating a charge pump to perform high-speed charging is provided.

According to the above means, the filter capacitance is charged up in a short time when the system is started up, reaches a desired output voltage, and the lock-up speed of the PLL circuit can be increased.

Preferably, after the current charging voltage reaches the target voltage, the operation of the second charge pump is stopped. As a result, once the target voltage is reached, the output voltage is generated only by the original charge pump circuit, thereby preventing the output voltage from undesirably fluctuating.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a charge pump circuit according to the present invention. Each element of the circuit is formed on one semiconductor chip such as single crystal silicon. However, the capacitance may be configured as an external element.

As shown in FIG. 1, the charge pump circuit according to this embodiment includes a power supply voltage Vcc and an output node N.
c, and a MOSFET Qp1 connected between the output node Nc and the power supply voltage Vss.
ET Qn1 and an up signal UP from a preceding circuit (for example, a phase comparison circuit) is connected to the gate terminal of Qp1.
When the down signal DWN from the phase comparison circuit is input to the gate terminal of Qn1 and the up signal UP is at a low level, the filter capacitor CF connected between the output node Nc and the power supply voltage Vss is charged. Down signal DWN
Is at a high level, the power supply voltage V1 in addition to the first charge pump CP1 for discharging the filter capacitance CF.
MOSFET connected between cc and output node Nc
A second charge pump CP2 including Qp2 is provided.

Further, the charge pump circuit of this embodiment has a reference voltage V set to a value close to a target voltage.
differential amplifier AMP for comparing ref with current charging voltage
Is provided, and the output of the differential amplifier AMP is connected to the charging MOSFE constituting the second charge pump CP2.
It is applied to the gate terminal of T Qp2. The reference voltage Vref is supplied from a not-shown constant voltage generating circuit formed on the same semiconductor chip.

Next, the operation of the charge pump circuit of the embodiment shown in FIG. 1 will be described.

At the start of the system, the filter capacitance C
Since F is not charged at all, the up signal UP is inputted and the charging MO constituting the first charge pump is charged.
The SFET Qp1 is turned on, and the filter capacitance CF is gradually charged. On the other hand, the output of the differential amplifier AMP is initially low because the charging voltage is lower than the reference voltage Vref, whereby the charging MOSFET Qp2 constituting the second charge pump is turned on, and the filter capacitance CF is rapidly charged. Is done. Thereafter, when the charging voltage of the filter capacitor CF reaches the reference voltage Vref, the output of the differential amplifier AMP changes to a high level, so that the charging MOSFET Qp2 is turned off, and thereafter, the charging and discharging of the capacitor by the first charge pump is performed. Then, the charging voltage of the filter capacitor CF is set to the target voltage.

In the embodiment shown in FIG. 1, in order to prevent the charging voltage from overshooting due to overcharging of the filter capacitor CF by the charging MOSFET Qp2 constituting the second charge pump, the reference voltage Vref is set lower than the target voltage. It is also desirable to set a little lower.

FIG. 2 shows a second embodiment of the charge pump circuit according to the present invention. The charge pump circuit according to this embodiment includes a second charge pump CP2,
In addition to the charging MOSFET Qp2 connected between the power supply voltage Vcc and the output node Nc, the output node Nc
And a power supply voltage Vss. The output of the inverter INV that inverts the output of the differential amplifier AMP is applied to the gate of the discharge MOSFET Qn2, and is turned on and off simultaneously with the charging MOSFET Qp2 that forms the second charge pump. Is configured.

The charge pump circuit of this embodiment comprises a charge MOSFET Qp2 and a discharge MOSFET Qp2.
Since the FET Qn2 is turned on at the same time, the filter capacitor CF is rapidly charged when the charging voltage is far from the reference voltage Vref, such as immediately after system startup,
When the charging voltage approaches the reference voltage Vref, the charging power decreases and acts to gradually approach the reference voltage. Therefore,
This embodiment is characterized in that even if the reference voltage is the same as the target voltage, a voltage change due to overshoot can be prevented. In addition, there is an advantage that it is hardly affected by process variations.

FIG. 3 shows a third embodiment of the charge pump circuit according to the present invention. The charge pump circuit of this embodiment has a high-level holding circuit composed of an OR gate G1 having an output terminal and one input terminal connected between a second charge pump CP2 and a differential amplifier AMP for driving and controlling the second charge pump CP2. A circuit is provided. Further, a pull-down resistor R1 is connected to an output terminal of the OR gate G1.

In the charge pump circuit of this embodiment, when the charging voltage at the time of system startup is lower than the reference voltage Vref, the outputs of the differential amplifier AMP and the OR gate G1 are at low level to constitute the second charge pump. The MOSFETs Qp2 and Qn2 are turned on to rapidly charge the filter capacitance CF, and the charging voltage becomes equal to the reference voltage Vref.
, The output of the differential amplifier AMP changes to the high level, the OR gate G1 holds the high level, the charging voltage becomes lower than the reference voltage Vref, and the output of the differential amplifier AMP changes to the low level again. Even if it changes, the output of the OR gate G1 maintains the high level. Therefore, in the charge pump circuit of this embodiment, the second charge pump operates at the time of system startup to perform high-speed charging.
Once the charging voltage reaches the reference voltage, the second charge pump operates to stop operating thereafter.

In the embodiment shown in FIGS. 1 and 2, once the charging voltage reaches the reference voltage Vref, when the charging voltage becomes lower than the reference voltage Vref, the output of the differential amplifier AMP changes to low level again and the second Since the charging is performed by the charge pump, the charging voltage may not easily converge to a constant value. However, in the charge pump circuit of the third embodiment, once the charge voltage reaches the reference voltage, the second charge pump stops operating thereafter.
There is an advantage that the charging voltage easily converges to a constant value.

In this embodiment, the differential amplifier AMP
Since the pull-down resistor R1 is connected to the output terminal of the OR gate G1 for maintaining the output high level, the output of the OR gate G1 is fixed to the low level by the pull-down resistor R1 during the initial operation. The pump CP2 can be reliably operated. Note that, also in the embodiment of FIG. 3, it is possible to omit the discharge MOSFET Qn2 as in the embodiment of FIG.

As described above, in the above embodiment, in addition to the charge pump circuit for charging / discharging the filter capacitance by the up signal and the down signal, the present charging voltage is compared with the target voltage to compare the current charging voltage with the target voltage. Second while the voltage is low
An auxiliary charge pump circuit for performing high-speed charging by operating the charge pump is provided, so that the filter capacitance is charged up in a short time at the start of the system to reach a desired output voltage, and the PLL circuit is locked. There is an effect that the speed-up can be achieved.

After the current charge voltage reaches the target voltage, the operation of the second charge pump is stopped. Therefore, once the target voltage is reached,
Since the output voltage is generated only by the original charge pump circuit, it is possible to prevent an undesired change in the output voltage.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment. For example, in the embodiment, the charging voltage of the filter capacitor exceeds the reference voltage. Although the OR gate is used as the output maintaining means for maintaining the output of the differential amplifier as the voltage comparing means for detecting whether or not the voltage has been detected, the present invention is not limited to this, and may be configured by a flip-flop or the like. In the embodiment, the filter capacitance is directly connected to the charge pump circuit. However, a low-pass filter may be configured by connecting a capacitance via a resistor.

In the above description, the invention mainly made by the inventor has been described in the field of application of PLL which is the background of the application.
The case where the present invention is applied to a charge pump circuit constituting a circuit has been described. However, the present invention is not limited to this, and can be widely used for a semiconductor integrated circuit having a built-in charge pump circuit.

[0030]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to realize a charge pump circuit which can charge up the filter capacitance in a short time at the time of starting the system, and a PLL circuit which locks up at a high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a charge pump circuit according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the charge pump circuit.

FIG. 3 is a block diagram showing a third embodiment of the charge pump circuit.

FIG. 4 is a block diagram illustrating a basic configuration of a PLL circuit as an application example of a circuit using a charge pump circuit.

FIG. 5 is a circuit diagram showing a configuration example of a conventional charge pump circuit.

[Explanation of symbols]

 CP1 First charge pump CP2 Second charge pump AMP Voltage comparing means (differential amplifier) G1 Output maintaining means (OR gate) PCD Phase comparing circuit CP Charge pump circuit CF Filter capacity VCO Voltage controlled oscillator circuit CKin Input clock CKf Feedback clock

Claims (6)

[Claims] A first switch means connected between a first power supply voltage terminal and an output node; and a second switch means connected between the output node and a second power supply voltage terminal. A third switching means connected between the first power supply voltage terminal and the output node; a capacitive element connected between the output node and the first or second power supply voltage terminal; Voltage comparison means for comparing the charge voltage of the capacitive element with a reference voltage, and while the charge voltage is lower than the reference voltage, the output of the voltage comparison means turns on the third switch means to turn on the third switch means. A charge pump circuit configured to charge a capacitance element. 2. A fourth switch means is connected between the output node and the second power supply voltage terminal. While the charging voltage is lower than the reference voltage, the fourth switching means is connected to the output of the voltage comparing means. The charge pump circuit according to claim 1, wherein the third switch means and the fourth switch means are turned on to charge the capacitance element. 3. An output maintaining means for maintaining an output of the voltage comparing means when a charging voltage of the capacitive element exceeds the reference voltage is provided at an output terminal of the voltage comparing means,
3. The charge pump circuit according to claim 1, wherein the third switch means or the third and fourth switch means are controlled by the output maintaining means. 4. A phase comparison circuit for detecting a phase difference between an input reference clock and a feedback clock; first switch means connected between a first power supply voltage terminal and an output node; A second switch connected between the first power supply voltage terminal and the output node; a third switch connected between the first power supply voltage terminal and the output node; And a voltage comparison means for comparing a charging voltage of the capacitance element with a reference voltage, wherein the charging voltage is lower than the reference voltage. A charge pump circuit configured to turn on the third switch means by an output of the voltage comparison means to charge the capacitance element, and to generate a voltage corresponding to a phase difference detected by the phase comparison circuit; Char A voltage-controlled oscillation circuit that oscillates at a frequency corresponding to the charging voltage of the pump circuit, wherein a clock output from the voltage-controlled oscillation circuit or a clock obtained by dividing the clock is supplied to the phase comparison circuit as the feedback clock A PLL circuit having a configuration as described above. 5. A fourth switch means is connected between the output node and the second power supply voltage terminal. While the charging voltage is lower than the reference voltage, the fourth switching means is connected to the output of the voltage comparing means. 5. The PLL according to claim 4, wherein the third switch means and the fourth switch means are turned on to charge the capacitance element.
circuit. 6. An output maintaining means for maintaining an output of the voltage comparing means when a charging voltage of the capacitive element exceeds the reference voltage is provided at an output terminal of the voltage comparing means,
6. The PLL circuit according to claim 4, wherein said output maintaining means controls said third switch means or said third and fourth switch means.