JPH11265587A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To confirm a writing state in a short time when multi-level data is written. SOLUTION: A current limiting circuit 10 is connected to a bit line 3 to which a memory cell transistor 1 is connected in parallel with the memory cell transistor 1. Current capacity of the current limiting circuit 10 is changed in accordance with contents of writing data, when the sum of a read-out current ir1 flowing to the memory cell transistor 1 from the bit line 3 and a read-out current ir2 flowing to the current limiting circuit 10 from the bit line 3 is converged to the prescribed value, writing operation is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device capable of storing multi-value data by a memory cell transistor having a floating gate.

[0002]

2. Description of the Related Art Electrically erasable programmable RO
M (EEPROM: Electrically Erasable Programmable ROM)
In, a memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. In the case of such a memory cell transistor having a double gate structure, data is written by accelerating hot electrons generated on the drain region side of the floating gate to the source side and injecting a part of the accelerated electrons into the floating gate. Done. Then, data is read by detecting a difference in operation characteristics of the memory cell transistor depending on whether or not charge is injected into the floating gate, that is, by detecting a change in threshold.

FIG. 6 is a circuit diagram showing a configuration of a semiconductor memory device having a memory cell transistor having a double gate structure, and FIG. 7 is a timing chart for explaining its operation. This figure shows a case where memory cells are arranged in 4 rows × 1 column, and a column selection circuit is omitted. The memory cell transistor 1 has an electrically independent floating gate and a control gate partially overlapping the floating gate. The memory cell transistor 1 is turned on / off in response to a potential applied to the control gate, and changes its threshold value according to the amount of charge stored in the floating gate.
Word line 2 is arranged corresponding to each row of memory cell transistors 1 and connected to the control gate of each memory cell transistor 1. The bit lines 3 are arranged corresponding to the columns of the memory cell transistors 1, the drains of the memory cell transistors 1 are connected in common, and the bit lines 3 are connected to a comparison circuit 8 described later. Source line 4
Are arranged between the memory cell transistors 1, and the sources of the memory cell transistors 1 are commonly connected.

A row selection circuit 5 is connected to each word line 2 and has a row selection signal L generated based on row address information.
S1 to LS4 are supplied to each word line 2. The row selection signals LS1 to LS4 are for selectively activating any one of the four word lines 2 in response to the selection clock φc, and the memory connected to the activated word line 2 The control gate of the cell transistor 1 is turned on.
When a plurality of columns of the memory cell transistors 1 are arranged, a desired column is selected based on column address information. Thereby, one of the plurality of memory cell transistors 1 is designated according to the row address information (and the column address information), and is connected to the comparison circuit 8.

The read control circuit 6 is connected to the bit line 3 and has a read clock φr synchronized with the selected clock φc.
, The potential Vrd for the read operation is applied to the bit line 3.
To precharge. The read control circuit 6
After the precharge of the bit line 3 is completed, the supply of the potential Vrd is cut off. However, until the memory cell transistor 1 is selected, the bit line 3 is in an electrically floating state, so that the potential Vrd is held. You. The write control circuit 7 is connected to the source line 4 and supplies a potential Vws for a write operation in response to a write clock φw synchronized with the selected clock φc. The write control circuit 7 supplies the ground potential Vg except during the period in which the write potential Vws is supplied to the source line 4. And
During a period in which the write potential Vws is supplied from the write control circuit 7, the read control circuit 6
Is supplied with a ground potential Vg.

In the read operation, the comparison circuit 8 compares the potential VBL of the bit line 3 with a predetermined reference potential Vref, and generates a comparison output C which rises when the potential VBL of the bit line 3 drops to the reference potential Vref. I do. The time determination circuit 9 measures the time from the rise of the read clock φr to the rise of the comparison output C, detects a match between the measurement result and time information set according to the write data, and detects a write stop signal E. Is output.

When writing multi-level data to the memory cell transistor 1, in order to improve the writing accuracy,
The charge injection (write) and the check of the injection amount (read) are repeated in a short cycle. That is, reading is performed each time while writing to the memory cell transistor 1 is performed little by little, and the writing is stopped when the read result matches the content of the data to be stored. For example, as shown in FIG. 7, the rising period of the write clock φw in synchronization with the selection clock φc is the writing period W, and the rising period of the read clock φr in synchronization with the selection clock φc is the reading period R.

In writing data, the bit line 3 applies the ground potential Vg to the memory cell transistor 1.
(For example, 0 V), and a writing potential Vws (for example, 14 V) is applied from the source line 4. As a result, in the specific memory cell transistor 1 in which the control gate is selectively turned on, the write current ip flows from the source region to the drain region, and charge is injected into the floating gate. On the other hand, in reading the written data, the bit line 3 is set at the read potential Vrd.
After being precharged (for example, 5V), the source line 4 is connected to the ground potential Vg (for example, 0V). When a control gate of a specific memory cell transistor 1 is selectively turned on, the memory cell transistor 1
The read current ir flows from the drain region to the source region. At this time, since the threshold value of the memory cell transistor 1 changes according to the written data (the amount of charge stored in the floating gate),
The change in the threshold appears as a difference in the rate of fall of the potential VBL of the bit line 3. That is, the memory cell transistor 1
Is low and the on-resistance value at the time of selection is small, the potential VBL of the bit line 3 drops rapidly,
Conversely, when the threshold value is high and the on-resistance value at the time of selection is high, the drop of the potential VBL of the bit line 3 becomes slow. Therefore, the comparator 8 detects that the potential VBL of the bit line 3 has dropped to the predetermined potential Vref, and measures the time from the start of the read operation to the detection timing of the comparator 8 by the time determination circuit 9. doing.

For example, one memory cell transistor 1
When four values are stored, the threshold values of the memory cell transistor 1 are set to four types. Then, the potential VBL of the bit line 3 read corresponding to the four types of thresholds is read.
Are four types as shown in FIG. That is, when no writing is performed on the memory cell transistor 1, the potential VBL of the bit line 3 rapidly drops from the read operation start timing t0 as shown by the curve a, and is the fastest. At the timing t1, the potential becomes the predetermined reference potential Vref. When data of "1/3" or "2/3" is written to the memory cell transistor 1, the potential VBL of the bit line 3 becomes the curve a as shown by the curve b or c. Timing t2 or t3 which is slower than
Attains a predetermined reference potential Vref. If the memory cell transistor 1 has been completely written and does not turn on even when selected, the bit line 3
Maintain the precharged potential Vrd.
Therefore, the time from when the potential VBL of the bit line 3 starts to be the read operation to when the potential VBL reaches the reference potential Vref is measured, and when the time coincides with the time from the timing t0 to the timing t1 to t3, the writing is performed. The operation is stopped.

[0010]

The potential VBL of the bit line 3
When confirming (reading) the write data by measuring the descent time, the time required for the read operation is determined by the condition that the descent speed is the slowest. When writing quaternary data as shown in FIG. 8, reading of the write data requires at least the time from timing t0 to timing t3. Such a delay in the read operation increases the time required for the operation of writing multi-value data in which the write operation and the read operation are repeated. In particular, in the case where the current capacity is reduced due to the miniaturization of the memory cell transistor 1 or when the memory cell transistor 1 is driven at a low voltage, the current flowing in the read operation is reduced, and the time required for the write operation is further increased.

SUMMARY OF THE INVENTION It is an object of the present invention to shorten the time required for checking write data and to complete writing of multi-value data in a short time.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a feature in that the present invention has an electrically independent floating gate, and stores the floating gate in the floating gate. A memory cell transistor that changes an on-resistance value in accordance with the amount of charge to be supplied, a write control circuit that supplies a write current from the source side to the memory cell transistor to inject charge into a floating gate, A read control circuit that supplies a read current from the drain side, and a current limiting circuit that is connected to the read control circuit in parallel with the memory cell transistor and changes a current capacity according to the content of write data. The current flowing from the read control circuit to the memory cell transistor and the current Until the sum of the current flowing to the limiting circuit reaches a predetermined amount, in alternately repeating the supply of the read current from the supply and the readout control circuit of the write current from the write circuit.

According to the present invention, when the on-resistance value of the memory cell transistor is large, the current capacity of the current limiting circuit increases, and the amount of current flowing from the write control circuit to the current limiting circuit increases. Then, the sum of the currents flowing out of the write control circuit finally converges to a substantially constant amount regardless of the on-resistance value of the memory cell transistor. Therefore, even when the on-resistance value of the memory cell transistor is large, the time required for the read operation does not increase.

[0014]

FIG. 1 is a circuit diagram showing a first embodiment of the nonvolatile semiconductor memory device of the present invention. In this figure, memory cell transistor 1, word line 2,
The bit line 3 and the source line 4 have the same configuration as in FIG. 6, and the row decoder 5, the read control circuit 6, the write control circuit 7, and the comparison circuit 8 connected thereto have the same configuration as in FIG. is there.

The feature of the present invention is that the bit line 3
Is connected to the current limiting circuit 10 so that a read current flows from the bit line 3 to the source line 4 through the memory cell transistor 1 and a read current also flows from the bit line 3 to the current limiting circuit 10. At this time, the current capacity of the current limiting circuit 10 is changed according to the content of data to be written to the memory cell transistor 1. As a result, the sum of the read currents at the time of completion of the writing becomes constant irrespective of the contents of the write data, so that the reading operation is completed in a short time.

The current limiting circuit 10 includes a transistor 11 as a current control element and an on / off state of the transistor 11.
It is constituted by a decoder 12 for controlling turning off. Transistors 11 each have a constant current capacity, and are connected in parallel between bit line 3 and a ground point by a number corresponding to the number of steps of multivalued data to be written to memory cell transistor 1. In the present embodiment, two transistors 11 are connected in parallel so that the current capacity can be changed in three stages corresponding to the case where four values are stored. Decoder 1
2 turns on the transistors 11 by the number corresponding to the contents of the write data in response to the rise of the selection clock φc. For example, 4 of “0”, “1/3”, “2/3”, “1”
Of the values, when storing “１ ／”, only one transistor 11 is turned on, and when storing “2/3”, both transistors 11 are turned on. As a result, the variation characteristic of the potential VBL of the bit line 3 when a read current is applied to the memory cell transistor 1 in which “1/3” is stored, as shown in FIG.
To curve a. Similarly, the variation characteristic of the potential VBL of the bit line 3 when a read current flows through the memory cell transistor 1 in which “2/3” is stored changes from the curve c to the curve a. When "1" is stored in the memory cell transistor 1, the memory cell transistor 1
Therefore, it is not necessary to operate the current control circuit 10 to check the write data because sufficient writing is performed so that no read current flows.

The time judging circuit 9 'has a read clock φr
The rise time of the comparison result C of the comparison circuit 8 is measured, and the measured result is compared with a predetermined reference value, so that the write stop signal E rises when the measurement result exceeds the reference value. . The threshold value of the memory cell transistor 1 is increased each time writing is repeated, and the on-resistance in the read operation is increased. Therefore, in the read operation, the drop in the potential VBL of the bit line 3 is gradually reduced. At the initial stage of the write operation, the potential VBL of the bit line 3 drops faster by the write current flowing from the bit line 3 to the current limiting circuit 10,
The writing operation is repeated until the descent speed reaches a predetermined descent speed. Therefore, the time required to read the write data is the longest at the time when the write is completed. In the time determination circuit 9 shown in FIG. 6, the reference value for the determination is variably set in association with the write data. However, in the time determination circuit 9 ', it is fixed.
For example, in FIG. 2, the value corresponding to the time from timing t0 to timing t1 is set as a reference value, and in all cases, the writing operation is stopped when the drop in the potential VBL of the bit line 3 matches the curve a. It is configured to

FIG. 3 is a block diagram showing an example of the time determination circuit 9 '. The time determination circuit 9 'includes a counter 9a,
It comprises a latch 9b and a comparator 9c. The counter 9a is reset at the timing of the rising edge of the read clock φr, counts the clock CK having a cycle sufficiently shorter than the selected clock φc, and outputs a count value that increases at a constant cycle. The latch 9b captures and holds the count value of the counter 9a at the timing of the rise of the determination result C of the comparison circuit 8. Then, the comparator 9c compares the count value held in the latch 9b with a predetermined reference value, and generates a write stop signal E which rises when the count value exceeds the reference value.

In the case of FIG. 2, a reference value is set in the curve a in accordance with the time from the read start timing t0 to the timing t1 at which the potential VBL of the bit line 3 becomes the reference potential Vref and the cycle of the clock CK. You. That is, the number at which the counter 9a is counted up by the clock CK from the timing t0 to the timing t1 shown in FIG. 2 is set as a reference value. The count value held in the latch 9b is such that the potential VBL of the bit line 3 is actually the reference potential VBL.
This corresponds to the time required to fall to ref, and is smaller than the reference value when the writing operation is started. When the write operation is repeated, the time required for the potential VBL of the bit line 3 to drop to the reference potential Vref becomes longer, so that the count value held in the latch 9b increases. Then, when the count value held in the latch 9b exceeds the reference value, that is, the time required for the potential VBL of the bit line 3 to drop to the reference potential Vref is shorter than the time between the timings t0 and t1 in FIG. Becomes longer, the write stop signal E rises. As a result, charges corresponding to desired write data are injected into the floating gate of each memory cell transistor 1.

FIG. 4 is a block diagram showing a second embodiment of the present invention. In this embodiment, the configuration other than the current limiting circuit 20 is the same as that of FIG. Current limiting circuit 2
0 is constituted by one transistor 21 as a current control element and a variable potential source 22 for supplying a variable potential to its gate. The transistor 21 is connected between the bit line 3 and the ground point, and changes its on-resistance in response to a potential applied to the gate, specifically, a potential difference applied between the gate and the source. The variable potential source 22 takes in the write data and applies a potential according to the content to the gate of the transistor 21. Thereby, the current capacity of the transistor 21 is variably set according to the content of the write data, and the same operation as the current limiting circuit 10 of FIG. 1 can be realized.

FIG. 5 is a block diagram showing a third embodiment of the present invention. In the present embodiment, the reference potential Vref is obtained by using the dummy cell transistor 13 arranged in parallel with the memory cell transistor 1. The dummy cell transistor 13 has the same structure as the memory cell transistor 1 and is arranged in parallel with each memory cell transistor 1 in an erased state. These dummy cell transistors 13 have their control gates connected to the common word line 2 with the memory cell transistors 1 and are selected simultaneously with the memory cell transistors 1 in the same row. The dummy bit line 14 is arranged along the arrangement of the dummy cell transistors 13. The dummy bit line 14 is connected to the drain of the dummy cell transistor 13 and to the inverting input of the comparison circuit 8. The potential of the dummy bit line 14 becomes the reference potential Vref.

The read control circuit 6 'is connected to the bit line 3 and the dummy bit line 14, and supplies a read potential Vrd to the bit line 3 and the dummy bit line 14 to precharge the same. The comparison circuit 8 is the same as the comparison circuit 8 of FIG. 1, and compares the potential VBL of the bit line 3 with the reference potential Vref which is the potential of the dummy bit line 14. The determination circuit 15 captures the comparison result C of the comparison circuit 8 at the rising timing of the delayed read clock φdr having a certain phase difference with respect to the read clock φr, and the potential VBL of the bit line 3 becomes higher than the reference potential Vref. The write stop signal E rises. The reference potential Vref obtained from the dummy bit line 14 drops to the ground potential Vg due to the read current flowing through the dummy cell transistor 13 in the erased state. The falling speed coincides with the falling speed when the read current is applied to the memory cell transistor 1 to which the writing is not performed in a state where the read current is not applied to the current limiting circuit 10, that is, the curve a shown in FIG. . Therefore, in order to compare the drop of the potential VBL of the bit line 3 with the drop of the reference potential Vref, the judgment result C of the comparator 8 is taken in after a predetermined period has elapsed from the rise of the read clock φr. Third
If the configuration is such that the reference potential Vref is taken out using the dummy cell transistor 13 as in the first embodiment, the influence of the fluctuation of the power supply potential and the temperature change becomes less likely, and a stable determination operation can be realized.

In the above embodiment, the case where the memory cell transistors 1 are arranged in 4 rows × 1 column is exemplified. However, it is easy to arrange the memory cell transistors 1 in 5 rows or more or a plurality of columns. In this case, a selection circuit for column selection is provided between the plurality of bit lines and the differential amplifier that determines the potential VBL of the bit line. The multivalued data stored in the memory cell transistor 1 is not limited to four values, but may be eight values (for three bits), sixteen values (for four bits) or more. In that case,
The current limiting circuits 10 and 20 may be configured to change the current capacity at a stage corresponding to the number of steps of the stored data.

[0024]

According to the present invention, when multi-value data is stored in a memory cell by repeating a write operation and a read operation, the time required for the read operation can be reduced, and as a result, the write time is reduced. can do.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a characteristic diagram showing how a potential of a bit line drops during a read operation.

FIG. 3 is a block diagram illustrating an example of a configuration of a time determination circuit.

FIG. 4 is a circuit diagram showing a second embodiment of the nonvolatile semiconductor memory device of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the nonvolatile semiconductor memory device of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a conventional nonvolatile semiconductor memory device.

FIG. 7 is a timing chart illustrating an operation of a conventional nonvolatile semiconductor memory device.

FIG. 8 is a characteristic diagram showing a state of a potential drop of a bit line during a read operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell transistor 2 Word line 3 Bit line 4 Source line 5 Row decoder 6, 6 'Read control circuit 7 Write control circuit 8 Comparison circuit 9, 9' Time judgment circuit 10, 20 Current limiting circuit 11, 21 Transistor (current control Element) 12 decoder 13 dummy cell transistor 14 dummy bit line 15 judgment circuit

Claims (4)

[Claims] 1. A memory cell transistor having an electrically independent floating gate and changing an on-resistance value according to the amount of electric charge stored in the floating gate, and a write current from a source side to the memory cell transistor. A write control circuit for supplying a charge to the floating gate by supplying a charge to the floating gate; a read control circuit for supplying a read current from the drain side to the memory cell transistor; and a read control circuit connected in parallel with the memory cell transistor. A current limiting circuit for changing a current capacity according to the content of write data, wherein the sum of the current flowing from the read control circuit to the memory cell transistor and the current flowing to the current limiting circuit reaches a predetermined amount Until the write current is supplied from the write circuit And a supply of a read current from the read control circuit is alternately repeated. 2. The current limiting circuit has a constant current capacity, and includes a plurality of current control transistors each connected in parallel to the read control circuit, wherein the plurality of current control transistors are configured to store the contents of the write data. 2. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is selectively turned on in response to the following. 3. The current limiting circuit includes a current control transistor connected to the read control circuit, the current control transistor changing a current capacity in accordance with a potential difference applied between a gate and a source, the current control circuit being adapted to the content of the write data. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a potential difference is applied between a gate and a source of said current control transistor. 4. A dummy cell transistor having the same structure as the memory cell transistor and connected in parallel with the memory cell transistor, and a read current flowing from the read control circuit to the memory cell transistor and the current limiting circuit. And a comparison circuit for comparing the potential change occurring on the drain side of the memory cell transistor when the read current flows from the read control circuit to the dummy cell transistor with the potential change occurring on the drain side of the dummy cell transistor. 2. The apparatus according to claim 1, further comprising: stopping a supply of a write current from the write circuit and a supply of a read current from the read control circuit in response to a comparison result of the comparison circuit. Non-volatile semiconductor memory device.