JPH11265575A - Semiconductor device and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To satisfy both of power consumption reduction by lowering an external power supply voltage in a standby state and data retention in the standby state. SOLUTION: When a data retention mode is not set in this semiconductor device, the driving level of word drivers 213A and 213B is formed by a first boosting means 232. When the data retention mode is set, the driving level of the word drivers is formed by using both of the first boosting means and a second boosting means 233 for boosting the output. Thus, both of the power consumption reduction by lowering the external power supply voltage VDD in the standby state and the data retention of the semiconductor device in the standby state are satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which is brought into a low power consumption state by lowering a power supply voltage, and more particularly to a semiconductor device which must retain data in a dynamic memory cell in a low power consumption state. For example, the present invention relates to a dynamic memory and a memory which is effectively applied to a data processing system having the memory.

[0002]

2. Description of the Related Art When a low power consumption state such as a standby state is set, the power consumption of individual semiconductor devices can be reduced by lowering the external power supply voltage of the system. For example, in a data processing system having a DRAM (Dynamic Random Access Memory), the power supply voltage in the standby state must be reduced within a range that does not hinder the refresh operation of the DRAM. That is, if the power supply voltage is lowered so that the word line selection level is too low, the word line selection operation for refreshing becomes insufficient, and the information stored in the memory cell cannot be refreshed. As an example of a document describing a DRAM, there is a CMOS Device Handbook, pages 379 to 382, published by Nikkan Kogyo Shimbun on September 29, 1987.

[0003]

SUMMARY OF THE INVENTION The present inventor has studied to further reduce the power supply voltage in order to enhance the low power consumption in the standby state. However, in this case, as described above, there is a natural limit to the reduction of the power supply voltage at the time of low power consumption in consideration of data retention. When the voltage is reduced below the limit, it is necessary to increase the external power supply voltage so as to guarantee data retention.

An object of the present invention is to provide a semiconductor device and a data processing system capable of satisfying both low power consumption by lowering an external power supply voltage in a standby state and data retention in a standby state. Is to do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the semiconductor device comprises a first boosting means (232) for boosting an external power supply voltage and a second boosting means (232) capable of further boosting the boosted voltage formed by the first boosting means. 233), an output voltage selecting means (234) for selecting the output of the second boosting means instead of the output of the first boosting means when the second boosting means performs the boosting operation, and the output voltage selecting means. Drivers (213A, 213B) that use the selected boosted voltage as a drive level, a circuit driven by the driver, and an output voltage of the second booster based on control information given from the outside. And a controller 212 for selecting

When attention is paid to retention of data stored in a dynamic memory cell, a DRAM or S
A semiconductor device such as a DRAM includes a first booster that boosts an external power supply voltage, a second booster that can further boost a boosted voltage formed by the first booster, and a second booster that boosts the boosted voltage formed by the first booster. Output voltage selecting means for selecting the output of the second boosting means instead of the output of the first boosting means when performing the boosting operation of the boosting means; and the boosted voltage selected by the output voltage selecting means as a word line selection level. A memory cell array having a word driver to be used, a dynamic memory cell having a word line driven by the word driver, a selection terminal connected to the word line, and a data input / output terminal connected to a bit line, and the memory cell array A row address selecting means for selecting a word line from the memory cell array; a column address selecting means for selecting a bit line from the memory cell array; An external input / output circuit for electrically connecting the bit line selected by the selection means to the outside; a second booster for the output voltage selection means when the data retention mode is designated and an internal operation mode is determined according to control information given from the outside; A controller for selecting the output voltage of the means.

According to the above means, when the data retention mode is not set, the driving level of the word driver is formed by the first boosting means. When the data retention mode is set, the drive level of the word driver is set to the first booster and the second booster for boosting its output.
It is formed using both of the step-up means. Therefore,
It is possible to satisfy both the reduction in power consumption by lowering the external power supply voltage in the standby state and the data retention in the standby state. Here, the data retention mode refers to an operation mode in which data is exclusively used in a dynamic memory, and is one of low power consumption states (power down state).

[0010] The semiconductor device is replaced with a first semiconductor device (1).
The data processing system mounted as (0) controls the first semiconductor device and instructs the first semiconductor device to perform the data retention mode when the standby mode is instructed. When,
A power supply circuit (30) for generating a power supply voltage for the first and second semiconductor devices and lowering the power supply voltage by instructing a standby mode is included in the mounting substrate. This makes it possible to reduce the power consumption of the entire data processing system without impeding the data retention (data retention) of the first semiconductor device.

[0011]

FIG. 1 is a block diagram showing an SDRAM as an example of a semiconductor device according to the present invention. Although not particularly limited, the SDRAM 1 shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. This SDRAM 1
Includes a memory array 200A forming the bank A and a memory array 200B forming the bank B. Each of the memory arrays 200A and 200B includes dynamic memory cells MC arranged in a matrix. According to the drawing, the selection terminals of the memory cells MC arranged in the same column are coupled to the word line WL for each column. The data input / output terminals of the memory cells arranged in the same row have complementary data lines BL,
It is bound to BLb. Although only a part of the word lines and the complementary data lines are representatively shown in FIG. 1, a large number are actually arranged in a matrix.

The word line WL of the memory array 200A
One selected according to the decoding result of the row address signal by the row decoder 201A is the word driver 213.
Driven to the selected level by A. Word driver 2
The word line selection level by 13A is a boosted voltage VPP boosted and generated by the word line level generation circuit 231. Details of the word line level generation circuit 231 will be described later.

[0013] Complementary data lines of memory array 200A are coupled to sense amplifier and column select circuit 202A.
The sense amplifier in the sense amplifier and column selection circuit 202A is an amplification circuit that detects and amplifies a small potential difference appearing on each complementary data line by reading data from the memory cell MC. The column switch circuit in this case is a switch circuit for selecting complementary data lines individually and conducting to the complementary common data line 204. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder 203A. Similarly, the row decoder 201 is provided on the memory array 200B side.
B, a word driver 213B, a sense amplifier and column selection circuit 202B, and a column decoder 203B. The complementary common data line 204 is connected to the output terminal of the data input buffer 210 and the data output buffer 2.
11 input terminals. Data input buffer 21
0 input terminal and the output terminal of the data output buffer 211 are 16-bit data input / output terminals I / O0 to I / O15.
Connected to.

The row address signal and the column address signal supplied from the address input terminals A0 to A9 are taken into the column address buffer 205 and the row address buffer 206 in an address multiplex format. The supplied address signal is held in each buffer. In the refresh operation mode, the row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal. The output of the column address buffer 205 is supplied as preset data of a column address counter 207. The column address counter 207 outputs a column address signal as the preset data or the column address thereof according to an operation mode specified by a command described later. The value obtained by sequentially incrementing the signal is applied to the column decoder 203A,
Output to 203B.

The controller 212 includes, but is not limited to, a clock signal CLK and a clock enable signal CK.
E, chip select signal CSb (suffix b means that the signal attached thereto is a row enable signal or a level inversion signal), column address strobe signal CASb, row address strobe signal RAS
b, an external control signal such as a write enable signal WEb, and control data from the address input terminals A0 to A9. The operation mode of the SDRAM and the circuit block It forms an internal timing signal for controlling the operation, and includes control logic (not shown) and a mode register 220 therefor.

The clock signal CLK is a master clock of the SDRAM, and other external input signals are made significant in synchronization with the rising edge of the clock signal CLK.

The chip select signal CSb indicates the start of a command input cycle by its low level. When the chip select signal is at a high level (chip unselected state), other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state.

The RASb, CASb, and WEb signals have different functions from corresponding signals in a normal DRAM, and are significant signals when defining a command cycle described later.

The clock enable signal CKE is a signal for instructing the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid. In a power down mode (which is also a data retention mode in SDRAM), the clock enable signal CKE is at a low level.

Further, although not shown, an external control signal for controlling output enable for the data output buffer 211 in the read mode is also supplied to the controller 21.
2, when the signal is at a high level, for example, the data output buffer 211 is brought into a high output impedance state.

The row address signal is a clock signal C
It is defined by the levels of A0 to A8 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of LK.

The input from A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is at a low level, the memory bank BANKA is selected, and when the input of A9 is at a high level, the memory bank BANKB is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the unselected memory bank are not selected, the data input buffer 210 and the data of only the selected memory bank are selected. This can be performed by processing such as connection to the output buffer 211.

The input of A8 in a precharge command cycle described later indicates a mode of a precharge operation for a complementary data line or the like, and its high level indicates that both memory banks are to be precharged, The level indicates that one of the memory banks indicated by A9 is to be precharged.

The column address signal is A0 in a read or write command (column address read command, column address write command described later) cycle synchronized with the rising edge of the clock signal CLK.
ＡA7. The column address defined in this way is used as a start address for burst access.

Next, the SDRA specified by the command
The main operation modes of M will be described. [1] The mode register set command is a command for setting the mode register 220. This command is CSb,
The command is specified by RASb, CASb, WEb = low level, and data to be set (register set data) is given via A0 to A9. Although not particularly limited, the register set data is set to a burst length, a CAS latency, a write mode, or the like. Although not particularly limited, the settable burst length is 1, 2, 4, 8, and full page (256), the settable CAS latency is 1, 2, 3, and the settable write mode is burst mode. Light and single light.

The CAS latency specifies how many cycles of the clock signal CLK are required from the fall of CASb to the output operation of the data output buffer 211 in a read operation specified by a column address read command described later. It is. Until the read data is determined, an internal operation time for data read is required, and this is set in accordance with the operating frequency of the clock signal CLK. In other words, when using a clock signal CLK with a high frequency, the CAS latency is set to a relatively large value, and when using a clock signal CLK with a low frequency, the CAS latency is set to a relatively small value.

[2] The row address strobe / bank active command is used to specify the row address strobe and A
9, CSb, RASb = low level, CASb, WEb
= High level. At this time, the address supplied to A0 to A8 is captured as a row address signal, and the signal supplied to A9 is captured as a memory bank selection signal. The fetch operation is performed by the clock signal CLK as described above.
Is performed in synchronization with the rising edge of. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

[3] The column address read command is
It is a command necessary to start the burst read operation and a command for giving an instruction of a column address strobe. CSb, CASb, = low level, Rb
ASb, WEb are specified by high level, and at this time, the addresses supplied to A0 to A7 are taken in as column address signals. The fetched column address signal is supplied to the column address counter 207 as a burst start address. In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the clock signal CLK. Column address counter 207 in synchronization with
Are sequentially selected in accordance with the address signal output from and read out continuously. The number of data to be continuously read is the number specified by the burst length. The start of reading data from the output buffer 211 is performed after waiting for the number of cycles of the clock signal CLK defined by the CAS latency.

[4] The column address write command is a command necessary to start the burst write operation when the mode register 220 is set to burst write as a mode of the write operation. When single write is set in the mode register 220, this is a command necessary to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write. The command is CSb, CASb, WEb, = low level, RAS
b = instructed by high level, at this time A0 to A7
Is taken in as a column address signal. The column address signal thus captured is supplied to the column address counter 207 as a burst start address in burst write.
The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of write data is started from the column address / write command cycle.

[5] The precharge command is A8, A
9 is a command to start the precharge operation for the memory bank selected by CS9, CSb, RASb, WE
b, = low level, CASb = high level.

[6] The auto refresh command is a command required to start auto refresh, and CSb, RASb, CASb = low level,
Indicated by WEb, CKE = high level. The refresh operation by this is the same as the CBR refresh.

[7] When the self-refresh entry command is set, the self-refresh function operates while CKE is kept at the low level. During this time, a predetermined interval is automatically set even if no external refresh instruction is given. Performs a refresh operation.

[8] The burst stop in full page command is a command necessary to stop the burst operation for a full page for all memory banks, and is ignored in burst operations other than the full page. This command is CASb, WEb = low level,
Indicated by RASb, CASb = high level.

[0034]

[9] The no operation command is a command for not performing a substantial operation,
Instructed by CSb = low level and RASb, CASb, WEb = high level.

In the SDRAM, when a burst operation is being performed in one memory bank, another memory bank is designated during the burst operation and a row address strobe / bank active command is supplied. The row address operation in the other memory bank is enabled without affecting the operation in one memory bank. For example, the SDRAM has means for internally holding data, addresses, and control signals supplied from the outside, and the held contents, particularly addresses and control signals, are not particularly limited, but may be held for each memory bank. It has become. Alternatively, data of one word line in a memory block selected by a row address strobe / bank active command cycle may be latched by a latch circuit (not shown) for readout before a column-related operation. I have. Therefore,
Unless data collision occurs at the data input / output terminals I / O0 to I / O15, during execution of a command whose processing has not been completed, precharge to a memory bank different from the memory bank to be processed by the command being executed The internal operation can be started in advance by issuing a command, a row address strobe / bank active command.

Further, the SDRAM 1 receives the clock signal CL
Since data, addresses, and control signals can be input and output in synchronization with K, a large-capacity memory similar to a DRAM can operate at a high speed comparable to that of an SRAM. By specifying the number of data to be accessed by the burst length, it is understood that a plurality of data can be read or written continuously by sequentially switching the selection state of the column system by the built-in column address counter 207. .

The SDRAM 1 generates an internal operation power supply by a step-down circuit 230 that steps down the external power supply voltage VDD and a word line level generation circuit 231 that steps up the external power supply voltage VDD. The boosted voltage VPP generated by the word line level generation circuit 231 is applied to the word drivers 213A and 213A.
3B is a word line drive voltage. The operating power supply for the other circuits such as the row decoders 201A and 201B and the sense amplifier and column selection circuits 202A and 202B is the step-down voltage VDL generated by the step-down circuit 230.

The SDRAM is set in the power down mode when the clock enable signal CKE is fixed at a low level. In the power-down mode, as described above, if the self-refresh entry command is set, the refresh operation is automatically performed at a predetermined interval during the period without externally giving a refresh instruction. In this example, it is assumed that the potential of external power supply voltage VDD is reduced in the power down mode. In other words, it is recommended to lower the potential of the external power supply voltage VDD on the system in the power down mode. In this sense, the power down mode is a low power consumption mode or a data retention mode. In this example, when the clock enable signal CKE is fixed at the low level, the controller 212 asserts the enable signal 221 in the data retention mode. Although not particularly limited, the enable signal 2
21 may be added as a condition for asserting that the level of the external power supply voltage VDD is equal to or lower than a predetermined level. This condition is satisfied when the external power supply voltage V
This is unnecessary if the reduction of the DD level is guaranteed.

FIG. 2 shows the word line level generating circuit 23.
One detailed example is shown. Word line level generator 2
Reference numeral 31 denotes a first booster circuit 232 for boosting the external power supply voltage VDD, a second booster circuit 233 capable of further boosting the boosted voltage formed by the first booster circuit 232, and the second booster circuit 233. An output voltage selection circuit 234 that selects the output of the second booster circuit 233 instead of the output of the first booster circuit 232 when the booster circuit 232 performs the boost operation; and an enable signal for the data retention mode output from the controller 212. When 221 indicates the data retention mode, the output voltage selection circuit 234 is turned off and the second booster circuit 233 is boosted, and the output voltage of the second booster circuit 233 is changed to the boosted voltage V.
Select as PP.

Therefore, when a self-refresh entry command is set in SDRAM 1 and a power down mode is instructed, signal 221 is asserted. When the power down mode is designated, the level of the external power supply voltage VDD is reduced on the system. Therefore,
The power consumption on the system including the SDRAM 1 is reduced. At this time, the word line level generating circuit 231 boosts the external power supply voltage VDD using the two boosting circuits 232 and 233 in series in response to the assertion of the signal 221. The difference from the normal mode is that only the booster circuit 232 is operated on one side. Therefore, even in the power down state, word line selection level VPP is set to the same level as in the normal operation. As a result, even when auto-refresh is performed in the power down state, the word line selection level is maintained at the normal level, so that the refresh of the information stored in the memory cell is completely performed.

FIG. 3 is a block diagram of a computer system which is an example of a data processing system using the SDRAM 1. This computer system includes a processor board 10 and peripheral circuits. In the processor board 10, a memory controller 13 and a PCI (Peripheral Component Interconnect) bus controller 14, which are typically shown, are connected to a processor bus 12 to which the microprocessor 11 is connected, centering on the microprocessor 11. Memory controller 13
SDRAM 1 as a main memory which is a work area or a primary storage area of the microprocessor 11
Are combined. The PCI bus controller 14 sends low-speed peripheral circuits to the processor bus 1 via the PCI bus 16.
2 functions as a bridge circuit for interfacing. Although not particularly limited, the PCI bus 16 includes a display controller 17 and an IDE (Integrated Device).
Electronics) Interface Controller 18, SC
An SI (Small Computer System Interface) interface controller 19 and another interface controller 20 are connected. The display controller 17 is connected to a frame buffer memory 21.

As peripheral circuits, a display 22 coupled to the display controller 17, a hard disk drive (HDD) 23 coupled to the IDE interface controller 18, an image scanner 24 coupled to the SCSI interface controller 19, and the other components. Keyboard 25, mouse 26 and modem 2 coupled to interface controller 20
7 and the like are provided.

A power supply circuit 30 is arranged on the processor board 10. Although not particularly limited, the power supply circuit 30 sets the processor board 10 to a low power consumption state when the standby signal STBY is asserted. For example,
The level of the power supply voltage VDD is reduced. The standby signal STBY is also input to the memory controller 13 and the like. The memory controller 13 outputs the standby signal S
When TBY is asserted, a self-refresh entry command is set in the SDRAM 1 and the clock enable signal CKE is fixed at a low level. As a result, the above-described power down mode is instructed to the SDRAM 1, and the data retention of the SDRAM is also guaranteed. Therefore, the data processing system of FIG. 3 realizes both the power-down state (low power consumption) by the standby signal STBY and the refresh of the information stored in the SDRAM 1.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the setting of the power down state of the SDRAM is not limited to the above description, and it is possible to set the power down state by a combination of the levels of a plurality of access control signals. Further, the switching of the boosting operation in the word line level generating circuit may be automatically performed when the detection level is equal to or lower than a certain level by using a level detecting means of the external power supply voltage VDD. Further, the clock enable signal CKE is not limited to the case where it is output by the memory controller, and may be output by a clock pulse generator on the system. Alternatively, the data may be directly output by a microprocessor or a microcomputer.

In the above description, the invention made mainly by the present inventor has been described in the SDR which
The case where the present invention is applied to the AM has been described, but the present invention is not limited to this, and the DRAM, the pseudo SRAM,
The present invention can be widely applied to various semiconductor devices such as a semiconductor device for data processing such as a microprocessor or a microcomputer in which a DRAM or an SDRAM is on-chip.

The present invention can be applied to a semiconductor device under a condition that a power-down state must be realized under a restriction of a data holding operation, and further to a data processing system.

[0048]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when the data retention mode is not set, the driving level of the word driver is set to the second level.
It is formed by one boosting means. When the data retention mode is set, the drive level of the word driver is formed by using both the first boosting means and the second boosting means for boosting its output. Therefore, it is possible to satisfy both the low power consumption due to the reduction of the external power supply voltage in the standby state and the data retention in the standby state.

By employing the above-described semiconductor device in the data processing system, even if a semiconductor device having a restriction on the data holding operation has to be used, a sufficiently low power consumption state (power down state) of the entire system is required. )
Can be realized.

[Brief description of the drawings]

FIG. 1 is an example of a semiconductor device according to the present invention, SDRA
It is a block diagram of M.

FIG. 2 is a block diagram illustrating an example of a word line level generation circuit.

FIG. 3 is a block diagram of a computer system which is an example of a data processing system using an SDRAM.

[Explanation of symbols]

 Reference Signs List 1 SDRAM 10 Processor board 11 Microprocessor 13 Memory controller 30 Power supply circuit STBY Standby signal MC Memory cell 200A, 200B Memory array 213A, 213B Word driver VDD External power supply voltage VPP Boost voltage VDL Buck voltage 231 Word line level generating circuit 232 First Booster circuit 233 Second booster circuit 234 Select circuit CKE Clock enable signal

Claims (3)

[Claims] A first booster for boosting an external power supply voltage; a second booster capable of further boosting a boosted voltage formed by the first booster; and a second booster. An output voltage selecting means for selecting the output of the second boosting means instead of the output of the first boosting means when performing the boosting operation, and a driver using the boosted voltage selected by the output voltage selecting means as a drive level. A semiconductor device, comprising: a circuit driven by the driver; and a controller that causes the output voltage selection means to select the output voltage of the second boosting means based on an external instruction. . 2. A first booster for boosting an external power supply voltage, a second booster capable of further boosting a boosted voltage formed by the first booster, and the second booster. Output voltage selecting means for selecting the output of the second boosting means instead of the output of the first boosting means when performing the boosting operation, and using the boosted voltage selected by the output voltage selecting means as a word line selection level. A memory cell array having a word driver, a dynamic memory cell having a word line driven by the word driver, a selection terminal connected to the word line, and a data input / output terminal connected to the bit line; and a word from the memory cell array. A row address selection unit for selecting a line, a column address selection unit for selecting a bit line from the memory cell array, and a selection by the column address selection unit An external input / output circuit for conducting the selected bit line to the outside, an internal operation mode in accordance with control information provided from the outside, and an output voltage of the second boosting means to the output voltage selecting means when the data retention mode is designated. And a controller for selecting
A semiconductor device comprising: 3. The data retention mode of the first semiconductor device according to claim 1 or 2, wherein the first semiconductor device controls the first semiconductor device and a standby mode is instructed to control the first semiconductor device. A mounting substrate comprising: a second semiconductor device to be instructed; and a power supply circuit that generates a power supply voltage for the first and second semiconductor devices and lowers the power supply voltage when a standby mode is instructed. A semiconductor device, characterized in that: