JPH11265169A - Liquid crystal display, array substrate and driving method for array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display with which reduction of luminance or double imprinting of an image does not occur even when propagation of pixel data in a data bus line is delayed or a waveform is rounded. SOLUTION: This device has a shift register 1, a polarity switching signal output circuit 2 for outputting polarity switching signals A and B, AND gates GT11-GTn2 for outputting pixel display timing signals corresponding to polarities, analog switches SW11-SWn2 for controlling switching corresponding to the outputs of the AND gates GT11-GTn2, and a pixel data output circuit 3 for outputting the pixel data of positive and negative polarities. Since the pixel data output circuit 3 supplies the same pixel data to the analog switches SW11-SWn2 from the ON of the analog switches SW11-SWn2 to the OFF, just before the OFF of the analog switches SW11-SWn2, the voltages of data bus lines L1 and L2 surely become a desired voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technique for a liquid crystal display or the like that periodically switches the polarity of a signal voltage supplied to a signal line.

[0002]

2. Description of the Related Art When a voltage is always applied to a liquid crystal layer in the same direction, the arrangement of the liquid crystal is solidified and the movement of the liquid crystal is slowed down, resulting in a dark display. For this reason, there has been proposed a liquid crystal display device employing an AC driving method in which the voltage applied to the liquid crystal layer is inverted in units of one frame (one screen), one horizontal line, one vertical line terminal, or one pixel. . On the other hand, the polysilicon TFT has a feature that a part of the peripheral driving circuit can be integrally formed on a glass substrate. An AC driving type liquid crystal display device using polysilicon TFTs supplies analog pixel data for positive polarity and analog pixel data for negative polarity at a predetermined timing from the outside, and either one of them is provided inside the drive circuit. Polarity analog pixel data is selected and guided to a sample and hold circuit. The sample and hold circuit is provided for each signal line, holds analog pixel data at a predetermined timing, and supplies the analog pixel data to the corresponding signal line. The analog pixel data supplied to each signal line is guided to a pixel electrode via a pixel TFT.

An analog switch is usually provided in the sample-and-hold circuit, and one analog switch is provided in one horizontal line display period.
Turn on only once. Actually, the pixel data on the data bus line immediately before the analog switch is turned off is held in the sample and hold circuit. More specifically, two analog switches are provided for each signal line. One analog switch is connected to a data bus line for supplying pixel data of a positive polarity, and the other analog switch is a pixel switch for a negative polarity. It is connected to a data bus line that supplies data.

FIG. 4 is an operation timing chart of a conventional liquid crystal display device. FIG. 4 shows a shift clock corresponding to the display cycle of the pixel, a start pulse signal for operating the shift register that determines the display timing of the pixel, a control pulse signal output from the shift register, a polarity switching signal,
Each timing waveform of the positive and negative data bus lines is shown.

As shown in FIG. 4, the shift register outputs a control pulse signal by shifting the phase by one cycle of the shift clock. The corresponding analog switch is turned on only while the control pulse signal is at the high level. The cycle of the pixel data supplied to each data bus line is synchronized with the timing of the control pulse signal, and when the control pulse signal is at a high level, the analog switch is turned on,
Pixel data on the data bus line is supplied to the signal line.

For example, between times T1 and T2 in FIG. 4, the control pulse signal G1 corresponding to the signal line S1 becomes high level, and the data S1 (+) is applied to the data bus line for positive polarity.
However, data S1 (−) is supplied to the data bus line for negative polarity. Therefore, one of the data S1 (+) and S1 (-) is supplied to the signal line S1 according to the logic of the polarity switching signal.

[0007] Between times T2 and T3 in FIG. 4, the control pulse signal G2 corresponding to the signal line S2 is at a high level, and the data bus line for positive polarity has data S2 (+).
However, the data S2 (−) is supplied to the data bus line for the negative polarity. Therefore, one of the data S2 (+) and S2 (-) is supplied to the signal line S2 according to the logic of the polarity switching signal.

[0008]

Since a large number of sample-and-hold circuits are connected to the data bus line, the signal waveform on the data bus line is generally distorted. Therefore, as shown in FIG. 5, the signal voltage on the data bus line may not reach a desired voltage immediately before the analog switch is turned off. In such a case, the voltage held in the sample-and-hold circuit may be reduced. Becomes lower than the original voltage,
The brightness is reduced.

If the load on the data bus line is heavy, the signal is delayed. In the worst case, the pixel data to be displayed during the on-period of the analog switch is not enough.
The data of the immediately preceding pixel may be held in the sample and hold circuit. In such a case, a ghost phenomenon in which an image is double reflected occurs, and the display quality of the liquid crystal is significantly reduced.

The present invention has been made in view of such a point, and an object of the present invention is to reduce the luminance even if the pixel data on the data bus line causes a propagation delay or the waveform of the pixel data becomes blunt. It is an object of the present invention to provide a liquid crystal display device, an array substrate, and a method for driving an array substrate, which do not cause a problem such as a reduction in image quality or double reflection of an image.

[0011]

In order to solve the above-mentioned problems, a first aspect of the present invention provides a plurality of scanning lines and signal lines arranged in a matrix and a scanning line for driving each of the scanning lines. An array substrate including a driving circuit, a signal line driving circuit for driving each of the signal lines, and a plurality of pixel display portions provided for different combinations of the scanning lines and the signal lines; and an array substrate facing the array substrate. A liquid crystal display device in which the array substrate and the counter substrate are disposed so as to face each other and a liquid crystal material is sealed between the two substrates. The liquid crystal display device supplies positive pixel data to a positive data bus line. A pixel data output circuit for supplying pixel data of a negative polarity to a data bus line of a negative polarity, and a polarity for outputting a polarity switching signal for instructing a polarity switching of a signal voltage supplied to each signal line A switching signal output circuit, and a pixel provided for each signal line, for selecting one of pixel data on the positive data bus line and pixel data on the negative data bus line based on the polarity switching signal. A data selection circuit, wherein the pixel data output circuit continuously supplies the same pixel data to a data bus line from before the pixel data selection circuit makes an arbitrary selection until after the selection is canceled. Is what you do.

According to a fifth aspect of the present invention, there are provided a plurality of scanning lines and signal lines arranged in a matrix, a scanning line driving circuit for driving each of the scanning lines, and a signal line driving circuit for driving each of the signal lines. Circuit, and a plurality of pixel display units provided for different combinations of scanning lines and signal lines, in an array substrate, supplying pixel data of a positive polarity to a data bus line of a positive polarity, and a pixel of a negative polarity. A pixel data output circuit for supplying data to the negative data bus line, a polarity switching signal output circuit for outputting a polarity switching signal for instructing a polarity switching of a signal voltage supplied to each signal line,
A pixel data selection circuit that is provided for each signal line and selects one of pixel data on the positive data bus line and pixel data on the negative data bus line; The same pixel data is continuously supplied to the data bus line from before the pixel data selection circuit makes an arbitrary selection to after the selection is canceled.

According to a ninth aspect of the present invention, there are provided a plurality of scanning lines and signal lines arranged in a matrix, a scanning line driving circuit for driving each of the scanning lines, and a signal line driving circuit for driving each of the signal lines. In a method of driving an array substrate having a circuit and a plurality of pixel display units provided for different combinations of scanning lines and signal lines, a positive pixel data and a negative data bus supplied to a positive data bus line are provided. Select one of the pixel data of the negative polarity supplied to the line and supply it to the corresponding signal line, and select one of the pixel data of the positive polarity and the pixel data of the negative polarity The same pixel data is continuously supplied to the selected data bus line from before the selection to after the selection is cancelled.

The first to ninth aspects of the present invention will be described with reference to FIG. 1, for example. A "pixel data output circuit" is a pixel data output circuit 3, and a "polarity switching signal output circuit" is a polarity switching signal output circuit 2. The "pixel data selection circuit" corresponds to each of the analog switches SW11 to SWn2.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a liquid crystal display device and an array substrate according to the present invention will be specifically described with reference to the drawings. FIG. 1 is a schematic circuit diagram of an embodiment of the liquid crystal display device according to the present invention. This circuit uses polysilicon T
An FT is formed on the array substrate.

The array substrate shown in FIG. 1 has a shift register 1 for outputting a control signal for pixel display, and a polarity switching signal output circuit 2 for outputting polarity switching signals A and B for AC driving.
And an AN that outputs a pixel display timing signal according to the polarity
D-gates GT11 to GTn2, and analog switches SW11 to SW3 which are switched and controlled in accordance with the outputs of the AND gates GT11 to GTn2.
SWn2 and a pixel data output circuit 3 that outputs pixel data of positive polarity and negative polarity. The positive pixel data output from the pixel data output circuit 3 is supplied to a positive data bus line L1, and the negative pixel data is supplied to a negative data bus line L2.

Two AND gates GT11 to GTn2 and two analog switches SW11 to SWn2 are provided for each of the signal lines S1 to Sn. One of the AND gates GT11, GT21,
, GTn1 are connected to the output terminal of the corresponding shift register 1 and the polarity switching signal A. The other AND gate G
, GTn2, the output terminal of the corresponding shift register 1 and the polarity switching signal B are connected.

Further, one analog switch SW11, S
One end of W21,..., SWn1 is a positive data bus line L1.
The other end is connected to corresponding signal lines S1 to Sn. One end of the other analog switch SW12, SW22,..., SWn2 is connected to the negative data bus line L2, and the other end is connected to the corresponding signal line S1 to Sn. Analog switch SW1
1, SW21,..., SWn1 are AND gates GT11, GT21,
,..., SWn2 are turned on only when the outputs of the AND gates GT12, GT22,..., GTn2 are at the high level.

The AND gates GT11 to GTn2 and the analog switches SW11 to SWn2 in FIG. 1 correspond to a signal line driving circuit. In FIG. 1, a scanning line driving circuit for driving a pixel TFT (not shown) is omitted.

The array substrate shown in FIG. 1 is bonded to a counter substrate, and liquid crystal is sealed between the two substrates to produce a liquid crystal display substrate.

FIG. 2 is a block diagram showing a schematic configuration of the whole system for driving the liquid crystal display substrate. The illustrated system includes a computer 11, a liquid crystal display substrate 12, and a substrate control unit 13 that controls the liquid crystal display substrate 12. The computer 11 sends a clock for liquid crystal display and pixel data to the substrate control unit 13. The substrate control unit 13 converts the pixel data sent from the computer 11 into analog pixel data, and sends the pixel data to the liquid crystal display substrate 12 in synchronization with a clock.

The polarity switching signal output circuit 2 and the pixel data output circuit 3 in FIG. 1 may be provided in either the liquid crystal display substrate 12 or the substrate control section 13. Further, the liquid crystal display substrate 12 and the substrate control section 13 may be integrally formed on one glass substrate.

FIG. 3 is an operation timing chart of the liquid crystal display device of FIG. Hereinafter, the operation of the apparatus of FIG. 1 will be described with reference to the timing chart of FIG. Hereinafter, a V-line driving method in which the polarity is inverted for each vertical line will be described as an example.

In FIG. 3, times T1 to T7 indicate the timing of the nth frame, and times T11 to T17 indicate the timing of the (n + 1) th frame. When the start pulse signal goes high at time T1 in FIG. 3, the shift register 1 starts operating, and each output terminal of the shift register 1 outputs a pulse having the same length as the shift clock cycle for one shift clock cycle. The output is shifted sequentially. While the pulse is being output, the analog switches SW11 to SWn2 are turned on. Hereinafter, each output of the shift register 1 is referred to as a control pulse signal, and a pulse included in the control pulse signal is referred to as a control pulse. The pixel data output circuit 3 of FIG. 1 transmits the same pixel data to the data bus lines L1 and L2 from before the control pulse is output from the shift register 1 until after the control pulse is output.
L2. Thus, immediately before the analog switches SW11 to SWn2 are turned off, the signal voltage on the data bus lines L1 and L2 becomes a desired voltage.

For example, when the control pulse signal G1 output from the shift register 1 becomes high level between the times T2 and T4, the pixel data output circuit 3 outputs the signal from the time T1 before the time T2 to the time after the time T4. Until time T5, the pixel data S1 (+) is supplied on the positive data bus line L1.

Connected to the output terminal of the shift register 1
Since the polarity switching signal B is at the high level, the AND gate GT11 outputs the control pulse output from the shift register 1 as it is. Therefore, while the control pulse is being output (time T2 to
Turns on only for T4).

On the other hand, the output of the AND gate GT12 is fixed at a low level because the polarity switching signal A is at a low level, and the analog switch SW12 is also kept off.

The positive data bus line L1 has:
Since the pixel data S1 (+) is supplied from time T1 to T5, this data is supplied while the control pulse is output from the output terminal of the shift register 1 (time T2 to T4).
Is supplied to the signal line S1. Actually, the voltage of the data bus line L1 immediately before the time T4 when the analog switch SW11 is turned off is held in the signal line. However, since the voltage of the data bus line L1 is already stable at the time T4, The voltage of the signal line S1 becomes a desired voltage according to the pixel data.

Next, when a control pulse is output from the output terminal of the shift register 1 between times T4 and T6, the pixel data output circuit 3 outputs a signal from time T3 before time T4 to time after time T6. Until T7, data S2 (+) is supplied to the negative data bus line L2.

Connected to the output terminal of the shift register 1
Since the polarity switching signal A is at a low level, the AND gate GT21 is fixed at a low level, and the analog switch SW21 remains off. On the other hand, the output of the AND gate GT22 indicates that the polarity switching signal B is at a high level.
The control pulse output from the shift register 1 is output as it is. Therefore, the analog switch SW22 is turned on only while the control pulse is being output (time T4 to T6).

At the negative polarity data bus line L2, the time T
Since the pixel data S2 (-) is supplied from 3 to T7, this data is supplied to the signal line S2 while the control pulse is output from the output terminal of the shift register 1 (time T4 to T6). Is done.

As shown in FIG. 3, the pixel data S1 (+), S3 at the odd pixel position are provided on the positive data bus line L1.
(+), S5 (+),... Are supplied to the negative data bus line L2, and pixel data S2 (−), S4 (−),
S6 (-),... Are supplied.

The data supplied to each of the data bus lines L1 and L2 has a period twice as long as the control pulse width, that is, a period corresponding to two periods of the shift clock. Further, the data supplied to each data bus line is shifted in phase by half a cycle, that is, by one cycle of the shift clock.

On the other hand, in the (n + 1) frame shown in FIG. 3, the logic of the polarity switching signals A and B is opposite to that of the n frame.
Between times T11 and T13, pixel data S1 (-) on the negative data bus line L2 is supplied to the signal line S1. Further, during the time T14 to T16, the positive data bus line L
1, the pixel data S2 (+) is supplied to the signal line S2.

As described above, in the present embodiment, the same pixel data is transferred to the data bus lines L1 and L2 from before the analog switches SW11 to SWn2 are turned on to after they are turned off.
L2, the data bus line L
Even if the pixel data on L1 and L2 causes a signal delay or the waveform of the pixel data becomes blunt, the analog switch S
Immediately before W11 to SWn2 are turned off, the data bus line L
1 and L2 can be set to desired voltages.
Therefore, according to the present embodiment, the data bus line L
The voltage drop of the signal line due to the signal delay on 1 and L2 and the rounding of the waveform can be prevented, and the problems such as the decrease in luminance and the double reflection, which are the conventional problems, do not occur.

In the above-described embodiment, the V-line drive system has been described as an example. However, the present invention can be applied to other AC drive systems. For example, an HV inversion driving method in which the polarity of the signal voltage is inverted in pixel units, an H line driving method in which the polarity of the signal voltage is inverted in units of one horizontal line, or frame inversion driving in which the polarity of the signal voltage is inverted in units of one screen When the signal lines are driven by the methods, the timing of the polarity switching signals A and B may be set according to each method.

Further, in the operation timing chart of FIG. 3, the period on the data bus line is determined by analog switches SW11 to SW.
Although the example in which the ON period of n2 is set to twice is shown, it is not always necessary to set the ON period to twice. That is, it is sufficient that the same pixel data is supplied to the data bus line from before the analog switches SW11 to SWn2 are turned on to after they are turned off. Therefore, the AND gates GT11 to GTG
The control pulse output from Tn2 does not necessarily have to be shifted in phase by one cycle of the shift clock as shown in FIG.

[0038]

As described above in detail, according to the present invention, the same pixel data is stored in the data bus line from before the pixel data selection circuit selects the pixel data until after the pixel data selection circuit cancels the selection. Since the data is continuously supplied, even if the pixel data on the data bus line causes a propagation delay or the waveform is rounded, the signal voltage of the signal line can be reliably set to a desired voltage. As a result, a high-quality liquid crystal display without a decrease in luminance or double reflection can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram of an embodiment of an array substrate.

FIG. 2 is a block diagram showing a schematic configuration of an entire system for driving a liquid crystal display substrate.

FIG. 3 is an operation timing chart of the liquid crystal display device of FIG.

FIG. 4 is an operation timing chart of a conventional liquid crystal display device.

FIG. 5 is a diagram showing an example in which a signal waveform on a data bus line is distorted.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register 2 Polarity switching signal output circuit 3 Pixel data output circuit 11 Computer 12 Liquid crystal display board 13 Substrate control part A, B Polarity switching signal L1 Positive data bus line L2 Negative data bus line GT11-GTn2 AND gate SW11-SWn2 Analog switch

Claims (9)

[Claims] A plurality of scanning lines and signal lines arranged in a matrix; a scanning line driving circuit for driving each of the scanning lines; a signal line driving circuit for driving each of the signal lines; And an array substrate having a plurality of pixel display units provided for different combinations of signal lines, and a counter substrate disposed to face the array substrate, wherein the array substrate and the counter substrate are disposed to face each other. In a liquid crystal display device in which a liquid crystal material is sealed between both substrates, a pixel data output that supplies positive pixel data to a positive data bus line and supplies negative pixel data to a negative data bus line A circuit, a polarity switching signal output circuit for outputting a polarity switching signal for instructing a polarity switching of a signal voltage supplied to each signal line, and a polarity switching signal output circuit provided for each signal line. A pixel data selection circuit that selects one of pixel data on the positive polarity data bus line and pixel data on the negative polarity data bus line. A liquid crystal display device wherein the same pixel data is continuously supplied to a data bus line from before the selection circuit makes an arbitrary selection to after the selection circuit cancels the selection. 2. The pixel data output circuit according to claim 1, wherein the pixel data selection circuit outputs each pixel data to the positive data bus line at a period substantially twice as long as a period during which the pixel data selection circuit selects any one pixel data. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is supplied to the negative data bus line and the phases of both data bus lines are shifted from each other by a half cycle. 3. The pixel data output circuit supplies pixel data at an odd-numbered pixel position to one of the positive-polarity data bus line and the negative-polarity data bus line in the pixel arrangement order, and supplies the other pixel data at an even-numbered pixel position to the other. 3. The liquid crystal display device according to claim 1, wherein the pixel data is supplied in a pixel arrangement order. 4. A polarity switching signal output circuit comprising: an HV inversion drive system for switching polarity in pixel units; an H line inversion drive system for switching polarity in horizontal line units; a V line inversion drive system for switching polarity in vertical line units; The liquid crystal display device according to any one of claims 1 to 3, wherein the polarity switching signal is output at a timing according to any one of a frame inversion driving method of switching a polarity in units of a screen. 5. A plurality of scanning lines and signal lines arranged in a matrix, a scanning line driving circuit for driving each of the scanning lines, a signal line driving circuit for driving each of the signal lines, and a scanning line. And a plurality of pixel display units provided for different combinations of signal lines, wherein positive pixel data is supplied to a positive data bus line, and negative pixel data is supplied to a negative data bus. A pixel data output circuit for supplying a bus line; a polarity switching signal output circuit for outputting a polarity switching signal for instructing a polarity switching of a signal voltage supplied to each signal line; A pixel data selection circuit that selects one of pixel data on a bus line and pixel data on the negative data bus line. , The array substrate having the pixel data selection circuit is before making any selection, until after canceled the selection, and supplying continuously the same pixel data in the data bus line. 6. The pixel data output circuit outputs each pixel data to the positive data bus line at a period substantially twice as long as a period during which the pixel data selection circuit selects any one pixel data. 6. The array substrate according to claim 5, wherein the array substrate is supplied to the negative data bus line and the phases of both data bus lines are shifted by half a period from each other. 7. The pixel data output circuit supplies pixel data at an odd pixel position to one of the positive data bus line and the negative data bus line in the pixel arrangement order, and supplies the pixel data at an even pixel position to the other. 7. The array substrate according to claim 5, wherein the pixel data is supplied in a pixel arrangement order. 8. A polarity switching signal output circuit comprising: an HV inversion drive system for switching polarity in pixel units; an H line inversion drive system for switching polarity in horizontal line units; a V line inversion drive system for switching polarity in vertical line units; 8. The array substrate according to claim 5, wherein a polarity switching signal is output at a timing corresponding to one of a frame inversion driving method and a polarity switching for each screen. 9. A plurality of scanning lines and signal lines arranged in a matrix, a scanning line driving circuit for driving each of the scanning lines, a signal line driving circuit for driving each of the signal lines, and a scanning line. And a plurality of pixel display sections provided for different combinations of signal lines, wherein the pixel data supplied to the positive data bus line and the pixel data supplied to the negative data bus line are supplied to the positive data bus line. Select one of the negative pixel data and supply it to the corresponding signal line, before selecting either the positive pixel data or the negative pixel data, A method of driving an array substrate, wherein the same pixel data is continuously supplied to a selected data bus line until after the selection is canceled.