JPH11262028A - Signal angle adjustment method and signal angle adjustment device thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a signal processing with fine resolution, regardless of a small arithmetic bit width. SOLUTION: This device that changes an angle of orthogonal signals such as color difference signals of a digital video signal, which is component-coded, for example, by ±θ deg. is provided with 1st phase shift means (8-13) that shift the phase of an input signal by a prescribed angle θk(e.g. -45 deg.) and with 2nd phase shift means (14-23) that shift the phase of the input signal by [-θk+θ], when θ is an angle desired to be changed, and the 1st phase shift means and the 2nd phase shift means are connected in series in an arbitrary order. For example, when the phase of the signal is changed by ±30 deg. with center as πk=45 deg., coefficients with a large change in both cos coefficient and sine coefficient is used and expressed in a small bit width. Thus, the bit width required for the arithmetic operation is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal angle adjusting method and a signal angle adjusting device, and more particularly to a signal angle adjusting method and a signal angle adjusting device capable of performing signal processing with a fine resolution with a small operation bit width. It is.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing the configuration of a conventional hue adjustment circuit for component digital video signals used in televisions and VTRs. A method of changing the hue will be described with reference to FIG. First, a component signal is represented by the following relational expression based on R, G, B and three primary colors.

[0003]

(Equation 1)

A composite signal is expressed as follows when the setup of the NTSC system (the shift amount of the black level) = 0:

[0005]

(Equation 2)

Here, fsc is a chrominance subcarrier frequency. Here, changing the hue ± θ ° is as follows.

[0007]

(Equation 3)

[0008] Hereinafter, they are expressed as BY / 2.03 = U and RY / 1.14 = V.

FIG. 7 shows a color difference signal vector when C2 (C2, Δφ + θ) is obtained by changing the color signal Cl (C1, Δφ) represented by the color difference signal (Ul, V1) by θ °. FIG. Assuming that the color difference signal changed by θ ° is (U2, V2), the following relational expression is derived.

[0010]

(Equation 4)

Here, since the length of the vector is C1 = C2, U2 and V2 are respectively expressed as follows.

[0012]

(Equation 5)

Therefore, the signal angle is changed by ± θ ° -the general formula is as follows.

[0014]

(Equation 6)

Equations (3) and (4) are replaced with the composite signal equation (1)
The following applies to

[0016]

(Equation 7)

It can be seen from the calculations of equations (3) and (4) that the hue changes by ± θ ° with respect to the original signal. Although the NTSC system has been described as an example, the same applies to other signal systems (PAL, PAL-M).

[0018]

In the above-described conventional hue adjustment circuit, the minimum unit of hue variation is 0.5 °.
In order to make cos0 ° = 1, cos0.5 ° ≒ 0.99996 must be distinguishable. The bit width n required to express this in a binary number is as follows, where 2 k raised to the power of 2 ^ k.

[0019]

(Equation 8)

Therefore, the required bit width is 16 bits or more. Note that the reason for setting nl is 1 to express cos0 ° = 1.
This is because more bits are needed. The sin coefficient is 0 ±
In the range of 45 °, the change is larger than that of the cos coefficient. With 9 bits, a resolution of 0.5 ° is obtained.

As described above, in the conventional example, since the configuration is variable around 0 °, the variation of the cos coefficient is small, and if a fine variation is to be performed, the operation bit width increases and the circuit scale increases. There was a point.

It is an object of the present invention to provide a signal angle adjusting method and a signal angle adjusting apparatus which can solve the above-mentioned problems of the prior art and enable signal processing having a fine resolution with a small operation bit width. It is in.

[0023]

SUMMARY OF THE INVENTION The present invention relates to an apparatus for changing the angle of an orthogonal signal such as a color difference signal of a component-coded digital video signal by. +-.. degree. A first phase shifter that shifts the phase of the input signal by [−θk + θ] when an angle to be changed is θ, and a first phase shifter that shifts the phase of the input signal by [−θk + θ]. The phase shifter and the second phase shifter are connected in series in an arbitrary order.

Conventionally, since the configuration is variable around 0 °, a change in the cos coefficient is small and a large bit width is required. -Generally, it is required that the hue variable range is about ± 30 °. For example, if ± 30 ° is centered around θ = 45 ° where cos θ = sin θ, the cos coefficient, sin
A portion having a large change in both coefficients can be used, and can be expressed with a small bit width. Therefore, for example, -45 ° in advance
After the phase shift, if it is changed by 45 ± θ °, ±
The same result as varying by θ ° can be obtained, and the bit width required for the operation can be reduced.

[0025]

Embodiments of the present invention will be described below in detail. As described above, generally, the required range of the hue is about ± 30 °, and cosθ =
If you change ± 30 ° around θ = 45 °, which is sinθ, cos
Both the coefficient and the sine coefficient can use a portion having a large change, and can be expressed with a small bit width.

When changing by 45 ± 30 °, the cos coefficient is 15 ° s
The coefficient change is smallest at around 75 ° in coefficient. cos15 ° ≒
Since 0.96593 and cos15.5 ° ≒ 0.96363, the bit width required to represent in binary is as follows.

[0027]

(Equation 9)

Therefore, if there are 9 bits, a resolution of 0.5 ° can be obtained for both the cos coefficient and the sin coefficient. Of course, a finer resolution can be obtained by increasing the bit width. Also, when changing by ± 30 ° or more, the operation bit width increases,
This method can be applied.

Therefore, after the phase is shifted by -45 ° in advance, 45 ± θ
If the angle is changed, the same result as that obtained by changing the angle by ± θ around 0 ° can be obtained, and the bit width required for the operation can be reduced. This arithmetic expression is obtained by modifying the expressions (3) and (4) as follows.

[0030]

(Equation 10)

When the phase is shifted by -45 ± θ ° after the phase is shifted by + 45 °, the following is obtained.

[0032]

[Equation 11]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a hue adjustment circuit for a digital video signal to which the present invention is applied. The first embodiment is a circuit for performing the calculation represented by the above-described equations (5) and (6).

The input terminal 1 receives a digitally encoded component signal Ul, and the input terminal 2 receives a digitally encoded component signal Vl. The component signal Ul is obtained by multiplying the coefficient given to the input terminal 5 by the multiplier 8.
After being multiplied by (1 / √2) × 2 ^ m, the bit shifter 10
Receive a bit shift of ^ m. However, the bit shift is an arithmetic process, and such a circuit does not exist.

After the component signal Vl is multiplied by the coefficient (1 / √2) × 2 ^ m given to the input terminal 5 by the multiplier 9,
The bit shifter 11 receives a bit shift of 1/2 m. The bit shifted (1 / √2) · Ul signal is input to the adder 12 and the subtractor 13. The bit-shifted (1 / √2) · Vl signal is input to the other input terminals of the adder 12 and the subtractor 13. The output of the adder 12 is (1 / √2) · (Ul + Vl), and the output of the subtractor 13 is (1 / √2) · (Vl−Ul). This signal is the input signal U
These are signals obtained by rotating l and Vl by -45 °.

The output of the adder 12 is the coefficient cos (45 ± θ) × 2 ^ n given to the input terminal 6 by the multiplier 14 and the coefficient sin (45 ± θ) given to the input terminal 7 by the multiplier 16. ) × 2 ^ n. The output of the subtractor 13 is a coefficient sin (45 ± θ) × 2 ^ n given to the input terminal 7 by the multiplier 15 and a coefficient cos (45 ± θ) × 2 given to the input terminal 6 by the multiplier 17. multiplied by ^ n. The outputs of multipliers 14, 15, 16, 17 are bit shifters 18, 1 respectively.
After being bit-shifted by 9, 20, and 21, they are subtracted and added by a subtractor 22 and an adder 23. The following signals are obtained from the outputs of the subtractor 22 and the adder 23.

[0037]

(Equation 12)

This signal has the same result as the above-described equations (3) and (4), and a signal obtained by changing the original signal by ± θ ° is obtained.

FIG. 2 is a block diagram showing a configuration of a second embodiment of a hue adjustment circuit for a digital video signal to which the present invention is applied. FIG. 3 is a block diagram showing the configuration of a third embodiment of a digital video signal hue adjustment circuit to which the present invention is applied. Embodiments 2 and 3 perform the same operation except that the order of the operations represented by the above-described equations (5) and (6) in Embodiment 1 is changed.

The second embodiment is an example in which the adder 12 and the subtractor 13 are brought to the head, and the third embodiment is an example in which the multipliers 8 and 9 and the bit shifters 10 and 11 are brought last. Therefore, the operation can be easily understood from the first embodiment. Note that the hue adjustment circuits based on the equations (7) and (8) are also described in Examples 1 and 2 of the hue adjustment circuit based on the equations (5) and (6).
3 can be easily realized.

FIG. 4 is a block diagram showing a configuration of a fourth embodiment of a hue adjustment circuit for a digital video signal to which the present invention is applied. The fourth embodiment is an example in which a signal level defined by the ITU-R BT601 component digital standard often used as an international standard is input. In the ITU-BT601 component digital standard, Cb =
Signal C normalized by the relational expression BY / 1.772, Cr = RY / 1.402
b and Cr are used. Therefore, BY / 2.03 = U, RY / 1.14 = V
And you get:

[0042]

(Equation 13)

From this relationship, in the fourth embodiment, the coefficient given to the multiplier 8 is (1 / √2) (1.772 / 2.03), and the coefficient given to the multiplier 9 is (1√2).
/ √2) (1.402 / 1.14).

FIG. 5 is a block diagram showing a configuration of a fifth embodiment of a digital video signal hue adjustment circuit to which the present invention is applied. Embodiment 5 is an example in which the input / output level is set to the ITU-R BT601 component digital standard. As described above, in order to convert from the component signal level to the composite signal level, the above-described operations of U and V are required. In the fifth embodiment, however, the signal level is converted by the coefficient inverse transformer. In order to return the absolute values of U and V, the absolute values are not important and the relative ratio may be used. Therefore, the coefficient given to the multiplier 8 is (1 / √2) K, K = (1.14
/ 2,03) (1.772 / 1.402), the coefficient given to multiplier 9 is (1 / √2)
After changing the hue, U2 × (l / K) = Cbo and V2 = Cro.

FIG. 6 is a block diagram showing a configuration of a sixth embodiment of a hue adjustment circuit for a digital video signal to which the present invention is applied. Embodiment 6 is an example in which the number of multipliers is reduced by performing time-division processing on a signal. The digitally encoded component signal is subjected to coefficient conversion and
Input to multiplier 8 of -45 ° phase shifter 50. (1
/ √2) Kl × 2 ^ m, a coefficient value of (1 / √2) × 2 ^ m is given to the input terminal 52, and after being selected by the switch 53, the multiplier 8
To the other input terminal. Where K = (1.14 / 2.0
3) (1.772 / 1.402).

As described above, in order to convert a component signal level into a composite signal level,
Although it is necessary to multiply U = (1.772 / 2.03) × Cb and V = (1.402 / 1.14) × Cr, in the sixth embodiment, since the signal level is returned by the coefficient inverse transformer 80, U, V Is not important, and may be a relative ratio. Therefore, the following is performed.

[0047]

[Equation 14]

The switch 53 multiplexes the coefficients so as to correspond to the multiplexed input signal Cb / Cr. By this processing, Cb × (1 / √2) K is obtained with one multiplier (8).
Cr × (1 / √2) is obtained. The output of the multiplier 8 is input to the bit shifter 10 to 1/2 m the coefficient obtained by 2 ^ m. The output of the bit shifter 10 is input to the D-type flip-flop 54 and is delayed by one clock.

By adding the output of the bit-shifted multiplier 8 and the output of the D-type flip-flop 54, an adder
Ul (−45) is obtained at the output of 12, and Vl (−45) is obtained at the output of the subtractor 13 by subtraction. U1 (−45) and Vl (−45) are as follows.

[0050]

(Equation 15)

This is a signal subjected to coefficient conversion and -45 ° phase shift. Output of subtractor 13 is D-type flip-flop 5
After delaying one clock by 5, the output of the adder 12 and the output of the D-type flip-flop 55 are selected by the switch 56, and held by the D-type flip-flop 57, whereby Ul (-4
5) and V1 (-45) are multiplexed. This makes the next 4
The number of multipliers of the 5 ± θ ° phase shifter can be reduced from four to two.

The output of the coefficient conversion and -45 ° phase shifter 50 is 45 ±
The signals are input to the multipliers 61 and 62 of the θ ° phase shifter 60. The other input terminal of the multiplier 61 is given a coefficient value of cos (45 ± θ) × 2 ^ n from the input terminal 5. To the other input terminal of the multiplier 62, a coefficient value of sin (45 ± θ) × 2 ^ n is given from the input terminal 6.

The output of the multiplier 61 passes through the bit shifter 63 and the D-type flip-flop 65 and is input to the subtracter 67.
The output of the multiplier 61 is also input to the adder 68 after the bit shift. The output of the multiplier 62 passes through the bit shifter 64 and the D-type flip-flop 66 and is input to the other input terminal of the adder 68. After the output of the multiplier 62 is bit-shifted, the subtractor 67
Is also input to the other input terminal. These outputs are held in D-type flip-flops 69 and 70, respectively, and sent to a coefficient inverse transformer 80. Assuming that the output of the D-type flip-flop 69 is U2 and the output of the D-type flip-flop 70 is V2, the following signals are obtained.

[0054]

(Equation 16)

This means that the hue can be varied by ± θ °. In the sixth embodiment, a coefficient inverse transformer 80 is added to make the output of the output terminal 91 a component signal level. The following conversion is performed in the coefficient conversion and the −45 ° phase shifter 50.

[0056]

[Equation 17]

Therefore, the coefficient inverse transformer 80 performs the following processing.

[0058]

(Equation 18)

The output of the D-type flip-flop 69 is input to the minus input of the multiplier 82, and the coefficient value (1 / K) × 2 ^ x is input to the other input from the input terminal 81. As a result, the output of the multiplier 82 becomes Cbo. The output of D-type flip-flop 70 is V2
= Cro. The output Cbo of the bit shifter 83 and the output Cro of the D-type flip-flop 70 are connected to the D-type flip-flop 84.
Select the signal delayed by 1 clock with switch 85 and switch C
The multiplex signal of bo / Cro is output to the output terminal 91.

While the embodiments of the present invention have been disclosed above, the present invention may have the following modifications. In the embodiment, an example in which a 45-degree fixed phase shifter is used is disclosed.
The phase shift angle of the fixed phase shifter is arbitrary. In this case, FIG.
Is connected in two stages in series. In this case, the phase shift angle is set to 30 degrees or 60 degrees.
In other words, sin (30 °) or cos (60 °) is 1/2 = 2-1
, And the circuit configuration is simplified.

In the embodiment, the example in which the circuit is constituted by hardware is disclosed.
It can also be realized by software processing using.

[0062]

As described above, the hue adjustment circuit according to the present invention can perform finer hue adjustment with a small operation bit width, and can reduce the circuit scale or the amount of operation because the operation bit width is small. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a hue adjustment circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a second embodiment of the hue adjustment circuit of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a hue adjustment circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a hue adjustment circuit according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a hue adjustment circuit according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a hue adjustment circuit according to a sixth embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a signal vector when a color difference signal is changed by θ °;

FIG. 8 is a block diagram illustrating a configuration of a conventional video signal hue adjustment circuit.

[Explanation of symbols]

1, 2, 90 input terminals, 3, 4, 91 output terminals,
5, 6, 7, 30, 31, 32, 51, 52, 81 ... adjustment signal input terminals, 8, 9, 14 to 17, 33, 61, 6
2, 82... Multipliers, 10, 11, 18 to 21, 63, 6
4, 83... Bit shifters, 12, 13, 22, 23, 6
7, 68 ... adder, 54, 55, 57, 65, 66, 6
9, 70, 84 ... D type flip-flop, 53, 5
6, 85 ... switch

Claims (4)

[Claims] 1. A method of adjusting a signal angle of a signal represented by two orthogonal signal components, wherein when a predetermined angle is θk and an angle to be changed is θ, an input signal is shifted by θk. A method for adjusting a signal angle, comprising: performing a first step that is compatible with the first step and a second step that shifts the phase of an input signal by [−θk + θ] in an arbitrary order. 2. The signal angle adjusting method according to claim 1, wherein the signal is a color difference signal of a digital video signal, and the predetermined angle θk is one of +45 degrees and −45 degrees. . 3. An apparatus for adjusting a signal angle of a signal represented by two orthogonal signal components, a first phase shifting means for shifting an input signal by a predetermined angle θk, and an angle to be changed being θ. When the input signal is [-θk
+ Θ], wherein the first phase shifter and the second phase shifter are connected in series in an arbitrary order. 4. The signal angle adjusting device according to claim 3, wherein the signal is a color difference signal of a digital video signal, and the predetermined angle θk is one of +45 degrees and −45 degrees. .