JPH11261072A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can be enhanced in speed operation and lessened in power consumption at the same time. SOLUTION: SOI layers 6 and 7 are formed on a silicon single crystal substrate 1 through silicon oxide films 3 and 5 to constitute MOSFETs 20 and 21. The MOSFETs 20 and 21 are turned to a complete depletion mode in a circuit operation where the MOSFETs 20 and 21 are repeatedly turned ON or OFF, and the SOI layers 6 and 7 are turned to be fully depleted in the thickness direction of the films. The MOSFETs 20 and 21 are turned to a partial depletion mode in a circuit standby where the MOSFETs 20 and 21 are kept in an ON state or an OFF state, and there exist regions which are not depleted in the thickness direction in the SOI layers 6 and 7. A switch of a depletion mode is made by a voltage applied to a back gate electrode layer 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A thin-film SOI device in which a MOSFET is formed on a silicon layer (SOI layer) formed on a silicon substrate with an insulating film interposed therebetween has a high speed and low power consumption operation of an LSI due to its low parasitic capacitance and the like. Enable. In a thin film SOI device, when the MOSFET is on,
A fully depleted device in which a depletion layer is formed in the entire region in the thickness direction of the SOI layer serving as a channel, and a partially depleted device in which a depletion layer is not formed in the entire region in the thickness direction of the SOI layer and a neutral region exists. is there.

[0003] This will be described with reference to FIGS.
16 and 17 are schematic cross-sectional views of a thin-film SOI device. FIG. 16 shows a partially-depleted device, and FIG. 17 shows a fully-depleted device, when the MOSFET is on. 16 and 17, an SiO ₂ film 7 as an insulating film is formed on a silicon single crystal substrate 70 as a semiconductor substrate.
The SOI layer 72, which is a single crystal semiconductor layer, is formed via the first through-hole 1. The gate oxide film 7 is formed on the SOI layer 72.
3, a gate electrode 74 is formed, and SO
A source diffusion layer 75, a drain diffusion layer 76,
A channel forming region 77 is formed, and constitutes a MOSFET 80. Further, the gate electrode 74 and the source diffusion layer 7
5. Each of the drain diffusion layers 76 is connected to a wiring.

In FIG. 16, the thickness T of the SOI layer 72 is shown.
The SOI is larger than the maximum depletion layer width Xdmax, and the depletion layer 78 formed in the channel formation region 77 by the gate potential is not formed in the entire region of the SOI layer 72 but near the interface of the SOI layer 72 on the substrate 70 side. A neutral region 79 exists. The maximum depletion layer width Xdmax is expressed as follows. _{Xdmax = 2 (ε S · ε} O · φ B / (q · NA)) 1/2 ε S; specific dielectric constant in vacuum phi _B;; semiconductor dielectric constant epsilon _O Fermi potential q; charge of the electron On the other hand, in the fully depleted device shown in FIG.
The thickness TSOI of the OI layer 72 is smaller than the maximum depletion layer width Xdmax, and a depletion layer is formed in the entire region of the SOI layer 72.

As described above, in the fully depleted device, the kink phenomenon does not occur during operation which occurs in the partially depleted device, and the operation speed is higher than that of the partially depleted device due to the effect of reducing the vertical electric field. Operation becomes possible. On the other hand, the threshold voltage Vt of the fully depleted device is S
Although it depends on the thickness TSOI of the OI layer 72, the threshold voltage Vt of the partially depleted device becomes the same as that of the bulk MOSFET, and does not depend on the thickness TSOI of the SOI layer 72.

Therefore, in a fully depleted device,
SOI generated due to variations in the SOI substrate manufacturing process
The threshold voltage Vt varies due to the variation in the thickness TSOI of the layer 72. In a MOSFET in which the threshold voltage Vt has decreased due to the variation in the threshold voltage Vt, the leakage current when the MOSFET is off increases, which causes a problem that the power consumption of the LSI increases.

Japanese Unexamined Patent Publication No. 8-32068 discloses a technique for realizing high-speed operation and low leakage current of a transistor. However, in a thin-film SOI type MOSFET, since the SOI film thickness is small, this film is required in a manufacturing process. It is difficult to control the thickness, and the thickness tends to vary. As a result, the threshold voltage Vt varies. This causes a problem of increasing power consumption when the semiconductor integrated circuit device is turned off. On the other hand, in the partially depleted device, there is a problem that the operation speed is reduced when the semiconductor integrated circuit device operates.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit device which can achieve both high-speed operation and low power consumption.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a fully depleted mode in which a single crystal semiconductor layer in a channel formation region is completely depleted in a film thickness direction; The semiconductor layer has a partial depletion mode in which a region not depleted exists in the thickness direction, and the MOS
It is characterized in that the FET is set to a fully depleted mode during a circuit operation in which the FET repeatedly transitions between an ON state and an OFF state, and is set to a partially depleted mode during a circuit standby in which a MOSFET holds an ON state or an OFF state. I have.

Therefore, in the circuit operation in which the MOSFET repeats the transition between the ON state and the OFF state, the MOSFET is set to the complete depletion mode, and the single crystal semiconductor layer in the channel formation region is completely depleted in the film thickness direction. Further, in a circuit standby state where the MOSFET is kept on or off, a partial depletion mode is set, and there is a region in the single crystal semiconductor layer of the channel formation region which is not depleted in the thickness direction. As a result, it is possible to achieve both high-speed operation during circuit operation and low power consumption during circuit standby.

According to a second aspect of the present invention, a MOSF
A counter electrode is arranged in an insulator layer facing the channel formation region in the ET, and a depletion state in the thickness direction in the single crystal semiconductor layer in the channel formation region is controlled by a bias voltage applied to the counter electrode. Then, it becomes practically preferable.

Further, at least two potentials of a DC power supply potential and a ground potential lower than the DC power supply are supplied from outside the device, and the DC power supply potential and the ground are supplied as bias voltages. Setting to a potential is practically preferable.

According to a fourth aspect of the present invention, the MOSF
N-channel MOSFET and P-channel MO as ET
In the N-channel MOSFET, the bias voltage is changed in the negative direction at the time of circuit standby compared with the time of circuit operation, and the P-channel MOSFET is provided.
At T, it is practically preferable to change the bias voltage in the positive direction at the time of circuit standby compared to the time of circuit operation.

More specifically, as shown in FIG.
6 has the same MOSFET structure as that shown in FIG.
In the case of an nMOS, a non-depleted neutral region on the substrate 70 side of the channel forming region 77 (reference numeral 79 in FIG. 16) is applied to the substrate 70 by applying a positive potential equal to or more than a certain value with respect to the source potential. ) Can be depleted, so that a fully depleted device can be obtained. pMOS
Similarly, in the case of (1), the partial depletion type device can be made a fully depletion type device by applying a negative potential to the substrate with respect to the source potential.

As described above, the electrodes capable of setting the substrate potential independently of the nMOS and the pMOS are formed, and each of the MMOS and the pMOS is formed.
By temporally controlling the depletion state of the OSFET, the thin-film SOI-M
By switching the operation mode of the OSFET to a desired mode, both high-speed operation during circuit operation and low power consumption during circuit standby can be achieved.

According to a fifth aspect of the present invention, at least two potentials of a DC power supply potential and a ground potential lower than the DC power supply are supplied from outside the device. When the circuit is operating, it is set to the DC power supply potential, when the circuit is on standby, it is set to the ground potential. In the P-channel MOSFET, the bias voltage is set to the ground potential when the circuit is operating, and when the circuit is on standby, Setting to the DC power supply potential is practically preferable.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic sectional view of a semiconductor integrated circuit device according to the first embodiment. In FIG. 1, a polycrystalline silicon layer 2, a silicon oxide film (SiO ₂ film) 3, a back gate electrode layer 4, and a silicon oxide film (SiO ₂ film) 5 are formed on a silicon single crystal substrate 1 as a semiconductor substrate. , SOI layers 6 and 7 which are single crystal semiconductor layers are formed. That is, SOI is formed on the silicon single crystal substrate 1 through the silicon oxide films 3 and 5 as a buried insulating film (insulator layer).
While the I layers 6 and 7 are formed, a back gate electrode layer (counter electrode) 4 made of polycrystalline silicon is buried in the buried insulating films 3 and 5.

A gate electrode 9 is formed on the SOI layer 6 via a gate oxide film 8 as a gate insulating film, and a source diffusion layer (source region) 10 and a drain diffusion layer (Drain region) 11 is formed. Further, the source diffusion layer 10 in the SOI layer 6
A channel forming region 12 is provided between the
Are formed. Thus, the N-channel MOSF
An ET (nMOS) 20 is configured. Similarly, SO
On the I layer 7, a gate oxide film 13 as a gate insulating film
The gate electrode 14 is formed via
In the layer 7, a source diffusion layer (source region) 15 and a drain diffusion layer (drain region) 16 are formed. further,
Source diffusion layer 15 and drain diffusion layer 16 in SOI layer 7
A channel forming region 17 is formed between the two. Thus, the N-channel MOSFET (nMOS) 21
Is configured. The gate electrodes 9 and 14, the source diffusion layers 10 and 15, and the drain diffusion layers 11 and 16 are respectively connected to wirings.

The back gate electrode layer 4 is formed of a silicon oxide film 5
Is connected to wiring via a contact hole 18 opened in a part of the wiring. Then, a DC power supply potential Vdd and a ground potential (G
ND potential) can be selectively supplied. At this supply potential, the DC power supply potential V
dd or a ground potential (GND potential) can be set.

In FIG. 1, interlayer insulating films and aluminum electrodes formed on the SOI layers 6, 7 and the gate electrodes 9, 14 are omitted. Further, the silicon single crystal substrate 1 is wired to a ground potential (GND).

Here, boron is added as a P-type impurity to the channel forming regions 12 and ^{17 at a} concentration NA of, for example, 5 × 10 ¹⁵ to 2 × 10 ¹⁷ cm ⁻³ .
Assuming that the maximum depletion layer width at the channel concentration is Xdmax, the film thickness TSOI of the SOI layers 6 and 7 is Xdmax <TSOI <2X
It is set in the range of dmax. This MOSFET 20,
Reference numeral 21 denotes a partial depletion mode in which, when the back gate electrode layer 4 is at the ground potential (GND potential), the SOI layers 6 and 7 of the channel formation regions 12 and 17 have regions that are not depleted in the film thickness direction. In MOS
FETs 20 and 21 are partially depleted devices (hereinafter Parti
ally depleted type device. D.). In addition, the back gate electrode layer 4
When a positive potential exceeding “a certain value” is applied, as shown in FIG.
The layers 6 and 7 are completely depleted in the film thickness direction. In this mode, the MOSFETs 20 and 21 are depleted.
Is a fully depleted device
Device is abbreviated to F. D. Function).

The "certain value" applied to the back gate electrode layer 4 is determined by NA, TSOI, and the thickness of the silicon oxide film 5 between the SOI layers 6 and 7 and the back gate electrode layer 4. The smaller the thickness of the TSOI and the thickness of the silicon oxide film 5, the smaller the value. In the present embodiment, each film thickness and concentration are set so that “a certain value” becomes a value smaller than the power supply voltage Vdd of the positive polarity, and as shown by the nMOS in FIG. If the power supply voltage Vdd is applied to D. It is possible to be.

FIG. 3 shows the V of both nMOS and pMOS.
7 schematically shows the dependency of the back gate voltage VBG on t. Points indicated by ● in FIG. 3 correspond to states used in the present embodiment and a second embodiment described later.

Now, referring to FIG.
When the circuit composed of 0 and 21 is in a standby state due to the circuit function,
In other words, the partial depletion mode is set when the circuit is in a standby state in which the MOSFETs 20 and 21 are kept on or off. In this mode, the back gate electrode layer 4 is set to the ground potential (GND potential). At this time,
Since the MOSFETs 20 and 21 do not perform the on / off operation while maintaining the on or off state, the MOSFE
The operation speed of T20 and T21 does not affect the circuit operation.
On the other hand, the current consumption in this circuit at this time is MOSFET
Is controlled by the off-state currents of the MOS transistors 20 and 21.
It depends on the threshold voltage Vt of the FETs 20 and 21. In this state, MOSFETs 20 and 21 are connected to P.O. D. , The threshold voltage Vt is equal to the film thickness T of the SOI layers 6 and 7.
It is the same as the bulk type MOSFET without being affected by the variation in SOI, the increase in the leakage current when the MOSFETs 20 and 21 are off is suppressed, and the power consumption is reduced.

On the other hand, referring to FIG.
When the circuit composed of 0 and 21 is in an operating state in terms of the circuit function,
That is, in the circuit operation in which the MOSFETs 20 and 21 repeat the transition between the ON state and the OFF state, the complete depletion mode is set. In this mode, the back gate electrode layer 4
Are set to the power supply potential Vdd. At this time, MOSFET2
0, 21 repeats the ON or OFF state, and MOSFE
The operation speed of T20 and T21 affects the circuit operation. In this state, MOSFETs 20 and 21 are connected to F.C. D. Therefore, high-speed operation can be realized. MOSF
In the operation of the ETs 20 and 21, the power consumption mainly depends on the parasitic capacitance and the operating frequency, so that the influence of the Vt variation is not so large.

The operating speed is also affected by Vt.
As shown in (2), the Vt value itself changes depending on the potential VBG of the back gate electrode layer 4. In the nMOS, when a positive potential is applied to the source, the Vt value decreases. High-speed operation can be realized.

In FIG. 3, the back gate electrode layer 4
The potential (VBG) of the nMOS and pMOS is based on the potential of the source in both of the nMOS and the pMOS.
= GND, the source is effectively biased to a negative potential with respect to the source.

Next, a method of manufacturing the semiconductor integrated circuit device thus configured will be described. 4 to 11 are schematic cross-sectional views of a main part showing a manufacturing process of the structure shown in FIG. 1. Hereinafter, an example of a manufacturing method of the present structure will be briefly described with reference to FIGS.

First, as shown in FIG. 4, a silicon single crystal substrate 30 is prepared, and from the surface of the silicon single crystal substrate 30, only the region where a thin film SOI device will be formed in the future is left, and other regions are subjected to dry etching or the like. To form a step 31 as shown in FIG.

Then, as shown in FIG. 5, a silicon oxide film (SiO ₂ film) 5 as an insulating film is formed by, for example, thermally oxidizing the substrate surface. Further, as shown in FIG. 6, for example, polycrystalline silicon serving as a back gate electrode is deposited on the entire surface by a CVD method, and is further patterned by photolithography and dry etching so that only a desired region is left. To form

Subsequently, as shown in FIG. 7, a silicon oxide film (SiO ₂ film) 3 as an insulating film is deposited on the entire surface by, for example, a CVD method, and the silicon oxide films 3 and 5 are formed around the back gate electrode layer 4. Cover with. These silicon oxide films 3 and 5 become buried insulating films.

Then, as shown in FIG. 8, in order to form a flat surface for wafer bonding, a relatively thick polycrystalline silicon film 2 is deposited over the entire surface by, for example, a CVD method, and then the surface is polished. To flatten the surface.

Further, as shown in FIG. 9, another silicon single crystal substrate 1 is prepared, and the flat surface of this silicon single crystal substrate 1 and the above-mentioned flat surface of the polycrystalline silicon film 2 are bonded together.

Subsequently, as shown in FIG. 10 (FIG. 10 is drawn upside down), the silicon single crystal substrate 30 is polished from the back surface, and stops when the silicon oxide film 5 is exposed. Thereby, thin SOI layers 6 and 7 are formed.

Thereafter, as shown in FIG. 11, the MOSI is formed on the SOI layers 6 and 7 by a normal MOSFET manufacturing process.
In addition to forming the FETs 20 and 21, a contact hole 18 is formed for wiring the back gate electrode layer 4. Further, wiring and the like are performed. As a result, the structure shown in FIG. 1 is obtained.

As described above, according to the present embodiment, in the same MOSFETs 20 and 21, two operation modes are temporally switched according to the back gate voltage in response to the circuit standby mode and the operation mode.
20, 21 as P.E. D. And F. D. As P. D. And F. D. By utilizing the features of (1), it is possible to realize an LSI that achieves both high speed and low power consumption.

More specifically, in a circuit operation in which the MOSFETs 20 and 21 repeat transitions between an on state and an off state, at least when the MOSFETs 20 and 21 are turned on (the gate electrodes 9 and 14 have the same polarity as the threshold voltage Vt and have an absolute value). When a large voltage is applied, the depletion mode is set, and at the time of standby of a circuit in which the MOSFETs 20 and 21 are kept on or off, at least when the MOSFETs 20 and 21 are on (the gate electrode 9). , 14 are set to the partial depletion mode when a voltage having the same polarity as the threshold voltage Vt and a large absolute value is applied.

As described above, this embodiment has the following features. (A) Complete depletion mode in which the SOI layers 6 and 7 in the channel formation regions 12 and 17 are completely depleted in the film thickness direction, and no depletion in the film thickness direction in the SOI layers 6 and 7 in the channel formation regions 12 and 17 It has a partial depletion mode in which a region exists, and sets the MOSFETs 20 and 21 to a complete depletion mode during a circuit operation in which the MOSFETs 20 and 21 repeatedly transition between an on state and an off state, and holds the MOSFETs 20 and 21 in an on state or an off state. Changed to partial depletion mode during circuit standby. As a result, it is possible to achieve both high-speed operation during circuit operation and low power consumption during circuit standby. (B) Insulator layers (silicon oxide films 3, 3) facing the channel formation regions 12, 17 in the MOSFETs 20, 21
The back gate electrode layer 4 as a counter electrode is disposed in 5), and depletion in the thickness direction in the SOI layers 6 and 7 in the channel formation regions 12 and 17 is performed by a bias voltage applied to the electrode layer 4. Because I controlled the state,
This is practically preferable. (C) At least two potentials of a DC power supply potential Vdd and a ground potential (GND potential) lower than the DC power supply Vdd are supplied from outside the device, and the DC power supply potential Vdd and the ground potential (GND potential) are supplied as bias voltages. ), Which is practically preferable.

An application example of this embodiment will be described below. In the above description, the nMOS is described. However, the same effect can be obtained for the pMOS by inverting the polarity.

That is, as shown in FIG. 18, even if the MOSFET structure is the same as that shown in FIG.
In the case of S, a positive potential equal to or more than a certain value with respect to the source potential is applied to the substrate, so that the channel forming region 7 is formed.
The non-depleted neutral region (reference numeral 79 in FIG. 16) on the substrate 70 side of No. 7 can be depleted. Thus, a fully depleted device can be obtained. Also, p
Similarly, in the case of MOS, a partially depleted device can be made a fully depleted device by applying a negative potential to the substrate with respect to the source potential.

As described above, the electrodes capable of setting the substrate potential of the nMOS and the pMOS independently of each other are formed.
As shown in (1), by controlling the depletion state of each MOSFET temporally, the operation mode of the thin-film SOI-MOSFET during circuit operation and circuit standby is switched to a desired mode, thereby achieving high-speed operation and low power consumption. Can be compatible.

In FIG. 1, two nMOSs are simultaneously controlled by the common back gate electrode (4).
A back gate electrode may be provided for each ET. Still further, a common back gate electrode may be provided for many MOSFETs.

Further, in the above description, the ground potential (GND potential) or the Vdd potential is directly applied as the bias voltage applied to the back gate electrode (4), but the characteristics of the thin film SOI-MOSFET are optimized. As such a bias voltage, any positive or negative voltage other than the ground potential (GND potential) or the Vdd potential may be applied. The bias voltage at this time may be supplied from a power supply circuit configured inside the LSI or from outside the LSI.

The bias voltage to be applied is also
It is not necessary to limit the value to two different levels, but to change the value into three or more levels in accordance with the operation speed required for the circuit function, and to change the mode (PD and FD) in one of the levels. May be performed.

Further, the structure shown in FIG. 12 may be used instead of FIG. In the structure shown in FIG. 1 and the structure shown in FIG. 12, the flatness of each part such as whether the surface of the buried insulating film 35 as an insulator layer is flat, and the flat There is a difference in the presence or absence of the polycrystalline silicon layer 2 for forming the layer, but these are differences caused by the manufacturing method and do not affect the functions described so far.

FIG. 13 is a diagram corresponding to FIG.
FIG. 3 is a schematic cross-sectional structure diagram when an FET (circuit) is in an operating state. (Second Embodiment) Next, a second embodiment will be described with reference to FIG.
This will be described with reference to FIGS.

FIGS. 14 and 15 are schematic cross-sectional views of a semiconductor integrated circuit device comprising a CMOS with nMOS and pMOS. SOI layer 4 on substrate 1 via insulator layer 35
0, 41 and SOI layers 42, 43 are formed.
N-channel MOSFET (nMOS) in layers 40 and 41
44 and 45 are formed, and the SOI layers 42 and 43 are formed.
, P-channel MOSFETs (pMOS) 46 and 47 are formed.

In the insulator layer 35 under the SOI layers 40 and 41, a back gate electrode layer 4a is arranged and
The back gate electrode layer 4b is disposed in the insulator layer 35 below the OI layers 42 and 43. That is, nMOS and p
In MOS, P.I. D. To F. D. In order to reverse the polarity of the voltage to be applied, the common back gate electrode layers 4a and 4b are provided independently for the nMOS and the pMOS as shown in FIGS.

FIG. 14 shows a state in which this circuit is in a standby state, and is set to the partial depletion mode. In this mode, the ground potential (GND potential) is applied to the back gate electrode layer 4a corresponding to the nMOS, and the Vdd potential is applied to the back gate electrode layer 4b corresponding to the pMOS.
Therefore, both nMOS and pMOS have a P.I. D. Becomes At this time, the absolute value of the threshold voltage Vt increases as shown in FIG. D. Therefore, the variation becomes small, and the off-state current of the MOSFET which controls the current consumption can be suppressed low.

FIG. 15 shows a state in which the present circuit operates, and is set to a complete depletion mode. In this mode, the Vdd potential is applied to the back gate electrode layer 4a corresponding to the nMOS and the back gate electrode layer 4a corresponding to the pMOS.
A ground potential (GND potential) is applied to b.
Therefore, both nMOS and pMOS have the F.F. D. Becomes At this time, as shown in FIG. 3, the absolute value of the threshold voltage Vt decreases, and D. Thus, the operation speed is improved.

As described above, this embodiment has the following features. (B) N-channel MOSFET 4
4, 45 and P-channel MOSFETs 46, 47. In the N-channel MOSFETs 44, 45, the bias voltage is changed in the negative direction (switching from Vdd to the GND potential) when the circuit is in standby compared to when the circuit is operating. In the MOSFETs 46 and 47, the bias voltage is changed in the positive direction (switching from the GND potential to Vdd) at the time of circuit standby during circuit operation, which is practically preferable. (B) More specifically, the DC power supply potential V
dd and a ground potential (GND) lower than the DC power supply Vdd.
Potential) and at least two potentials
In the OSFETs 44 and 45, the bias voltage is set to the DC power supply potential Vdd during circuit operation, and to the ground potential during circuit standby, and the P-channel MOSFETs 46 and 4
In 7, the bias voltage is set to the ground potential during circuit operation, and is set to the DC power supply potential Vdd during circuit standby, which is practically preferable.

In this embodiment, nMOS,
Although the back gate voltage is changed for both pMOSs, a back gate electrode may be provided for only one of the pMOSs to apply the voltage. Even if only one MOSFET applies a bias voltage at the same time, two or more M
It may be an OSFET. Further, as in the first embodiment, a ground potential (GND potential) or a potential different from the Vdd potential may be applied as a bias voltage applied to the back gate electrode.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor integrated circuit device according to a first embodiment when a MOSFET is in a circuit standby state;

FIG. 2 is a schematic cross-sectional structure diagram when a MOSFET is in an operating state on a circuit.

FIG. 3 is a diagram schematically showing the back gate voltage dependency of Vt.

FIG. 4 is a cross-sectional view for explaining a manufacturing process.

FIG. 5 is a cross-sectional view for explaining a manufacturing process.

FIG. 6 is a cross-sectional view for explaining a manufacturing process.

FIG. 7 is a cross-sectional view for explaining a manufacturing process.

FIG. 8 is a cross-sectional view for explaining a manufacturing process.

FIG. 9 is a cross-sectional view for explaining a manufacturing process.

FIG. 10 is a sectional view for explaining a manufacturing process.

FIG. 11 is a sectional view for explaining a manufacturing process.

FIG. 12 is a schematic cross-sectional view of a semiconductor integrated circuit device in an application example during standby.

FIG. 13 is a schematic cross-sectional structure diagram corresponding to a state where the semiconductor integrated circuit device is in an operating state.

FIG. 14 is a schematic cross-sectional view of the semiconductor integrated circuit device according to the second embodiment during standby.

FIG. 15 is a schematic sectional view corresponding to a state where the semiconductor integrated circuit device is in an operating state.

FIG. 16 is a schematic sectional view of a thin-film SOI device.

FIG. 17 is a schematic sectional view of a thin-film SOI device.

FIG. 18 is a schematic cross-sectional view of a thin-film SOI device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon single crystal substrate, 2 ... Polycrystalline silicon layer, 3 ...
Silicon oxide film, 4 back gate electrode layer, 5 silicon oxide film, 6 SOI layer, 7 SOI layer, 8 gate oxide film, 9 gate electrode, 10 source diffusion layer, 11 drain diffusion layer, 12 channel forming region, 13 gate oxide film, 14 gate electrode, 15 source diffusion layer, 16
... Drain diffusion layer, 17 ... Channel formation region, 20 ... N
Channel MOSFET, 21 ... N-channel MOSFET
T, 44: N-channel MOSFET, 45: N-channel MOSFET, 46: P-channel MOSFET, 47:
P-channel MOSFET

Claims (5)

[Claims] A single crystal semiconductor layer formed over a semiconductor substrate via an insulator layer; a gate electrode formed over the single crystal semiconductor layer via a gate insulating film; MOSFET having formed source and drain regions, and a channel formation region between the source region and the drain region in the single crystal semiconductor layer
A complete depletion mode in which the single crystal semiconductor layer in the channel formation region is completely depleted in the thickness direction, and depletion in the thickness direction in the single crystal semiconductor layer in the channel formation region. A partial depletion mode in which a region does not exist, and the MOSFET is set to the full depletion mode during a circuit operation in which the MOSFET repeatedly transitions between an on state and an off state;
2. A semiconductor integrated circuit device according to claim 1, wherein said partial depletion mode is set when said circuit is in a standby state in which said MOSFET is kept on or off. A counter electrode disposed in the insulator layer facing the channel formation region in the MOSFET, and a film thickness in the single crystal semiconductor layer in the channel formation region is adjusted by a bias voltage applied to the counter electrode. 2. The semiconductor integrated circuit device according to claim 1, wherein a state of depletion in a direction is controlled. 3. A method in which at least two potentials of a DC power supply potential and a ground potential lower than the DC power supply are supplied from outside the device, and the bias voltage is set to the DC power supply potential and the ground potential. Claim 2
3. The semiconductor integrated circuit device according to 1. 4. An N-channel MOSFET as the MOSFET.
An OSFET and a P-channel MOSFET are provided. In the N-channel MOSFET, the bias voltage is changed in a negative direction when the circuit is in standby for the circuit operation, and in the P-channel MOSFET, the circuit is in standby for the circuit operation. 3. The semiconductor integrated circuit device according to claim 2, wherein the bias voltage is sometimes changed in a positive direction. 5. At least two potentials, a DC power supply potential and a ground potential lower than the DC power supply, are supplied from outside the device.
The bias voltage is set to the DC power supply potential during a circuit operation, is set to the ground potential during a circuit standby, and the bias voltage is set at the P-channel MOSFET during the circuit operation. 5. The semiconductor integrated circuit device according to claim 4, wherein the potential is set to the DC power supply potential when the circuit is on standby.