JPH11259408A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system which can easily and flexibly change the setting of peripheral equipment. SOLUTION: A buffer 50 provided with tristate buffers T1 -T3 is arranged between data transmission lines L1 -L3 and the respective terminals of CK, DT and DONE. At the time of rewriting the setting content of FPGA (rewritable logic circuit) 40, data input terminals PF1 -PF3 and the inner circuit of FPGA 40 are interrupted with a setting start signal SPR supplied from a setting start signal line L5 as a trigger. The buffer 50 is set to be the input means of a rewriting data signal SDT transmitted from CPU10 through a part of the data transmission lines L1 -L3 by setting a rewriting control signal SCT supplied from the DONE terminal to be L. When the supply of the rewriting data signal SDT terminates, the data input terminals PF1 -PF3 and the above inner circuit come to conduction state. Then, the buffer 50 becomes a high impedance element with the rewriting control signal SCT set to H.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to a computer system capable of flexibly changing the functions of peripheral devices from the main unit.

[0002]

2. Description of the Related Art In recent computer systems, a rewritable logic circuit (FPGA: Field) is provided so that a user can quickly and flexibly set and change the contents of a logic circuit.
Pro-grammable gate arrays are already mounted on peripheral devices in advance.

Conventionally, there are two methods for changing the contents of the FPGA.

[0004] One method is to take rewrite data, which is the content of the setting change, into a new ROM, replace the ROM already mounted on the peripheral device with this new ROM, and then switch on the FPGA from the new ROM when the power is turned on. The rewrite data is transferred to the server and the contents are changed.

However, according to this method, the change of the setting of the FPGA is limited only when the power is turned on. In addition, even when a slight change in the contents is required, the process must be interrupted and the ROM must be replaced. The operation is very complicated. Furthermore, if a ROM in which desired rewrite data is recorded cannot be obtained, there is a problem that the setting cannot be changed.

As another method, there is a method of connecting the computer main body and the peripheral device FPGA with a dedicated setting line, transmitting desired rewrite data, and changing the contents.

A method of changing the setting of the FPGA using the dedicated setting line will be described with reference to the drawings.

FIG. 4 is a schematic diagram showing an example of a conventional computer system. A computer system 60 shown in FIG. 1 includes an input device such as a keyboard, etc., and controls a CPU 10 that controls the entire system.
And a peripheral device 70 having 0.

The CPU 40 and the FPGA 40 of the peripheral device 70
And it is connected by a plurality of signal lines L ₁ ~L _8.

The signal lines L _{1 to} L ₄ are connected to the terminal P _{c1 of} the CPU 10.
Connected to P _c4 and FPGA40 data input terminal and a P _F1 to P _F4 respectively, a data transmission line for transmitting the normal data signal to be logic operation, also the signal lines L ₅ ~
L ₈ is, of CPU10 and FPGA40 PROG, CK,
Connect to each input terminal of DT and DONE, FPGA
This is a setting line provided exclusively for changing the settings of 40.

[0011] Among them, a signal line L ₅ represents setting start signal line, and transmits a setting start signal for starting the configuration change from CPU 10 FPGA 40, FPGA 40 of PRO
Supply to G terminal. The signal line L ₆ transmits a set clock signal for controlling the operation timing of each gate array at the time of rewriting, and supplies it to the CK terminal of the FPGA 40. The signal line L ₇ is a rewritable data transmission line for supplying the DT terminal of FPGA40 by transmitting a rewrite data signal is a configuration changes, further, the signal line L _8, when the setting change is completed The FPGA 40 transmits a setting end signal to the CPU 10 from the DONE terminal.

The data transmission lines L _{1 to} L ₄ and the setting line L ₅
~L ₈ constitute a cable C _3, C ₂ are respectively integrated.

[0013] In a computer system 60 having the above structure, When changing the settings of the FPGA 40, first, the setting start signal via a setting line L ₅ FP
After supplying the PROG terminal of GA40, while supplying to the CK terminal through the signal line L ₆ setting clock signal, FPGA desired rewrite data signal by rewriting the data transmission line L ₇
Supply to 40 DT terminals. When the setting change of the FPGA 40 is completed in response to the rewrite data signal, the FPGA 40
Supplied to the CPU10 via the signal line L ₈ the setting end signal.

Thereafter, normal data is transferred to the data input terminals P _F1 to P _F1 of the FPGA ₄₀ via the data transmission lines L _{1 to} L _4.
Supplied to the P _F4.

According to this method, there is an advantage that the settings of the FPGA 40 can be changed to desired contents as needed.

[0016]

[SUMMARY OF THE INVENTION However, as shown in FIG. 4, in addition to the existing data transmission line L ₁ ~L _4, F
To connect the dedicated line L ₅ ~L ₈ 4 pieces of for configuration changes PGA40 is not only very complicated, space is newly required for providing these dedicated line, made in the data transmission line other cable C _3, since it is necessary to prepare the cable C ₂ only for FPGA configuration on the space occupied by the entire system becomes large, the reliability of the connection is reduced by that amount, there is a problem that.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a computer system capable of easily and flexibly changing settings of peripheral devices.

[0018]

The present invention solves the above problems by the following means.

That is, according to the present invention (claim 1), the CP
U, a rewritable logic circuit, and data to be subjected to a logical operation supplied from the CPU, and a part thereof is used as a rewrite data transmission line for transmitting rewrite data for rewriting the logic circuit. A data transmission line, disposed between the data transmission line and the logic circuit, and when receiving the supply of the rewrite data, serves as an input means of the logic circuit;
When the supply of the rewrite data ends, a computer system including a tri-state buffer serving as a high impedance element is provided.

The computer system may further include a setting start signal line for transmitting a setting start signal for controlling the start of rewriting of the logic circuit. The logic circuit receives the setting start signal and becomes high to receive the setting data. It is preferable to supply a rewrite control signal which becomes low upon completion of the supply to the control terminal of the tri-state buffer.

Further, it is preferable that the data transmission line and the setting start signal line form an integrated cable.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a data transmission line is not used while the setting of a logic circuit is being changed, and a dedicated line is not used after the setting change is completed. Focusing on the point, a feature is that a part of the data transmission line is shared as a setting line.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following figures, FIG.
The same parts as those described above are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 1 is a schematic diagram showing one embodiment of a computer system according to the present invention.

The computer system 1 shown in FIG.
A PU 10 and a peripheral device 20 are provided. The CPU 10 and the peripheral device 20 are connected to four data transmission lines L _{1 to} L ₄ ,
Are connected by setting start signal line L ₅ which is a dedicated line of the present, these five signal lines constitute a single cable C _1.

The peripheral device 20 includes an FPGA 40 and a buffer 50 characteristic of the present invention.

The buffer 50 has three tri-state buffers T ₁ , T ₂ and T ₃ . The input terminal of the tristate buffer T ₁ is connected to the data transmission line L ₁ , and the output terminal is connected to the CK terminal of the FPGA 40. Similarly, the input terminal of the tri-state buffer T ₂ is connected to the data transmission line L ₂ , and the output terminal is connected to the DT terminal of the FPGA 40. The tri-state buffer T ₃ has an output terminal connected to the data transmission line L ₃ and an input terminal connected to the DONE terminal of the FPGA 40. The control terminals of the _three tri-state buffers T ₁ , T ₂ and T ₃ are all connected to an inverting input terminal Pr via a control line L _C2 , and the inverting input terminal Pr is connected to the DONE of the FPGA 40 via a control line L _c1. Connected to terminal.

The buffer 50 operates as a buffer amplifier for shaping the signal waveform of the rewrite data supplied from the CPU 10, and the CK, DT and DO of the FPGA 40.
It operates as input control means for rewriting data with the NE terminal.

The operation of the buffer 50 will be described with reference to FIG.

FIG. 3 is a waveform diagram of signals output from the CPU 10 and the FPGA 40 when the setting of the FPGA 40 is changed. 3 (a) is an example waveform diagram of the rewrite data signals S _DT outputted from the CPU10 of the terminal P _C2,
FIG. 3B shows a state in which the DONE terminal of the FPGA 40 is connected to the CPU.
10 is a waveform diagram of the rewrite control signal S _CT to be output to the terminal P _C3 of, also, FIG. 3 (c) is a setting start signal S _PR outputted from the CPU10 of the terminal P _C5.

First, at time t ₀ , the setting start signal S _PR is L and the rewrite control signal S _CT supplied to the inverting input terminal Pr is H, so that the tristate buffer T
Signals supplied to the respective control terminals of ₁ through T ₃ is L, and the buffer 50 are cut off as a result become a high-impedance element. As a result, when the CPU 10 outputs the normal data to be subjected to the logical operation, the normal data is supplied to the terminals P _{F1 to} P _F3 of the FPGA 40.

Next, at time t ₁ , the setting start signal S
If _PR is H from L, L next to rewrite the control signal S _CT from H to be supplied to the inverting input terminal Pr, signal H is input to the control terminal of the tristate buffer T ₁ through T _3. As a result, the buffer 50 becomes conductive,
CPU10 of the terminal P _C1 ~P _C3, respectively FPGA40
CK, DT and DONE. At this time, the FPGA 40 is connected to the data input terminal P
Interrupting the connection between the internal circuit (not shown) and _F1 to P _F3. Accordingly, from time t ₂ to time t _n, with the configuration clock signal S _CK from CPU10 of the terminal P _C1 is supplied to the CK terminal of the FPGA 40, the rewrite data signals S _DT is FPGA 40 DT terminal from CPU10 of the terminal P _C2 Supplied to

[0033] Thereafter, the supply of rewrite data signals S _DT at time t _n has been completed, at time t _{n + 1,} H next to the rewrite control signal S _CT is L supplied to the inverting input terminal Pr,
The signals input to the control terminals of the tristate buffers T _{1 to} T _{3 change} from H to L. At this time, FPG
A40 makes the data input terminals P _{F1 to} P _F3 conductive with the above-mentioned not-shown internal circuit. Thereby, the CPU 10
Terminals P _{C1 to} P _C3 to the data input terminals P of the FPGA 40
Normal data will be able to supply to the _F1 to P _F3. The operation of the entire computer system 1 having such a buffer 50 will be described with reference to the flowchart of FIG.

First, the power is turned on (step S10).
In the initial state immediately after 0), the rewrite control signal S _CT is set to be H, and the potential of the internal control line L _C2 is set to L by the inverting input terminal Pr. Therefore, the outputs of the tri-state buffers T _{1 to} T ₃ are all shut off, and the terminals P _{C1 to} P _C3 of the CPU 10 are in a state where normal data can be transmitted to the data input terminals P _{F1 to} P _F3 of the FPGA 40 ( Step S110).

Therefore, the setting start signal S _{PR is} sent from the CPU 10.
Is not output (step S120), the CPU 10 outputs normal data from the data input terminals P _{F1 to} P _{F1 of the} FPGA 40.
It is supplied to _F3 (step S200).

When changing the setting of the FPGA 40,
Setting start signal PROG terminal of FPGA40 via the setting start line L ₅ from CPU 10 S _PR is input (step S120), with FPGA40 is defined as L the rewrite control signal S _CT from H this as a trigger, the data input terminal The connection between P _{F1 to} P _F3 and an internal circuit (not shown) is cut off (step S130). As a result, all of the tri-state buffers T _{1 to} T ₃ of the buffer 50 become conductive, and the terminals PC ₁ to PC _{3 of the} CPU 10
K, is ready to transmit a respective signal to the terminals of DT and DONE (step S140), it sets the CPU10 of the terminal P _C1 clock signal S _CK data transmission line L ₁
The signal is supplied to the CK input terminal of the FPGA 40 via the buffer 50. Thereby, the operation timing of each gate array of the FPGA 40 is controlled.

Further, setting the clock signal S rewrite data signal synchronized with the _CK S _DT is FPGA40 via the data transmission line L ₂ and the buffer 50 from the CPU10 of P _C2 terminal D
Supplied to the T input terminal (step S150),
The arrangement and wiring in 40 are changed.

[0038] When the supply of the rewrite data signal S _DT is finished,
The FPGA 40 changes the rewrite control signal S _CT from L to H (step S160). As a result, all the tri-state buffers T _{1 to} T ₃ enter the cutoff state (step S
170). At the same time, the FPGA 40 has a data input terminal P _F1
And an internal circuit and to P _F3 not shown in a conductive state. Therefore, the terminals P _{C1 to} P _C3 of the CPU 10 are connected to the data signal lines L ₁ to L ₁ .
Through L ₃ it is ready to supply the normal data to the data input terminal P _F1 to P _F3 of FPGA 40 (step S20
0).

The above steps S120 to S200 are repeated until a command to end the program is output from the CPU 10 (step S210).

As described above, in the computer system 1 according to the present embodiment, the buffer 50 for shaping the signal waveform is used.
Is also used as input control means for rewriting data, so that among the data transmission lines L _{1 to} L ₄ , L _{1 to} L ₃ among the data transmission lines L _{1 to} L ₄ can be set to change the setting of the FPGA ₄₀ without adding a switching circuit such as a multiplexer. Can be used as part of a line.

[0041] Thus, by simply adding one dedicated line L ₅ of transmitting a setting start signal S _PR to the data transmission line L ₁ ~L _4, and facilitate FPGA40 settings in the peripheral device 20 from the CPU 10, flexible Can be changed to

Further, since the data transmission lines L _{1 to} L ₄ and the setting start signal line L ₅ are integrated into one cable C ₁ , the space occupied by the entire system can be reduced and the connection can be reduced. Reliability is improved.

Incidentally, since setting start signal line L ₅ represents, that when the FPGA 40 except when the setting change is operating, the other data is transmitted, there is a risk of accidentally changing the setting of the FPGA 40, It cannot be shared with other signal lines.

In the description of the above embodiment, four data transmission lines are used for the sake of simplicity. However, the present invention is not limited to this. The rewrite data signal _SDT , the set clock signal _SCK, and the rewrite control signal can be three or more data transmission lines three signals can be transmitted each S _CT to the present invention, if any.

[0045]

As described in detail above, the present invention has the following effects.

That is, according to the computer system of the present invention, a tri-state buffer is provided as an input means of a logic circuit when supplied with rewrite data, and becomes a high impedance element when supply of rewrite data is completed. Therefore, a part of the data transmission line can be shared as a rewrite data transmission line. Therefore, there is provided a computer system capable of flexibly changing the settings of peripheral devices with a simple configuration in which one dedicated line is added to an existing data transmission line.

Further, since there is no need to provide a cable composed of only a dedicated line in addition to a cable composed of a data transmission line or the like, the occupied area of the entire system can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an embodiment of a computer system according to the present invention.

FIG. 2 is a flowchart illustrating an operation of the computer system shown in FIG.

FIG. 3 illustrates a CPU and an FP when changing settings of an FPGA;
FIG. 3 is a waveform diagram of a signal output from a GA. That is, FIG.
FIG. 3A is a waveform diagram of an example of rewrite data supplied from the CPU, and FIG.
FIG. 3 is a waveform diagram of a rewrite control signal output to
(C) is a setting start signal output from the CPU.

FIG. 4 is a schematic diagram showing an example of a computer system according to the related art.

[Explanation of symbols]

1,60 computer system 10 CPU 20, 70 peripheral 40 FPGA 50 buffer C ₁ -C ₃ cable L ₁ ~L ₄ data transmission lines L _C1, L _C2 control line L ₅ set start signal line L ₆ ~L ₈ setting line P _{F1 to} P _F4 data input terminals S _CK setting clock signal S _CT rewriting control signal S _DT rewriting data signal S _PR setting start signal T _{1 to} T ₃ tristate buffer

Claims (3)

[Claims] 1. A CPU, a rewritable logic circuit, and rewrite data transmission for transmitting data to be subjected to a logical operation supplied from the CPU, and partially transmitting rewrite data for rewriting the logic circuit A data transmission line used as a line, disposed between the data transmission line and the logic circuit, and when receiving the supply of the rewrite data, serves as an input means of the logic circuit, and the supply of the rewrite data ends. When you do
A computer system including a tri-state buffer serving as a high impedance element. 2. The apparatus according to claim 1, further comprising a setting start signal line for transmitting a setting start signal for controlling a start of rewriting of said logic circuit, wherein said logic circuit receives said setting start signal and becomes high to end supply of said rewriting data. The computer system according to claim 1, wherein a rewrite control signal which becomes low by the control signal is supplied to a control terminal of the tri-state buffer. 3. The computer system according to claim 2, wherein said data transmission line and said setting start signal line form an integrated cable.