JPH11259379A - Fault processor for personal computer and personal computer processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the probability of server down by decreasing a fault generation rate as an entire server when two or more processors are constituted in one server. SOLUTION: Concerning a fault processor for personal computer(PC) provided with an intelligent processor 103 between the server and an input/output device, this processor is provided with an error detecting and holding means 104 for detecting the fault of the intelligent processor 103 and holding the data of a control line and a selecting means for selecting either the output of the intelligent processor 103 or the output of the server based on the data on the control line from the error detecting and holding means. Besides, the fault processor for PC has a system bus 107 between the server and the intelligent processor 103 and when any fault occurs at the intelligent processor 103, the intelligent processor 103 and the system bus 107 are isolated by a bus controller 102 for controlling the system bus 107.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal computer fault processing apparatus and a personal computer processing apparatus, and more particularly, to a personal computer fault processing apparatus which operates for a fault of an intelligent processor and a personal computer processing apparatus in a system related to the personal computer.

[0002]

2. Description of the Related Art Conventionally, in a personal computer server, to distribute and reduce the load on a central processing unit (CPU) of the server, an I ² O (Intelligent Input / Output: a standard between the OS and device driver software) is used. Interface standard). This I ² O specification
System bus (PCI bus: Peripheral Component Int)
A new processor (I ² O-compatible processor) is set under the erconnect Bus (input / output bus used for a personal computer or the like), and this processor executes processing such as interrupting, buffering, and data transfer for the input / output device. , The I / O throughput of the server is improved, and the CPU of the server can process more important tasks.

[0003] In particular, in recent years, I ² O has been developed for operating systems (OS).
system) and device driver software. One device driver software can be used with different OSs, and its use is increasing. Bridge LSI that connects PCI buses
Has been developed and a register set defined by I ² O,
The development according to the downsizing trend is progressing with a buffer for storing commands received from device driver software conforming to I ² O.

[0004]

However, in general, the I / O processing unit of the information processing apparatus is relatively susceptible to failure compared with other units such as an arithmetic unit and a memory unit, and has a certain degree of processing capability. The I ² O processor has a problem that it is also prone to failure.

[0005] Further, when two processors are configured in one server, the failure occurrence rate of the server as a whole increases, the probability of the server going down increases, and the operation of the personal computer system is remarkably hindered. There is.

[0006] An object of the present invention is to provide a personal computer fault handling apparatus which solves the above-mentioned problems.

[0007]

SUMMARY OF THE INVENTION The present invention achieves the above-mentioned object, and in a fault processing apparatus for a personal computer having an intelligent processor between a server and an input / output device, a fault of the intelligent processor is detected and controlled. Error detecting and holding means for holding line data; and selecting means for selecting an output of the intelligent processor and an output of the server based on data on a control line from the error detecting and holding means. And Further, in the fault processing device for a personal computer, a system bus is provided between the server and the intelligent processor, and the intelligent processor and the system bus are separated by a bus controller that controls the system bus when the intelligent processor fails. It is characterized by the following.

[0008] The present invention also provides a failure processing device for a personal computer comprising a server, a system bus connected to the server, and an intelligent processor connected to the system bus, wherein the failure of the intelligent processor is detected. Error detecting and holding means for holding the data of the control line, and selecting means for selecting the output of the intelligent processor and the output of the server based on the data on the control line from the error detecting and holding means. It is characterized by.

Further, the present invention relates to a personal computer processing apparatus comprising a server, a system bus connected to the server, and a plurality of intelligent processors connected to the system bus, wherein the server and / or the intelligent processor Error detecting means for detecting a fault in the control line and holding data on the control line, an output of the intelligent processor based on data on the control line from the error detecting means, and an output of the system bus connected to the server And selecting means for selecting

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the internal configuration of a PC server. The input / output device adapter 10 is based on the I ² O specification.
6 is controlled. Referring to FIG. 1, reference numeral 101 denotes a server such as a host computer or a mainframe, which is a CPU that outputs commands to input / output devices and performs access such as data transmission / reception, and 102 denotes a device when a plurality of devices are connected to a bus. This is a bus controller that controls whether to grant the right to use 32 or 64 bus lines without collision.

Reference numeral 103 denotes an I ² O processor which has the ability to independently process input / output devices to some extent to reduce the load on the CPU 101, and 104 denotes an I ² O processor 1
The error detection and holding circuit 103 detects the error 03, particularly the error of the PCI bus control unit of the I ² O processor 103, and holds the fact of the error by a flag or the like. And signal line 12
0, a selection circuit for selecting any one of 0, a hard disk driver, a printer, a digital camera, a CD-R
It is an input / output device adapter that performs data conversion for an input / output device such as an OM driver and a DVD-RAM, a bus management mechanism for adjusting the information transmission right, and transmission / reception of control signals.

Here, the types of errors include a hardware failure such as a parity error of an address or data, and a software error such as designating an address which does not exist in a corresponding device address. or,
There are various methods for detecting an error, such as a parity check and a control circuit for checking whether or not a flag is lit at an improper timing. The error detection result is not limited, and an EIF (Error Indicator) Flag)
The error is detected by turning on the flag.
Although only one I ² O processor and one input / output device adapter are shown, a plurality of I ² O processors are connected via the PCI bus 107, and a failure handling device is provided individually or collectively. Shall be

Next, a normal operation of the fault handling mechanism of the present embodiment will be described with reference to FIG.

When the server accesses an input / output device, the CPU 101 transmits a command, an address, and a control code via the PCI bus 107 to the I ² O processor 10.
3 (S11). The I ² O processor 103
The input / output device is a processor that performs input / output processing in place of the CPU 101, and executes a command for the input / output device (S12). Next, the error detection holding circuit 104 determines whether an error has been detected in the output of the I ² O processor 103 (S13).

The selection circuit 105 includes an error detection holding circuit 10
When the signal line 110 which is the output line of No. 4 is 0 (no), I
^TwoFrom the signal line 111 for access of the O processor 103
And if the signal line 110 is 1 (yes),
Signal from signal line 112 introduced from PCI bus 107
Is a circuit for selecting. Message from CPU 101
I received^TwoThe O processor 103 includes a selection circuit 105 and
Input / output device via the input / output device adapter 106
Access the data on the device, and ^TwoO pro
The processor 103 notifies the CP via the PCI bus 107
Notify U101 (not shown). Bus controller 1
02 indicates a plurality of I / Os connected to the PCI bus 107.^TwoO
If a processor or I / O device exists,
It performs management processing to avoid data collisions, etc.
In a normal operation, this process is sequentially executed.

Next, a case where a failure occurs in the I ² O processor 103 will be described. Error detection holding circuit 10
4 detects an error of a signal transmitted from the I ² O processor 103 to the input / output device, and when an error is detected, sets the signal line 110 to 1 and holds the state.

When the signal line 110 becomes 1, the bus controller 102 sends the I ² O processor 103 to the PCI bus 10
7 (S14), and instead, the signal line 112 is a circuit that enables access from the CPU1. Therefore, when a failure occurs in the I ² O processor 103, the signal line 110 is held at 1 by the error detection holding circuit 104, and the selection circuit 105 always selects the signal line 112, so that the command is reissued from the CPU 101 (S1).
5). The input / output device receives the access from the CPU 101 directly.

Further, after reissuing a command or the like from the CPU 101, the presence or absence of an error is detected again, and if there is an error, the system is shut down (S17). If no error is detected, access to the input / output device is controlled by the command data (S18).

After the above-described fault processing, the CPU 101 re-executes the instruction that has detected the error. In the flowchart of FIG. 2 described above, the process is re-executed once. If an error is still detected, the main body itself is stopped (system down) because it cannot be repaired (S17). Here, the number of re-executions of the CPU and the processing when remedy is impossible depend on the content configuration of the main body. That is, the main body itself may be restored after a predetermined time, and the CPU may be restarted from the I2O processor 103 again.

In the above embodiment, the I ² O processor 10
A 3 and the error detection holding circuit 104 has been described to separate, but the error detection holding circuit 104 I ² O processor 10
3, the error detection may be performed by software in the I ² O processor 103, and 1 or 0 in a normal state may be output to the signal line 110.

Although the system bus of the CPU 101 of the server has been described as the PCI bus 107, the ISA (Indu
stry Standard Architecture) bus, EISA (Exte
ndedIndustry Standard Architecture) bus, SCSI
A bus, an S-100 bus, or the like may be used.

[0023]

According to the present invention, even if a failure occurs in the I ² O processor, there is no need to replace the and I ² O processor stops server, eliminating troubles may be caused in the operation. By doing so, the probability of the server as a whole going down can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a failure handling mechanism according to the present invention.

FIG. 2 is a flowchart of a failure handling mechanism according to the present invention.

[Explanation of symbols]

101 CPU 102 Bus Controller 103 I ² O Processor 104 Error Detection and Holding Circuit 105 Selection Circuit 106 I / O Device Adapter 107 PCI Bus 110, 111, 112 Signal Line

Claims (6)

[Claims] 1. A fault processing apparatus for a personal computer having a plurality of intelligent processors between a server and an input / output device, comprising: an error detecting and holding means for detecting a fault in the intelligent processor and holding data of a control line; A fault processing device for a personal computer, comprising: a selection unit that selects an output of the intelligent processor and an output of the server based on data on a control line from a detection and holding unit. 2. A system bus between the server and the intelligent processor, wherein the intelligent processor and the system bus are separated by a bus controller controlling the system bus when the intelligent processor fails. The personal computer failure processing apparatus according to claim 1. 3. A fault processing device for a personal computer, comprising: a server; a system bus connected to the server; and a plurality of intelligent processors connected to the system bus. Error detecting and holding means for holding line data; and selecting means for selecting an output of the intelligent processor and an output of the server based on data on a control line from the error detecting and holding means. Fault handling device. 4. The system bus is a PCI bus,
4. The fault processing device according to claim 3, wherein when the fault of the intelligent processor is detected by the error detection and holding means, the system bus is separated from the intelligent processor. 5. When the error detection and holding means detects a fault in the intelligent processor, the system bus and the input / output device are connected by the selection circuit,
The failure processing apparatus according to claim 3, wherein the input / output device is directly accessed from the server. 6. A personal computer processing device comprising a server, a system bus connected to the server, and a plurality of intelligent processors connected to the system bus, wherein a failure of the server and / or the intelligent processor is detected. Error detecting means for holding data of a control line, and selecting an output of the intelligent processor and an output of the system bus connected to the server based on data on the control line from the error detecting means. A personal computer processing device comprising: a selection unit.