JPH11259295A - Instruction scheduling device for processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of a processor by the speculative solution of data dependence. SOLUTION: The entry of the instruction window of a register updating unit is provided with a predicted bit 160 for indicating whether or not a value held in a content field 122 of a destination field 120 is a predicted value. In this case, when either an executed bit 150 or the predicted bit 160 is set, the arithmetic operation of a following instruction in data dependence with this instruction is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a processor.
In particular, it relates to instruction scheduling of a processor.

[0002]

2. Description of the Related Art One of the factors hindering the performance improvement of a processor is a problem of dependency between instructions. These dependencies include control dependence, resource dependence (namedependence), and data dependence (data d
ependence). Among them, many studies have been made on control dependencies, and attempts have been made to eliminate the dependencies by branch prediction and speculative execution. The resource dependency is caused by a shortage of hardware resources such as the number of registers. This is the register name change (RMKeller, Look-Ahead Processors, AC
M Computing Surveys, vol.7, no.4, pp.177-195,197
It can be solved by applying 5). However, there is no way to resolve data dependencies, which is also called "true dependencies". In other words, data dependencies are a very serious problem that hinders improving instruction level parallelism.

Here, as a specific example of the data dependency,
An instruction sequence as shown in FIG. 6 will be described. For ease of understanding, the source operand of each of the operations f ₁ -f ₄ is limited to one. The execution latency is assumed to be 1 except for the instruction I1. Instruction I1 is:
For example, it is assumed that the load instruction is a load instruction in which a data cache miss has occurred, and its latency is 4.

There are two data dependencies in the instruction sequence of FIG. One is between instruction I1 and instruction I3, and the other is between instruction I3 and instruction I4. If there is a data dependency, the subsequent instruction cannot execute the operation without waiting for the end of the preceding instruction. In this example, the instruction I3 cannot start the operation unless the instruction I1 ends, and the instruction I4 cannot start the operation until the instruction I3 ends. Therefore, in the conventional example, an instruction that is not dependent on data is executed first, overtaking an instruction whose operation is stopped due to data dependence.
This operation is called dynamic instruction scheduling, and is performed by the reservation station (RMTomasulo, An E
ffecient Algorithm for Exploiting Multiple Arithme
tic Units, IBM Journal, vol. 11, pp. 25-33, 1967).

FIG. 7 shows a register update unit (GSSohi,
Instruction Issue Logic for High-Performance, Int
erruptible, Multiple Functional Unit, Pipelined Co
mputers, IEEE Trans.on Computers, vol.39, no.3, p
p. 349-359, 1990) shows one entry of an instruction window (a plurality of which exist). Each entry in the instruction window includes two source operand fields (Source Operand1,2) 100 (110), a destination field (Destination) 120, a dispatch bit (Dispatched) 130, a functional unit field (Functional Unit) 140, and an execution bit ( Execu
ted) 150 and the program counter field (P
rogram Counter) 180.

When the source operand is not obtained during the operation, the ready bit (Ready) 101 (111) is reset to indicate that the source operand is not available. At the same time, a tag (Ta
g) 102 (112) is set. When the operand becomes available, the value of the source register is set in the content field 103 (113), and the ready bit 10
1 (111) is set. The destination register number accompanying the tag information is held in the Register field 121 of the destination field 120,
The execution result of the instruction is stored in the content field 122. Dispatch bit 130 indicates whether an instruction has been dispatched to the functional unit specified in functional unit field 140. Execute bit 150 is set when the instruction is completed. If the execute bit 150 is set, subsequent instructions that have a data dependency with this instruction can be dispatched. The program counter field 180 is used for recovering the processor state from a branch prediction failure and realizing an accurate interrupt.

Each instruction is registered in the register update unit in the order in which the instructions appear in the program. When the preceding instruction finishes the operation, the operation result (122) and the destination register number (121) are broadcast. Subsequent instructions observe the destination register number (121), and if they match the source operand doug 101 (111), fetch the operation result as the source operand 103 (113). An instruction becomes executable when all source operands are available. Even if the preceding instruction has not completed execution, it can be overtaken and executed.

FIG. 8 is a block diagram showing a configuration of a conventional processor which executes an operation having a data dependency. This processor includes an instruction memory (I cache) 200, a register file (Register File) 210, and an instruction window (Instruction Window) as an instruction scheduling device.
w) 220, operation units (FU) 240 to 243, and a data memory (D cache) 250.

The processor fetches an instruction from the instruction memory 200 and registers it in the instruction window 220. The source operand is read from the register file 210 or the instruction window 220. If the source operand cannot be obtained from the register file 210, the operation units 240 to 24 wait until the preceding instruction is completed.
Capture the result of 3. The instruction having the source operands is issued to the operation units 240 to 243. The operation results in the operation units 240 to 243 are stored in the instruction window 22
0 is written to the register file 210.

FIG. 9 shows an example of instruction scheduling when the instruction sequence shown in FIG. 6 is executed. FIG. 9 is a simplified version of the instruction window entry shown in FIG. 7, and shows only the fields necessary for the description. Here, "s
“rc” is the tag of the source operand, “r” is the ready bit, “dest” is the destination register,
“D” indicates a dispatch bit, and “e” indicates an execution bit. Of these, when there is a check mark in the r, d, and e fields, it indicates that the bit has been set.

Further, the following assumptions are made to simplify the explanation. The fetch width and the dispatch width of the processor are both set to 1. Instruction commit is omitted. It is also assumed that the destination register number including the tag information is the same as the architecture register number. It is assumed that the register (r1) and the register (r2) are already available. It is also assumed that there is no operation to overtake an instruction whose operation has been stopped due to data dependence. Instruction scheduling will be described based on the above assumptions.

First, an instruction I1 is issued (issued) in a first cycle. The source operand tag r1 and the destination register tag r11 are held in the corresponding fields. Since r1 is available, the ready bit (r) is set. Further, the instruction I1 is dispatched, and the dispatch bit (d) is also set (a.). In the next cycle, instruction I2 is issued and dispatched (b.). In the following cycle, the instruction I3
Is issued. Since the execution bit (e) of the instruction I1 that generates the source operand r11 of the instruction I3 is not set, the instruction I3 cannot be dispatched. In the same cycle, the instruction I2 that has completed the operation is r1
2, the operation result is written back, and the execution bit (e) is set (c.). Source operand r12 obtained here
Is not used for the operation of the instruction I3 because it does not match r11 required by the instruction I3. Arrows represented by dotted lines in the figure indicate that the source operand tag and the destination tag did not match. In the next cycle, instruction I4 is issued. Since r13 is not yet available, it is not dispatched (d.). In the next cycle, the instruction I1 terminates the operation, writes the operation result back to r11, and sets the execution bit (e). Since r11 is a source operand required by the instruction I3, the instruction I3
Is dispatched. The arrow indicated by the thick line in the figure indicates that the source operand tag and the destination tag match (e.). Subsequently, in the next cycle, the operation of the instruction I3 is completed, and the instruction I4 is dispatched (f.) Because r13 is available. The execution of the instruction I4 ends in the last cycle (g.), And the instruction sequence in FIG. 6 ends.

[0013]

In the above example of the instruction scheduling, the operation result of the instruction I1 is used as the source operand r11 of the instruction I3.
The instruction I3 cannot be executed until the operation of 1 is completed. Similarly, the operation of the instruction I4 cannot be started unless the operation of the instruction I3 is completed. As described above, in the execution of an instruction sequence in which a data dependency exists, there is a waiting time until the operation of the preceding instruction is completed, so that the performance of the processor cannot be sufficiently exhibited. there were.

In order to solve the problem of data dependency, Lipasti et al. Have proposed a method of predicting the operation result and speculatively solving the data dependency (MHLipasti,
JPShen, Exceeding the Dataflow Limit via Value P
rediction Proc. of the 29thAnn.Int'l Symp. on Mic
roarchitecture, pp.226-237, 1996). When the operation result of an instruction that requires a long time for the operation is used in the subsequent operation, the operation result is predicted by the method described above, and the operation is performed using the result. Later, if the prediction result matches the actual calculation result, it means that the data dependency has been speculatively resolved.

The above proposal merely shows a method for predicting the operation result, but does not mention a specific method for realizing the instruction window. Therefore, in order to realize the speculative solution of the data dependency, it is necessary to construct a new instruction window for performing dynamic instruction scheduling.

An object of the present invention is to provide an instruction scheduling apparatus capable of improving the performance of a processor by realizing a speculative solution of data dependency.

[0017]

In order to solve the above-mentioned problems, an invention according to a first aspect of the present invention is directed to an instruction scheduling apparatus used for dynamic instruction scheduling of a processor, wherein data for predicting a value of a source operand required for an operation is provided. A plurality of entries for holding a plurality of instructions, each entry having a field indicating that the value of the source operand is the value predicted by the data prediction unit. I do.

According to a second aspect of the present invention, in the first aspect of the present invention, each of the entries includes at least a field for storing information about a source operand, a field for storing information about an operation result, a field indicating that an operation is being performed,
A field that indicates the operation unit where the instruction was issued, a field that indicates the end of execution, a field that indicates that the source operand is the predicted value, and a field that holds the program counter. At the time of execution of a subsequent instruction having a dependency, if either the field indicating the end of the execution or the field indicating that the source operand is a predicted value is set, information on the operation result is retained. The operation is started by using the data value held in the field to be operated.

According to a third aspect of the present invention, in the first or second aspect of the present invention, when the prediction of the source operand fails, all instructions following the failed instruction are discarded.

According to a fourth aspect of the present invention, in the first or second aspect of the present invention, each entry is provided with a field indicating that the instruction has been reissued.

According to a fifth aspect of the present invention, in the invention of the fourth aspect, when the prediction of the source operand fails, an instruction having a data dependency with the failed instruction is reissued.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an instruction scheduling apparatus for a processor according to the present invention will be described below. In this embodiment, the instruction scheduling when the instruction sequence shown in FIG. 6 is executed is taken as an example.

[First Embodiment] The instruction window of the first embodiment executes an instruction by predicting a calculation result when an instruction sequence has a data dependency (hereinafter referred to as an instruction window).
If the prediction fails later, the calculation result after the predicted instruction is discarded, and instruction scheduling for re-executing the instruction is realized.

The instruction window of this embodiment also stores prediction data used for speculative execution. When the speculatively executed instruction ends the operation, the value of the result is compared with the prediction data. If they match, the speculative execution is successful. If they do not match, it is necessary to return the state of the processor to the state before speculation. Here, all instructions following the load instruction that made an incorrect prediction are discarded, and execution is resumed from that instruction.

FIG. 1 shows an instruction window in which the register update unit is expanded, and the same parts as those in FIG. 7 are denoted by the same reference numerals. Each entry in the instruction window is 2
Source Operand1,
2) 100 (110), destination field (Destination) 120, dispatch bit (Dispatc
hed) 130, Functional unit field (Functional Un
It) 140, an execution bit (Executed) 150, a prediction bit (Predicted) 160, and a program counter field (Program Counter) 180.

When the source operand is not obtained during the operation, the ready bit (Ready) 101 (111) is reset to indicate that the source operand is unavailable. At the same time, a tag (Tag) 10 indicating the operand
2 (112) is set. When the operand becomes available, the value of the source register is
3 (113) and the ready bit 101 (11
1) is set. The destination register number accompanied by the tag information is the destination field 1
20 are stored in a Register field 121, and the execution result of the instruction is stored in a Content field 122. Also C
The ontent field 122 is also used for the purpose of holding data used for speculative execution. Dispatch bit 130 indicates whether the functional unit and instruction specified in functional unit field 140 have been dispatched. Execute bit 150 is set when the instruction is completed. The prediction bit 160 indicates whether the value held in the content field 122 of the destination field 120 is a predicted value. If either the execution bit 150 or the prediction bit 160 is set, a subsequent instruction having a data dependency with this instruction can be dispatched. Then, when the actual calculation result is obtained, the predicted value and the actual value are compared, and the success / failure of the speculative execution is determined. The actual value is stored in the content field 122 of the destination field 120, and the prediction bit 160 is reset. Finally, the program counter field 180
It is used to recover the processor state from branch prediction and data prediction failure, and to realize an accurate interrupt.

FIG. 2 is a block diagram showing the configuration of a processor for speculatively executing an operation having a data dependency. The processor includes an instruction memory 200, a register file 21
0, an instruction window 221 as an instruction scheduling device, a data prediction device (Pred) 230, operation units 240 to 243, and a data memory 250.

The processor fetches an instruction from the instruction memory 200 and registers it in the instruction window 221. The source operand is read from the register file 210 or the instruction window 221.
If it is not possible to obtain from the number 10, the data prediction device 230
Predicts the source operand. A known prediction device can be used as the data prediction device 230 (for example, MHLipasti, JPShen, Exceeding the Dat
aflow Limit via Value Prediction Proc. ofthe 29th
Ann. Int'l Symp. On Microarchitecture, pp.226-237,
1996). Here, the description of the configuration and operation of the data prediction device 230 is omitted.

If the source operand cannot be predicted, the results of the arithmetic units 240 to 243 are fetched after the completion of the preceding instruction as in the conventional case. The instruction having the source operands is issued to the operation units 240 to 243. The operation result is written to the register file 210 through the instruction window 221.

FIG. 3 shows an example of instruction scheduling when the instruction sequence of FIG. 6 is executed. FIG.
Is a simplified version of the instruction window entry shown in
9 are denoted by the same reference numerals. "P" in FIG.
Indicates an entry of a newly added predicted bit (Predicted) 160.

Next, instruction scheduling in the first embodiment will be described. However, for the sake of simplicity, the same assumption is made as in the example of FIG. Here, it is assumed that only the instruction I1 can predict the data value.

First, an instruction I1 is issued in the first cycle. The source operand tag r1 and the destination register tag r11 are held in the corresponding fields. Since r1 is available, the ready bit (r) is set. Further, the instruction I1 is dispatched, and the dispatch bit (d) is also set. In the instruction I1, the value of r11 is predicted, and the prediction bit (p) is set (a.). In the next cycle, instruction I2 is issued and dispatched (b.). In the following cycle, instruction I
3 is issued. Here, since the prediction bit (p) is set in the instruction I1 for generating the source operand r11 of the instruction I3, the instruction I3 can be dispatched. In the same cycle, the instruction I2 writes the operation result back to r12 and sets the execution bit (e) (c.). The source operand r12 obtained here does not match r11 required by the instruction I3 and is not used. In the next cycle, instruction I4 is issued. The instruction I4 is dispatched (d.) Because the instruction I3 has completed the operation and r13 is available. There are two cases for the next cycle. The case where the prediction of the instruction I1 is successful (correct) and the case where the prediction is failed (fail).

If the prediction of r11 succeeds, the instruction I1 resets the prediction bit (p) and sets the execution bit (e). In the same cycle, instruction I4 completes the operation and also sets execution bit (e) (e.). This ends the sequence. On the other hand, if the prediction of r11 fails, the instructions I2 to I4 must be discarded. The execution bit (e) of the instruction I1 is set, and the processor resumes the execution from the fetch of the instruction I2 (f.).

Therefore, in the instruction scheduling of the first embodiment, if the prediction is successful, the instruction sequence can be completed in four cycles, and the operation is completed in a smaller number of cycles than in the conventional example of FIG. be able to. However, if the prediction fails, the following miss penalty will be incurred. That is, four cycles due to the above-described incorrect speculative execution, a cycle for discarding an instruction, and a cycle for refetching an instruction.

[Second Embodiment] In the instruction scheduling according to the first embodiment, when the prediction fails, all the instructions having no data dependency are recalculated. The instruction window of the second embodiment detects, in addition to the prediction of the operation result as in the first embodiment, an instruction that has a data dependency with the instruction whose prediction failed, and recalculates only that instruction. This implements instruction scheduling.

FIG. 4 shows an instruction window in which the register update unit shown in FIG. 1 is further extended to enable reissuing of instructions, and the same parts as those in FIG. 1 are denoted by the same reference numerals. Each entry of the instruction window has a reissued bit (Reissued) 170 added to the configuration of FIG. The reissue bit 170 indicates that the corresponding instruction has been reissued, that is, the instruction to be recalculated. As in the first embodiment, the predicted data value is held in the content field 122. When the instruction is completed and the result is obtained, the destination tag and the execution result are broadcast as in the conventional instruction scheduling. At the same time, a signal indicating the success / failure of the prediction is also broadcasted (hereinafter, this signal is referred to as a reissue signal).

If the prediction is successful, the subsequent instruction in which the destination tag 121 matches the source operand tag 101 (111) can be dispatched, as in the conventional scheduling. On the other hand, when the prediction fails, the instruction in which the destination tag 121 and the source operand tag 101 (111) match becomes a target of reissue. Dispatch bit 130 of the instruction with the matched tag
Is already set, the instruction is performing an operation with the wrong source operand and must be reissued. In this case, the dispatch bit 130 and the execution bit 150 are reset, and the reissue bit 170 is set. A reissue signal is also broadcast when execution of the reissued instruction ends. Therefore, the reissue signal indicates that the instruction whose data value has failed to be predicted or the reissued instruction has finished executing. Thereafter, similarly to the above-described first embodiment, the instruction whose tag matches and whose dispatch bit 130 is set is reissued. Thus, instructions that must be reissued are detected in order.

FIG. 5 shows an example of instruction scheduling including instruction reissue when the instruction sequence of FIG. 6 is executed. FIG. 5 is a simplified version of the entry in the instruction window shown in FIG. 1 as in FIG. 3, and the same parts as those in FIG. 9 are denoted by the same reference numerals. “I” in FIG. 5 indicates an entry of a newly added reissued bit (Reissued) 170.

Next, the instruction scheduling in the second embodiment will be described. The configuration of the processor is substantially the same as that of FIG. For the sake of simplicity, the same assumptions as in the first embodiment are made. further,
Until the execution of the instruction I1 is completed, (a.) To (c.) Are the same as those described with reference to FIG.

If the prediction of r11 succeeds, the instruction I1 resets the prediction bit (p) and sets the execution bit (e). In the same cycle, instruction I4 completes the operation and also sets execution bit (e) (e.). This ends the sequence. On the other hand, when the prediction of r11 fails, a reissue signal is broadcast, and reissuance of an instruction having a data dependency relationship is started. That is, since the instruction I3 with the matching tag has already been dispatched using the wrong source operand, the instruction I3 is to be reissued and the reissue bit (i) is set. The instruction I3 is issued again and the dispatch bit (d) is set (f.). In the next cycle, instruction I3 ends, sets execution bit (e) and resets reissue bit (i). At the same time, a reissue signal is broadcast. In the same manner as in the previous cycle, the subsequent instruction I4 is detected as a reissue target and the reissue bit (i) is set (g.). Instruction I in the next cycle
4 ends (h.), Sets the execution bit (e) and resets the reissue bit (i). This instruction sequence is completed in seven cycles.

Therefore, in the instruction scheduling of the second embodiment, the number of cycles required when the prediction of the data value fails is the number of cycles required when the data-dependent speculative execution described in the conventional example is not performed. Is the same as That is, even if the speculation fails, the calculation is not performed again for all the instructions including the instruction having no data dependency, so that the penalty can be minimized.

The instruction window of the second embodiment is as follows:
Compared with the conventional instruction window shown in FIG. 7, the number of reissue signals is increased by one and the number of entries is increased by 2 bits. When the reissue signal is issued, execute the next instruction or
Alternatively, a circuit for determining whether or not to start over is required. However, compared to the conventional example, there is no significant increase in hardware, and even if prediction fails, the number of cycles does not increase. In other words, the reissue of the instruction can be realized with relatively small-scale hardware and within a range that does not greatly affect the number of cycles.

[0043]

As described above, according to the first to fifth aspects of the present invention, the value of the source operand required for the operation is predicted, and the operation of the subsequent instruction having the data dependency is executed using this value. Thus, when an instruction sequence having a data dependency is executed, a waiting time until the operation of the preceding instruction is completed can be omitted. Therefore, it is possible to solve the data dependency speculatively and improve the performance of the processor.

In particular, in the inventions according to claims 4 and 5, when the prediction of the source operand fails, only the instruction having a data dependency with the failed instruction is reissued. The number of cycles required for recalculation can be minimized as compared to re-executing all instructions. Therefore, the performance of the processor can be further improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an instruction window in which a register update unit is extended.

FIG. 2 is a configuration block diagram of a processor that speculatively executes an operation having a data dependency relationship.

FIG. 3 is an explanatory diagram illustrating an example of instruction scheduling according to the first embodiment.

FIG. 4 is an explanatory diagram showing an instruction window in which a register update unit is further extended;

FIG. 5 is an explanatory diagram showing an example of instruction scheduling including instruction reissuing in the second embodiment.

FIG. 6 is an explanatory diagram showing a specific example of an instruction sequence.

FIG. 7 is an explanatory diagram showing one entry of an instruction window configured using a register update unit.

FIG. 8 is a configuration block diagram of a conventional processor that executes an operation having a data dependency.

FIG. 9 is an explanatory diagram showing an example of instruction scheduling in a conventional example.

[Explanation of symbols]

 100, 110 Source operand field 101, 111 Ready bit 102, 112 Tag field 103, 113 Operand field 120 Destination field 121 Destination register field 122 Operation result field 130 Dispatch bit 140 Function unit field 150 Execution bit 160 Prediction bit 170 Reissue Bit 180 Program counter field 200 Instruction memory 210 Register file 220, 221 Instruction window 230 Data prediction device 240, 241, 242, 243 Arithmetic unit 250 Data memory

Claims (5)

[Claims] 1. An instruction scheduling apparatus used for dynamic instruction scheduling of a processor, comprising: a data predicting unit for predicting a value of a source operand required for an operation; and a plurality of entries for holding a plurality of instructions. An instruction scheduling apparatus for a processor, wherein each entry is provided with a field indicating that the value of the source operand is the value predicted by the data prediction means. 2. Each of the entries includes at least a field for holding information about a source operand, a field for holding information about an operation result, a field indicating that an operation is being performed, a field indicating an operation unit to which an instruction has been issued, and an execution end. And a field for indicating that the source operand is a predicted value, and a field for holding a program counter. When a subsequent instruction having a data dependency with the previously executed instruction is executed, the execution is terminated. If either the field that indicates the expected value or the field that indicates that the source operand is the predicted value is set, the operation is performed using the data value held in the field that holds the information about the operation result. 2. The processor of claim 1, wherein the processor is started. Scheduling apparatus. 3. The instruction scheduling apparatus for a processor according to claim 1, wherein when the prediction of the source operand fails, all instructions subsequent to the failed instruction are discarded. 4. The instruction scheduling apparatus for a processor according to claim 1, wherein a field indicating that the instruction has been reissued is provided in each of the entries. 5. The instruction scheduling apparatus for a processor according to claim 4, wherein when the prediction of the source operand fails, an instruction having a data dependency relationship with the failed instruction is reissued.