JPH1125614A - Pll circuit and disk reproducing device using the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL(phase/locked loop) circuit capable of obtaining a stable loop characteristic regardless of a rate of an input EFM (eight to fourteen modulation) signal and a disk reproducing device using it. SOLUTION: Although the PLL circuit of the disk reproducing device forms a feedback loop consisting of a phase comparator 64, an LPF(low-pass filter) 65, a loop gain amplifier 66 and a VCO(voltage controlled oscillator) 61 by making the EFM signal an input, the feedback loop is composed of LSIs except the LPF requiring flexibility. A part of a resistor in the LPF 65 constituted of the resistor Rb and a capacitor C is incorporated into the output part of the phase comparator 64 in the LSI (semiconductor chip) as the resistor (Ra) 67. An effect due to on-resistance of a transistor is eliminated apparently, and phase comparison information is transmitted correctly to a next stage. Thus, the stable loop characteristic is obtained regardless of the rate of the input EFM signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CD player, C
The present invention relates to a disk reproducing apparatus such as a D-ROM and a DVD-ROM, and more particularly to a PLL circuit used for the disk reproducing apparatus.

[0002]

2. Description of the Related Art A disk reproducing apparatus used for audio equipment and computer peripheral equipment is configured as shown in the system diagram of FIG. A laser pickup (P) is provided on a pit row on the disk 1 rotated by the disk motor 3.
U) The pit information is obtained by irradiating a beam generated from 2 and converting a beam reflected from the beam into an electric signal (RF signal) by a photodiode. The converted RF signal is further amplified by the RF amplifier 4. The amplified RF signal is binarized into a digital signal called an EFM (Eight to Fourteen Modulation) signal by a data slice circuit (asymmetry correction circuit) 5 for asymmetry correction and digitization, and then a PLL (Phase Lock).
Loop) supplied to the circuit. The PLL circuit 5 generates a bit clock signal PLCK extracted based on the EFM signal. The EFM signal is sent to the subsequent signal processing circuit 7 together with the bit clock signal PLCK. Signal processing circuit 7
Receives an EFM signal as input, detects synchronization pattern,
A circuit that performs processes such as demodulation, deinterleaving, and error correction, and outputs audio or computer data to the outside only after these processes.

[0003] The present invention relates to a PLL circuit in the disk reproducing apparatus described above. FIG. 2 shows a PLL circuit of a conventional disk reproducing apparatus. Voltage Controlled Oscillator (VCO) 6
1.PDO (PhaseDetector / Pase Comparato)
r) 64, low-pass filter LPF (Low-Pass Filter) 6
5. A feedback loop composed of a loop gain amplifier AMP66 is formed. This feedback loop can be roughly divided into functional groups.
Phase comparison means 6 receiving the O output signal and the EFM signal as inputs
2 and the output of the phase comparison means 62, and the output is
And a filter means 63 for supplying to the CO 61. Details of the PLL circuit will be further described. VCO
61 outputs a VCO output signal. Phase comparison means 62
Is composed of a phase comparator 64 and its output unit.
The filter means 63 comprises an LPF 65, a loop gain amplifier 66, resistors R1 and R2, and a capacitor C0. The output of the phase comparator includes a P-channel MOS transistor Pch and an N-channel MOS transistor Nc.
h CMOS transistor and N-channel MOS
And an analog switch ASW composed of a transistor pair.

A P-channel MOS transistor Pch has
The source is connected to the power supply, and the drain is
(PDO terminal), and the gate is connected to the output of the phase comparator 64. The N-channel MOS transistor Nch has a source grounded and a drain PDO
The terminal is connected to the drain of the P-channel MOS transistor Pch, and the gate is connected to the output of the phase comparator 64. A consisting of an N-channel MOS transistor pair
SW connects the source and the drain of the N-channel MOS transistor to each other, and has one gate connected to the output of the phase comparator 64 and the other gate connected to the phase comparator 6.
4 is connected via an inverter INV.
P channel MOS transistor Pch outputs a high level (H) potential, and N channel MOS transistor N
ch outputs a low-level (L) potential, and the N-channel MO
The S transistor pair ASW outputs an intermediate potential. The filter means 63 has an LPF 65 having a function as a holding circuit for removing a high frequency component and noise from the phase difference voltage and stably locking the PLL circuit, and an amplifier (loop gain amplifier) 66 for obtaining a loop gain. And LPF6
Reference numeral 5 denotes a resistor R having one end connected to the PDO terminal and a capacitor C having one end connected to the intermediate potential and the other end connected to the other end of the resistor R. The output of the LPF 65 is input to the amplifier 66 via the resistor R2,
And the output of the amplifier 66 via the resistor R, and this output is input to the VCO 61.

The PLL circuit 6 receives the EFM signal, compares the phase difference with the VCO output signal by the phase comparator 64, and supplies the phase difference signal voltage to the VCO 61 via the LPF 65 and the amplifier 66 to control the oscillation frequency. I do. Here, the phase comparator 64 operates as shown in the timing chart of FIG.
Three levels of H level, intermediate potential and L level are output for each edge of the signal. Of these, the H level width has phase information. When the edge of the EFM signal is ahead of the rising edge of the VCO output signal, it is wider than the half cycle of the VCO output, when it is late, it is narrow, and when it is equal, it is Are output for a half cycle. In addition, the L period is always generated for a half cycle, and the other period has an intermediate potential. The PLL circuit 6
The VCO is controlled based on the phase difference signal, and the edge of the EFM signal is always locked so as to be synchronized with the rising edge of the VCO output signal, thereby stabilizing the bit clock PLC.
K is extracted.

[0006]

In the above configuration, when the frequency of the input EFM signal increases, the influence of the on-resistance of the CMOS transistor at the output of the phase comparator is reflected on the phase difference signal. This means that the phase information cannot be correctly transmitted to the LPF of the next stage in the loop system, which is a problem in terms of system stability. The effect of the on-resistance will be specifically described with reference to FIGS.
As shown in FIG. 4, the output section of the phase comparator 64 has a CMOS output format including a P-channel MOS transistor Pch and an N-channel MOS transistor Nch.
This output passes through the PDO terminal to the L
PF (not shown). Normally, when the PLL circuit is completely locked, since the edge of the EFM signal coincides with the rising edge of the VCO output signal, the signal seen at the PDO terminal ideally has the waveform shown in the timing chart of FIG. However, as shown in FIG.
Since the terminal is an I (semiconductor chip) terminal, a capacitance component Cp such as a capacitance between pins exists between the device and the package pins. Also, the transistor P
The on-resistance of the channel and the on-resistance of the transistor Nch are generally not equal. This indicates that the rise and fall times of the waveform (determined by the time constant determined by the on-resistance of the transistor and the capacitance component of the terminal) differ between the H level and the L level appearing at the PDO terminal. This difference in delay time is not a problem within a range that can be neglected sufficiently with respect to the oscillation frequency of the VCO.
When the rate of the M signal increases and the oscillation frequency of the VCO increases, it cannot be ignored.

The timing chart of FIG. 5 shows the waveform of the PDO terminal when the oscillation frequency of the EFM is high. In this example, the on-resistance of the transistor on the Pch side is N
The behavior when the on-resistance is larger than the on-resistance of the transistor on the ch side is shown. However, as shown in this figure, even though the edges of the EFM signal and the VCO output signal match, the H level due to the above-mentioned delay time difference. And the width of the L level are not the same. In other words, this indicates that the phase comparison information cannot be correctly transmitted to the LPF of the next stage, which means that the loop filter characteristics have not been correctly obtained. In such a state, the quality of the bit clock generated by using the output of the VCO is significantly reduced, and the quality of the entire system is reduced. The present invention has been made in view of such circumstances, and a PLL that obtains a stable loop characteristic regardless of the rate of an input EFM signal.
A circuit and a disk reproducing apparatus using the circuit are provided.

[0008]

Means for Solving the Problems CD Player, CD-R
2. Description of the Related Art A disk reproducing device such as an OM or a DVD-ROM has a built-in PLL circuit for extracting a bit clock from an EFM signal recorded on a disk. The PLL circuit receives the EFM signal as an input and forms a feedback loop including a phase comparator, an LPF, a loop gain amplifier, and a VCO. However, the PLL circuit is configured by an LSI except for the LPF that requires flexibility. In such a configuration,
When the rate of the input EFM signal increases and the oscillation frequency of the VCO increases, the delay time generated by the capacitance between the terminals of the phase comparator output and the on-resistance of the output transistor of the comparator greatly affects the comparison result. The phase comparison information cannot be correctly transmitted to the LPF. Therefore, the present invention eliminates the effect of the on-resistance of the transistor by incorporating a part of the resistance of the LPF including the resistor and the capacitor in the output section of the phase comparator in the LSI (semiconductor chip). It is characterized in that the comparison information is correctly transmitted to the next stage.

That is, the PLL circuit of the present invention comprises a voltage (current) -frequency converting means whose oscillation frequency is controlled by an input voltage or an input current, a recording / reproducing signal and an output of the voltage (current) -frequency converting means. Phase comparing means for detecting a phase difference with the signal and outputting a voltage waveform corresponding to the difference,
An output terminal to which the output of the phase comparison means is supplied to the outside; a resistance element arranged in series between the output transistor of the phase comparison means and the output terminal; and a phase difference voltage after passing through the resistance element And a filter means having a low-pass filter having a function as a holding circuit for stably locking the PLL circuit and a signal amplifying means for obtaining a loop gain. A phase difference voltage is generated so as to absorb the influence of the on-resistance of the output transistor of the phase comparison means. A data reproducing apparatus according to the present invention includes: a photoelectric conversion element that optically reads data recorded on a disc and converts the data into an electric signal; an amplifier that amplifies an electric signal supplied from the photoelectric conversion element; A data slice circuit for converting an electric signal to be converted into a binary signal, a PLL circuit for generating a clock signal corresponding to a change in data reproduction speed based on the binary signal, and the clock signal. And a signal processing circuit for demodulating the binarized signal based on the data and reproducing data. Thus, LPF
Is built in the LSI, the input E
It is possible to obtain a stable loop characteristic regardless of the FM signal rate.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. The PLL circuit used in the disk reproducing apparatus of the present invention has a built-in resistor Ra between the CMOS transistor and the PDO terminal at the output of the phase comparator. FIG. 1 shows a disk reproducing apparatus used for an audio device, a computer peripheral device, and the like, and its detailed contents are as described above. FIG. 6 shows a PLL circuit of the CD-ROM reproducing device. This PLL circuit includes a voltage controlled oscillator VCO6
1. Phase comparator PDO64, low-pass filter LPF6
5. A feedback loop composed of an amplifier (loop gain amplifier AMP) 66 is formed. When this feedback loop is roughly divided into functions, VCO6
1, a phase comparison means 62 to which a VCO output signal and an EFM signal are inputted, and a filter means 63 to which the output of the phase comparison means 62 is inputted and the output is supplied to the VCO 61.

The details of the PLL circuit will be further described.
VCO 61 outputs a VCO output signal. The phase comparing means 62 is composed of a phase comparator 64 and its output part. The filtering means 63 is composed of an LPF 65, an amplifier 66, resistors R1, R2, and a capacitor C0. The output of the phase comparator 64 includes a P-channel MOS transistor Pch and an N-channel MOS transistor Nch
, And an analog switch ASW including a pair of N-channel MOS transistors. P channel MOS transistor Pch
Has a source connected to the power supply, a drain connected to the terminal (PDO terminal) of the phase comparing means 62 via the resistance element Ra which is a feature of the present invention, and a gate connected to the output of the phase comparator 64. . The N channel MOS transistor Nch has a source grounded and a drain P channel M
The drain of the OS transistor Pch and the resistance element R
is connected to the PDO terminal via a, and the gate is connected to the output of the phase comparator 64. An ASW composed of a pair of N-channel MOS transistors connects the source and the drain of the N-channel MOS transistor to each other, and has one gate connected to the output of the phase comparator 64 and the other gate connected to the output of the phase comparator 64. It is connected via INV. P channel MOS transistor Pch
Output a high-level (H) potential, N-channel MOS transistor Nch outputs a low-level (L) potential, and N
Channel MOS transistor pair ASW outputs an intermediate potential.

The filter means 63 removes high-frequency components and noise from the phase difference voltage, and serves as an LPF 65 having a function as a holding circuit for stably locking the PLL circuit, and an amplifier for obtaining a loop gain (loop gain amplifier). 6
The LPF 65 has a resistor Rb having one end connected to the PDO terminal, one end connected to the intermediate potential, and the other end having a resistor Rb.
Is connected to the other end of the capacitor C. L
The output of the PF 65 is input to the amplifier 66 via the resistor R2, and is connected to the output of the amplifier 66 via the capacitor C0 and the resistor R. This output is input to the VCO 61. The PLL circuit 6 receives the EFM signal, performs a phase difference comparison with the VCO output signal by the phase comparator 64,
The phase difference signal voltage is converted to VC through the LPF 65 and the amplifier 66.
It is given to O61 to control the oscillation frequency. Here, the phase comparator 64 is as shown in the timing chart for explaining the operation of the signal of the phase comparator 64 in FIG.

In the PLL circuit of the present invention shown in FIG. 6, a resistor Ra67 is built in between the CMOS transistor (transistor Pch and transistor Nch) and the PDO terminal at the output of the phase comparator 64. This resistance element R
In order to solve the problem of the prior art, FIG. 2A shows that a part of the resistance R of the LPF 65 constituted by the external CR in FIG. 2 is sufficiently larger than the ON resistance of the CMOS transistor, and the process variation of the LSI (semiconductor chip). It is intended to make the influence of the capacitance component of the terminal invisible by incorporating it in a semiconductor chip within a range where the influence of the above does not appear. Therefore, in FIG. 6, the resistance of the LPF 65 is Rb. In FIG. 6, r1 is the ON resistance of the transistor Pch, r2 is the ON resistance of the transistor Nch, and r3 is the ON resistance of the analog switch ASW. At this time, a part (Ra in the figure) of the resistor R of the LPF which has been conventionally externally mounted is built in a range that satisfies the following conditions (1) and (2). Ra + Rb = R (1) Ra >> r1, r2, r3 (2) Ra is set to a value that does not affect the performance due to the variation in the resistance value due to the process variation of the LSI. Is preferred.

With such a configuration, the P shown in FIG.
The ideal waveform of the PDO terminal when the LL circuit is completely locked is delayed by a delay time uniquely determined by the resistance element Ra incorporated in the semiconductor chip and the capacitance Cp of the PDO terminal. Therefore, the actual phase comparison difference signal viewed at the PDO terminal is H level as shown in FIG.
Both the level and the L level are pulse waveforms of the same width delayed by the same time. According to the above configuration, the delay time of the phase comparison difference signal is determined by the internal resistance Ra and the capacitance component Cp of the terminal.
Therefore, the influence of the unbalance of the on-resistance of the transistor can be apparently eliminated. That is, if both the H level and the L level are uniformly delayed, the original phase comparison information can be correctly transmitted to the LPF of the next stage, and the stability of the system can be ensured regardless of the oscillation frequency of the VCO.

Next, with reference to FIG. 8 and FIG. 9, an arrangement structure of each part of the disk reproducing apparatus will be described. The system of a disc playback device is composed of mechanical parts such as a disc, a disc motor, and a pickup, a circuit for outputting audio output, a motor control circuit, and a part mounted on a board such as a system controller for controlling these circuits. ing. FIG. 8 is a plan view of a circuit board such as a printed circuit board used for this board. FIG. 2 mainly shows circuits related to the present invention among those mounted on a circuit board. The circuit board 100 includes a semiconductor chip 11 composed of an RF amplifier, a data slice circuit,
A semiconductor chip 10 in which an LL circuit and a signal processing circuit are formed as one is mounted. In addition, a system controller, a motor control circuit, and the like are formed on the respective semiconductor chips 12 and 13 and mounted on the circuit board 100. In addition, for example, components such as passive elements are directly mounted on a circuit board without being incorporated in a semiconductor chip (this is called external attachment). Further, components constituting the circuit are also externally attached to the circuit board 100 as needed. For example, a low-pass filter constituting a PLL circuit is also externally provided.

FIG. 9 is a plan view of a circuit board on which a low-pass filter constituting a PLL circuit is mounted. Circuit board 10
The semiconductor chip 10 made of silicon or the like mounted on the phase comparator 64 includes a phase comparator 64, a PDO terminal of the phase comparator 64, and a resistance element Ra inserted between the phase comparator 64 and the PDO terminal.
67 are formed. As the resistance element Ra, a diffusion resistance formed on the semiconductor chip 10, a polysilicon resistance formed on the semiconductor chip 10 via an insulating film, or the like can be used. LPF electrically connected to PDO terminal
63 is a circuit board 1 directly not formed on a semiconductor chip.
It is mounted on 00. The PDO terminal is connected to the resistor Rb of the LPF 63.

[0017]

According to the present invention, the delay time of the phase difference signal output from the phase comparator is uniquely determined by the resistance element Ra built in the semiconductor chip and the capacitance component Cp of the terminal of the phase comparator. This makes it possible to apparently eliminate the influence of the unbalance of the on-resistance of the output transistor of the phase comparator. That is, if both the H level and the L level are delayed by the same time, the original phase comparison
And the stability of the system can be ensured irrespective of the oscillation frequency of the VCO. This allows input E
It is possible to extract a stable bit clock regardless of the FM signal rate.

[Brief description of the drawings]

FIG. 1 is a block diagram of the present invention and a conventional disk reproducing apparatus.

FIG. 2 is a circuit block diagram of a conventional PLL circuit.

FIG. 3 is a timing chart showing the operation of the phase comparator of FIG. 2;

FIG. 4 is a configuration diagram of a conventional phase comparator output unit and a timing diagram showing an ideal operation of a PDO terminal at the time of locking.

FIG. 5 is a configuration diagram showing a conventional model of inter-terminal capacitance of an output section of a phase comparator and a timing diagram showing an operation of an actual PDO terminal in a high-frequency region.

FIG. 6 is a circuit block diagram of a PLL circuit of the present invention.

FIG. 7 is a timing chart showing an operation of a PDO terminal in a high frequency region at the time of locking in the PLL circuit of FIG. 6;

FIG. 8 is a plan view of a circuit board on which the disk reproducing device of the present invention is mounted.

FIG. 9 is an enlarged plan view of a circuit board on which the disk reproducing device of the present invention is mounted.

[Explanation of symbols]

1 ... Disc, 2 ... Pickup (P
U), 3: disk motor, 4: RF amplifier, 5: data slice circuit, 6: PLL
Circuit, 7 ... Signal processing circuit, 10, 11, 12,
13 semiconductor chip, 61 voltage-controlled oscillator V
CO, 62 ... Phase comparison means, 63 ... Filter means, 64 ... Phase comparator (PDO), 65
..Low-pass filter LPF, 66... Amplifier (loop gain amplifier), 67... Resistive element (Ra), 1
00 ... circuit board.

Claims (12)

[Claims] 1. A voltage (current) -frequency converter whose oscillation frequency is controlled by an input voltage or an input current, and a phase difference between a recording / reproducing signal and an output signal of the voltage (current) -frequency converter is detected. A phase comparison unit that outputs a voltage waveform according to the difference; an output terminal to which the output of the phase comparison unit is supplied to the outside; and an output transistor of the phase comparison unit and the output terminal in series. And a low-pass filter and a loop gain having a function as a holding circuit for stably locking the PLL circuit while removing high-frequency components and noise from the phase difference voltage after passing through the resistive element. And a filter means having a signal amplifying means for adjusting the phase of the resistance element so as to absorb the influence of the on-resistance of the output transistor of the phase comparison means. PLL circuit, characterized in that to generate a voltage. 2. The PLL circuit according to claim 1, wherein a bit clock is extracted from a signal recorded on an optical disk. 3. The PLL circuit according to claim 1, wherein the low-pass filter includes a resistor and a capacitor having one connected to an intermediate potential and the other connected in series with the resistor. . 4. The PLL circuit according to claim 3, wherein a time constant of the low-pass filter is determined from the resistance element, the resistance, and the capacitor. 5. The phase comparison means comprises a phase comparator and an output transistor thereof, wherein the output transistor is connected between an output of the phase comparison means and the resistance element. The PLL circuit according to claim 1. 6. The output transistor according to claim 5, wherein said output transistor comprises a CMOS transistor comprising a P-channel MOS transistor and an N-channel MOS transistor, and an analog switch comprising a pair of N-channel MOS transistors. The PLL circuit as described in the above. 7. The P-channel MOS transistor outputs a high-level potential, the N-channel MOS transistor outputs a low-level potential, and the N-channel MOS transistor pair outputs an intermediate potential.
3. The PLL circuit according to 1. 8. The P-channel MOS transistor,
A source is connected to the power supply, a drain is connected to the resistance element, a gate is connected to the output of the phase comparator, and the N-channel MOS transistor has a source grounded and a drain connected to the resistance element and the P-channel MOS transistor.
The N channel MOS transistor pair connects the source and the drain of the N channel MOS transistor to each other, and one gate is connected to the output of the phase comparator. 8. The PLL circuit according to claim 6, wherein the PLL circuit is connected to an output, and the other gate is connected to an output of the phase comparator via an inverter. 9. The PLL circuit according to claim 8, wherein the resistance of the resistance element is sufficiently larger than the on-resistance of each of the P-channel MOS transistor, the N-channel MOS transistor, and the analog switch. 10. A photoelectric conversion element for optically reading data recorded on a disk and converting the data into an electric signal, an amplifier for amplifying an electric signal supplied from the photoelectric conversion element, and an electric power supplied from the amplifier. The PLL according to any one of claims 1 to 9, wherein a data slice circuit converts a signal into a binary signal, and a clock signal according to a change in a data reproduction speed based on the binary signal. A circuit; demodulating the binary signal based on the clock signal;
A data reproducing apparatus, comprising: a signal processing circuit for reproducing data. 11. The data reproducing apparatus according to claim 10, wherein the amplifier, the data slice circuit, the PLL circuit, and the signal processing circuit are formed on a circuit board. 12. The voltage (current) -frequency conversion means, the phase comparison means, the output terminal, and the resistance element constituting the PLL circuit are formed on a semiconductor substrate mounted on the circuit board, and the low-pass The disk reproducing apparatus according to claim 11, wherein the filter is directly mounted on the circuit board.