JPH11252549A - Image coding/decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an image coding/decoding device best suited for mounting on a portable information terminal where miniaturization and low power consumption are required. SOLUTION: A motion compensation section (MC-ADD/SUB) 37, a discrete cosine transform section(DCT) 34, a quantization/inverse quantization processing section(Q/IQ) 313 and an inverse discrete cosine transform section(IDCT) 35 are operated as a pipeline, in which 6 blocks consisting of luminance blocks (y0-y3) and color blocks (Cb, Cr) configuring one macro block are sequentially subject to motion compensation pixel subtraction (MC-SUB), discrete cosine transform(DCT), quantization/inverse quantization(Q/IQ), inverse discrete cosine transform(IDCT) and motion compensation pixel sum processing (MC-ADD). The image is coded efficiently even at a low operating frequency by applying parallel processing to plurality of different blocks from each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image encoding / decoding device, and more particularly to an image encoding / decoding device used in a portable information terminal or the like.

[0002]

2. Description of the Related Art Generally, an image coding algorithm employs a method of sequentially using a large number of processes. For example, ISO
MPEG, which is a standard for image coding of / IEC, realizes highly efficient coding by using discrete cosine transform, quantization, motion compensation frame prediction, and entropy coding by variable length coding. Other image coding processes are also realized by a combination of similar algorithms.

In these image encoding processes, an input image is divided into regions of a fixed size, and each data is sequentially subjected to the above-mentioned encoding process. For example, ISO /
FIG. 15 shows a method used in IEC MPEG. The input image has 16 × 1 luminance pixels as shown in FIG.
Each of the chrominance pixels is divided into 8 × 8 pixels to form one data group (referred to as a macroblock), and one macroblock is divided into four 8 × 8 blocks to divide one macroblock into six pixels. Each block is composed of 8 × 8 pixel blocks, and each process of encoding is sequentially performed in units of 8 × 8 pixel blocks while taking in the macro block in order from the upper left to the lower right.

In MPEG, as shown in FIG.
First, the input moving image is divided into a large number of 8 × 8 pixel blocks by the block dividing unit 11, and the encoding process is performed serially while being cut out in units of one block. First, the input video image of the first block is subjected to motion compensation difference processing (MC-SUB) by the subtractor 12, and a difference from a prediction image signal obtained by prediction is obtained as a prediction residual signal. As described above, the motion compensation difference processing for obtaining the prediction residual signal is performed by motion compensation (MC; MotionCompe).
nsation), and is called motion compensation pixel difference processing (MC-SUB). Next, a discrete cosine transform (DCT; Discrete Cosine Tr) is applied to the prediction difference signal by a discrete cosine transform unit (DCT) 13.
DCT coefficient data is obtained. The DCT coefficient data is quantized (Q; Quantized) by a quantization unit (Q) 14, and then sent to a variable-length coding unit (VLC) 15 to perform variable-length coding (VLC) together with motion vector information. VLC; Variavl
e Length Coding), assembled into an encoded bit stream of a predetermined format, and sent to a transmission path.

The quantized DCT coefficient data is
Inverse quantization unit (IQ) 16, inverse discrete cosine transform unit (ID
CT) 17 and inverse quantization (IQ; Inverse Quantize), which is a process opposite to the process of the quantization unit (Q) 14 and the discrete cosine transform unit (DCT) 13.
r) and the inverse discrete cosine transform (IDCT; Invert)
se Discrete Cosine Transf
orm) is sequentially received, and is added to the predicted image signal by a motion compensation addition process (MC-ADD) by the adder 18 to restore the image signal of the original block. The restored image signal is stored in the frame memory 19 as a locally decoded signal. The process of restoring the residual signal to the original image signal by adding to the predicted image signal in this manner is called a motion compensation pixel addition process (MC-ADD) in motion compensation (MC). .

When macroblock data of a screen temporally different from the screen stored in the frame memory 19 is input, the motion detection unit (ME) 20 performs motion estimation (ME). By comparing the input macroblock with the stored reference screen, a search for a motion vector or the like is performed, thereby selecting an encoding mode and creating a predicted image signal.

The above processing is repeatedly executed serially in units of 8 × 8 pixels, and when the processing of all six blocks included in one macroblock is completed, the next macroblock data is fetched and the same processing is repeated. . The switches S1 and S2 are used for switching the encoding mode, and in the INTER mode for performing the inter-frame prediction encoding of encoding the residual signal between the prediction image and the input image as described above. Switch S
1 is off, the switch S2 is on, and in the INTRA mode for performing intra-frame encoding, the switch S1 is on and the switch S2 is off.

On the decoding device side, as shown in FIG.
The coded bit stream received from the transmission path is subjected to variable length decoding (VL) by a variable length decoding unit (VLD) 21.
D; Variable Length Decodin
g), each of the plurality of blocks in each macroblock is subjected to an inverse quantization unit (IQ) 22 and an inverse discrete cosine transform unit (I
DCT) 23, motion compensation addition processing section (MC-ADD) 2
4, the inverse quantization process (IQ), the inverse discrete cosine transform process (IDCT), and the motion compensation addition process (MC-ADD) are performed to obtain a decoded image. The decoded image is sent to the monitor via the video output interface 26 and is stored in the frame memory 26.

By the way, in the case of encoding a video taken by a camera and transmitting the encoded video to a decoding device, real-time encoding is required. For example, when the input screen size is 176 horizontal pixels × 144 vertical pixels, the total number of macro blocks is 99, and the number of blocks is 594.
In order to encode this image in real time at 10 frames per second, the time that can be spent for encoding one macroblock is 1.01 ms.

When the above processing is performed only by, for example, a digital signal processor (DSP), it is necessary to improve the operation speed in order to perform the above encoding processing in real time. The improvement of the calculation speed can be realized by adopting a multi-DSP configuration or the like. However, considering that it is mounted on a portable information terminal or the like that requires a small size and low power consumption, such a configuration in which the arithmetic unit is made redundant increases the size of the device, increases the cost, and above all, increases the power consumption. It is not suitable for inviting.

[0011] That is, low power consumption is the most required item in a small device such as a portable information terminal, and it is necessary to realize an image coding processing device with a low operating frequency.

[0012]

For the above reasons, as a method of realizing an image coding apparatus on a small terminal, a part of each processing of coding is constituted by a dedicated circuit, and control of the dedicated circuit is performed together with other processing. It is preferable to configure a small LSI in combination with a CPU for performing software. In this case, it is necessary to keep the operating frequency of the small LSI at a relatively low value. This is because, when the operating frequency is increased, the power consumption is increased accordingly.

As described above, in order to encode an image having a screen size of 176 pixels horizontally by 144 pixels vertically in 10 frames per second in real time, it can be used to encode one macroblock. Time is 1.01
Since this is m seconds, for example, if this is to be realized at a processing speed of 33 MHz, the maximum number of cycles that can be applied to one macroblock is only 33333 cycles. This value is not sufficient in consideration of a normal operation amount required for processing one macroblock.

Therefore, conventionally, a small LS with low power consumption is used.
If an encoding device is to be configured using I, it is necessary to reduce the overall processing amount by reducing the screen size or reducing the frame rate, which causes a problem that image quality is reduced.

[0015] The present invention has been made in view of such circumstances, and enables efficient encoding / decoding of an image even at a low operating frequency, thereby achieving both a sufficient image quality and low power consumption. It is an object of the present invention to provide a simple image encoding / decoding device.

[0016]

In order to solve the above-mentioned problems, an image encoding apparatus according to the present invention performs an encoding process on input data composed of a plurality of image block data each composed of a plurality of pixels in each of vertical and horizontal directions. A first to an n-th encoding processing means for performing the following, and the first to the n-th encoding processing means process the image block data in a first to an n-th order, and A control unit for controlling each of the encoding processing units so that the first to n-th encoding processing units perform processing on different image block data in parallel with each other.

In this image coding apparatus, the processing necessary for the coding process is divided into first to n-th divided processes in a time series, and each of the divided coding processes is constituted by a dedicated circuit or the like. Respectively assigned to a plurality of independent first to n-th encoding processing means. These encoding units operate in a pipeline under the control of the control unit, and process the image block data in the first to n-th order while sequentially inputting and processing the image block data. Thus, a plurality of different image block data are simultaneously processed by different encoding processing units. In this way, the first to n-th encoding processing units perform the division encoding processing on different image block data in parallel, so that the image encoding processing can be performed efficiently even at a low operating frequency. Also, as compared with a conventional configuration in which a plurality of arithmetic processing units for performing the same processing are provided in a redundant manner and the same encoding processing is simultaneously performed on a plurality of blocks, the apparatus size is reduced by the amount of no redundancy. Therefore, it is possible to realize an encoding device that is optimal for mounting on devices requiring low power consumption such as portable information terminals.

Further, according to the present invention, the processing time of each processing performed in parallel by the first to n-th encoding processing means is variably set according to a plurality of image block data to be processed in parallel. Features.

In general, when parallel processing is performed by pipeline operation, a fixed time is allocated to each stage. However, in image coding processing, processing time varies depending on input image data. In the transform (IDCT) process and the inverse quantization (IQ) process, when the input data value is zero, the output is also zero, so that there is no need to perform the calculation process, and the process ends immediately. Is variable, it is possible to reduce the time required for the entire encoding process.

Such a variable setting of the processing time of each stage is performed by the control means for each of the first to n-th encoding processes performed in parallel by the first to n-th encoding processes. This is realized by determining whether or not the operation of each of the encoding processing units is completed by acquiring an end flag or the like, and performing control to shift to the next divided encoding process when the operation of all the encoding units is detected to be completed. This makes it possible to control each processing time so as to match the longest processing among the simultaneously operating processes.

Further, according to the present invention, the processing by the first to n-th encoding processing means includes, in order from 1, a motion compensation processing,
It is characterized by discrete cosine transformation processing, quantization and inverse quantization processing, inverse discrete cosine transformation processing, and motion compensation pixel addition processing. In this way, by integrating several divisional encoding processes and assigning them to one encoding processing means, it is possible to make the processing time of the parallel processing almost the same and optimize the parallel operation. It becomes possible. Further, the processing by the first to n-th encoding processing means is as follows:
The motion compensation process, discrete cosine transform and quantization process, inverse quantization and inverse discrete cosine transform process, and motion compensation pixel addition process may be performed in order from 1.

Further, according to the present invention, in an apparatus having both an image encoding function and a decoding function, a first method for performing encoding processing on input data composed of a plurality of image block data each composed of a plurality of pixels in each of vertical and horizontal directions. To n-th processing means, and at the time of encoding, the first to n-th processing means processes the image block data in the first to n-th order, and The processing means controls the respective processing means so as to perform processing on image block data different from each other in parallel, and at the time of decoding, each of the encoded pixel blocks is encoded using a part of the first to n-th processing means. Data is processed in a predetermined order for decoding, and a part of the first to n-th processing means used for decoding performs processing on image block data different from each other in parallel. Characterized by comprising a control means for controlling each of said processing means so.

As described above, by using a part of the processing means used for the decoding process also for the decoding, it is possible to reduce the size of the apparatus.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, an image encoding / decoding device according to a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the image encoding / decoding device according to the first embodiment. This image encoding / decoding device is an MPEG having error tolerance in a wireless environment.
4 [1] One-chip LSI that supports Visual Simple Profile and has both image coding and decoding functions
It is implemented as a CODEC. This image encoding / decoding device has an operating frequency of 33 MHz and a width of 176 pixels ×
It is configured so that an image having a screen size of the QCIF standard of 144 pixels vertically can be encoded in 10 frames per second in real time.

Although MPEG4 has a structure that is resistant to transmission errors, the processing when an error occurs is left to the decoding side, so the image quality depends on the concealment processing in the decoder. The present image encoding / decoding device is made to operate by downloading a program from the outside so that error processing can be improved.

That is, as shown in FIG. 1, the present image encoding / decoding apparatus comprises a controller 31 composed of a RISC processor and a group of hardware modules controlled by the controller 31. .

The hardware modules include a DMA controller (DMAC) 32 for performing a DMA transfer between each hardware and an external working memory 40, and a video interface for exchanging data with an external camera or display. (VIDEO-I / F) 33, a discrete cosine transform (DCT) 34 for performing a discrete cosine transform (DCT) process, and an inverse discrete cosine transform (IDCT) 35 for performing an inverse discrete cosine transform (IDCT) process. , A motion detection unit (ME) 36 for performing motion detection (ME) processing such as motion vector detection and encoding mode selection, and a motion compensation pixel addition process (MC-ADD) and a motion compensation pixel difference process (MC-SUB) Motion compensation unit (MC-A
DD / SUB) 37, a variable length coding unit (VLC) 38 for performing variable length coding (VLC) processing, and a variable length decoding unit (VLD) 39 for performing variable length decoding (VLD) processing. Have been.

The controller 31 includes, as functional modules realized by a computer program, an encoding / decoding control unit (Enc / Dec) 311 for controlling the entire encoding and decoding operations, and a DMA controller (DMAC) 32 A DMA control unit 312 for controlling the DMA transfer function of, and a quantization / inverse quantization processing unit (Q / IQ) 313 for performing quantization (Q) and inverse quantization (IQ) processing are provided.

That is, the main functions realized by the software are the hardware modules 32-38.
Overall control and quantization (Q) in the encoding / decoding process
And an inverse quantization (IQ) process, insertion of a synchronization code for error tolerance, syntax processing by reversible VLC, and the like. In the encoding / decoding process, all other processes except the quantization (Q) and inverse quantization (IQ) processes, that is, discrete cosine transform (DCT),
Inverse discrete cosine transform (IDCT), motion detection (ME),
Processes requiring the most processing amount for encoding / decoding signal processing such as motion compensation (MC), variable length code (VLC), and variable length decoding (VLD) are performed by independent dedicated hardware modules 34 to 38, respectively. Has been realized.

In this system configuration, since the DCT processing, IDCT processing, MC processing, and quantization / dequantization processing necessary for encoding / decoding are performed in independent blocks, a motion compensation unit (MC-ADD) is used. / SUB) 37,
Discrete cosine transform unit (DCT) 34, quantization / inverse quantization processing unit (Q / IQ) 313, inverse discrete cosine transform unit (I
By performing the pipeline operation of the DCT 35, these processes can be simultaneously performed on a plurality of different image blocks constituting a macroblock. In this case, the motion compensation unit (MC-ADD / SUB) 3
7. Block data exchange among the discrete cosine transform unit (DCT) 34, the quantization / inverse quantization processing unit (Q / IQ) 313, and the inverse discrete cosine transform unit (IDCT) 35 is shared among them. This is performed via the memory 40 that is present.

The present inventor has studied the processing amount required for processing block data of 8 × 8 pixels. As a result, DCT and IDCT have a processing of about 1500 each.
Cycles, quantization and inverse quantization up to about 1600
Cycle and motion compensation processing are about 700 each for addition and difference processing.
It was a cycle.

Therefore, considering parallel processing so that each processing time becomes substantially the same, when encoding, DCT processing, IDCT processing, Q and IQ processing, and motion compensation (MC) processing are divided. Can be. FIG. 2 shows a pipeline configuration in the case where the above processing is performed in parallel on each image block of 8 × 8 pixels.

In FIG. 2, four luminance blocks (Y0-Y) in an arbitrary macro block (MBn) are arranged in the vertical direction.
Y3) and two color difference blocks (Cb, Cr) are shown as processing target block data, and each stage of the pipeline is shown in the horizontal direction.

In the stage 0, the DCT processing for the luminance block Y0 and the MC processing (M
C-SUB) are performed in parallel.

In stage 1, Q and IQ processing are sequentially performed on the luminance block Y0, and in parallel with this, DCT processing on the luminance block Y1 and MC processing (MC-SUB) on the luminance block Y2 are performed. .

In the following stage 2, the luminance block Y0
Processing and Q and IQ of the luminance block Y1
The processing, the DCT processing for the luminance block Y2, and the MC processing (MC-SUB) for the luminance block Y3 are performed in parallel.

Subsequently, in stage 3, the luminance block Y0
In parallel with the MC processing (MC-ADD) for the luminance block Y1, the IDCT processing for the luminance block Y1 and the luminance block Y2
, The DCT process for the luminance block Y3, and the MC process (MC-SUB) for the color difference block Cb.

In the subsequent stage 4, the luminance block Y1
In parallel with the MC processing (MC-ADD) for the luminance block Y2, the IDCT processing for the luminance block Y2 and the luminance block Y3
Q and IQ processing, DCT processing of the color difference block Cb,
MC processing (MC-SUB) of the color difference block Cr is performed.

Subsequently, in stage 5, the luminance block Y2
In parallel with the MC processing (MC-ADD) on the luminance block Y3, the IDCT processing on the luminance block Y3 and the chrominance block Cb
Q and IQ processing and DCT processing of the color difference block Cr are performed.

During these stages 0-5,
The next macro block (M
Bn + 1) is being subjected to motion detection processing (ME).

Subsequently, in stage 6, the luminance block Y3
In parallel with the MC processing (MC-ADD), the IDCT processing of the color difference block Cb and the Q and IQ processing of the color difference block Cr are performed. When the MC processing (MC-ADD) for the luminance block Y3 is completed, the processing by the motion compensation unit (MC-ADD / SUB) 37 is performed by the MC processing (MC-MC) for the luminance block Y0 in the next macroblock (MBn + 1). −ADD), and this processing is performed by the IDCT processing of the color difference block Cb and the color difference block Cr.
Is performed in parallel with the Q / IQ processing.

In the following stage 7, the color difference block Cb
In parallel with the MC processing (MC-ADD), the IDCT processing of the color difference block Cr is performed. The color difference block C
When the IDCT processing of r is completed, in this stage 7,
The MC processing (MC-ADD) of the color difference block Cr is continuously performed.

In this stage 7, the encoding mode (INT) for the next macroblock (MBn + 1) is set.
RA / INTER) is determined by the motion detection unit (ME) 36.

As described above, the luminance blocks (Y0-Y
6) consisting of 3) and color difference blocks (Cb, Cr) are sequentially shifted by one stage each,
SUB processing, DCT processing, Q / IQ processing, IDCT processing, and MC-ADD processing are performed. Thus, a series of encoding processes for all six blocks in one macroblock is completed in eight stages from stage 0 to stage 7.

As described above, taking into account that DCT and IDCT require about 1500 cycles for processing, quantization and inverse quantization together require a maximum of about 1600 cycles, and motion compensation processing requires about 700 cycles for addition and difference processing. ,
When the encoding process is performed serially for each block as in the related art, the encoding process for one macroblock takes about 37000 cycles at the maximum. However, in the present embodiment, the parallel processing by the pipeline is performed. Approximately 13
The encoding process of one macroblock can be completed in 000 cycles.

In this embodiment, the motion detector (M
E) For processing by 36, MC-A within one stage
Controls such as performing both DD and MC-SUB, and performing following the IDCT in the final stage 7, are performed in a shorter time than MC-ADD and MC-SUB compared to other processes. Therefore, the overall processing time is further reduced.
Therefore, excluding such MC processing, in the pipeline operation of the present embodiment, the total number of pipeline stages T required for the encoding processing of all image block data to be processed is equal to the number of image block data to be processed. Is N and the number of pipeline stages is K, T = N + K−1
The relationship established. This means that in the example of FIG.
6, K = 3, which means that the pipeline processing is completed in a total of eight stages.

In general, when parallel processing is performed by a pipeline operation, a time required for each process stage is generally assigned a fixed time. However, in image coding processing, a time is required in accordance with input image data. The time required for the processing is different. For example, in the case of the IDCT processing and the IQ processing, when the input data value is zero, the output is also zero, so that it is not necessary to perform the calculation processing. Therefore, if a fixed time is allocated, when the input contains many zero values, a state occurs in which the input is simply waited without doing anything.

In order to avoid such a situation, in the present embodiment, the motion compensation unit (MC-ADD / SUB) 37, the discrete cosine transform unit (DCT) 34, and the quantization / inverse quantization processing unit (Q / IQ) 313, inverse discrete cosine transform unit (IDC
T) 35, each time one block of processing is completed, an end flag indicating the completion is returned to the controller 31. The controller 31 acquires all the end flags of the processes operating simultaneously. At this point, control to move to the next stage is performed. Accordingly, each processing stage has a variable time, and the above-described processing cycle can be further reduced.

The decoding process is also performed in parallel by a pipeline. This is shown in FIG.

In the decoding process, as shown in FIG. 3, six blocks including a luminance block (Y0-Y3) and a chrominance block (Cb, Cr) are sequentially subjected to IQ processing, IDCT processing while being delayed by one stage. Processing, MC
-ADD processing is performed. As a result, a series of decoding processes for all six blocks in one macroblock is completed in seven stages from stage 0 to stage 6. Also,
In the final stage 6, the IDCT process for Cr and M
C-ADD processing is sequentially performed. Therefore, MC-ADD
Excluding the processing, the number of pipeline stages becomes K = 2, so that the above equation, T = N + K−1, holds.

Next, the control operation of the encoding process by the controller 31 will be described with reference to the flowcharts of FIGS.

First, before entering the pipeline stage from stage 0, the start of the MC-SUB process for Y0 is instructed to the motion compensator (MC-ADD / SUB) 37 (step S1). Then, when the end flag is obtained from the motion compensation unit (MC-ADD / SUB) 37 (step S2), the process shifts from the stage 0 to the pipeline stage.

In stage 0, the start of the DCT process for Y0 is instructed to discrete cosine transform unit (DCT) 34 (step S3), and the MC-to-YT1 DCT process is started.
The start of the SUB processing is performed by the motion compensation unit (MC-ADD / SU).
B) An instruction is given to 37 (step S4). When the end flags are obtained from both the discrete cosine transform unit (DCT) 34 and the motion compensation unit (MC-ADD / SUB) 37 (steps S5 to S7), the process proceeds to stage 1.

In stage 1, the Q / IQ processing for Y0 is sequentially performed by a quantization / dequantization processing unit (Q / I
Q) 313 is instructed (step S8), and Y1
Start of the DCT process for the discrete cosine transform unit (DC
T) 34 (step S9), and the start of the MC-SUB process for Y2 is further started by the motion compensation unit (MC-AD).
D / SUB) 37 (step S1)
0). Then, a quantization / inverse quantization processing unit (Q / IQ) 3
When the end flags are obtained from all of the discrete cosine transform unit (DCT) 34 and the motion compensation unit (MC-ADD / SUB) 37 (steps S11 to S14), the process proceeds to stage 2.

In the stage 2, the start of the IDCT process for Y0 is instructed to the inverse discrete cosine transform unit (IDCT) 35 (step S15), and the Q and IQ processes for Y1 are sequentially performed. / Inverse quantization processing unit (Q / IQ) 313 (step S16),
The start of the DCT process for Y2 is instructed to the discrete cosine transform unit (DCT) 34 (step S17), and the start of the MC-SUB process for Y3 is also started by the motion compensation unit (M
C-ADD / SUB) 37 is instructed (step S18). Then, an inverse discrete cosine transform unit (IDC
T) 35, quantization / inverse quantization processing unit (Q / IQ) 31
3. When the end flags are obtained from all of the discrete cosine transform unit (DCT) 34 and the motion compensation unit (MC-ADD / SUB) 37 (steps S19 to S23), the process proceeds to stage 3.

In stage 3, MC-AD for Y0
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S24) and Y1
Is instructed to the inverse discrete cosine transform unit (IDCT) 35 (step S2).
5), the quantization / dequantization processing unit (Q / IQ) 313 is instructed to sequentially perform the Q and IQ processing on Y2 (step S26), and the DCT processing on Y3 is started by the discrete cosine transform unit. (DCT) 34 is instructed (step S27). Motion compensation unit (MC-ADD / SUB)
When the end flag is acquired from the subroutine 37 (steps S28, S
32), the start of the MC-SUB process for Cb is instructed to the motion compensation unit (MC-ADD / SUB) 37 (step S33). Thereafter, an inverse discrete cosine transform unit (IDCT) 35 and a quantization / inverse quantization processing unit (Q / I
Q) When end flags are obtained from all of the 313, the discrete cosine transform unit (DCT) 34, and the motion compensation unit (MC-ADD / SUB) 37 (steps S29 to S31, S
34, S35), and proceeds to the stage 4 in FIG.

In stage 4, MC-AD for Y1
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S36) and Y2
Is instructed to the inverse discrete cosine transform unit (IDCT) 35 (step S3).
7), the quantization / dequantization processing unit (Q / IQ) 313 is instructed to sequentially perform Q and IQ processing on Y3 (step S38), and the DCT processing on Cb is started by the discrete cosine transform unit (DCT) 34 is instructed (step S39). Motion compensation unit (MC-ADD / SUB)
When the end flag is obtained from the subroutine 37 (steps S36, S
44), the start of the MC-SUB processing for Cr is instructed to the motion compensation unit (MC-ADD / SUB) 37 (step S45). Thereafter, an inverse discrete cosine transform unit (IDCT) 35 and a quantization / inverse quantization processing unit (Q / I
Q) When the end flag is obtained from each of the 313, the discrete cosine transform unit (DCT) 34, and the motion compensation unit (MC-ADD / SUB) 37 (steps S41 to S43,
S 46, S 47), and proceed to stage 5.

In stage 5, MC-AD for Y2
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S48) and Y3
Is instructed to the inverse discrete cosine transform unit (IDCT) 35 (step S4).
9), the quantization / dequantization processing unit (Q / IQ) 313 is instructed to sequentially perform Q and IQ processing on Cb (step S50), and the DCT processing on Cr is started by the discrete cosine transform unit (DCT) 34 is instructed (step S51). Then, a motion compensation unit (MC-ADD /
SUB) 37, inverse discrete cosine transform unit (IDCT) 3
5. When an end flag is obtained from each of the quantization / inverse quantization processing unit (Q / IQ) 313 and the discrete cosine transform unit (DCT) 34 (steps S52 to S56), the process proceeds to stage 6.

In stage 6, MC-AD for Y3
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S57) and Cb
Is instructed to the inverse discrete cosine transform unit (IDCT) 35 (step S5).
8) Further, the quantization / inverse quantization processing unit (Q / IQ) 313 is instructed to sequentially perform Q and IQ processing on Cr (step S59). The motion compensator (MC-
When the end flag is obtained from the (ADD / SUB) 37 (steps S60 and S63), the start of the MC-SUB process for Y0 of the next macroblock is started by the motion compensation unit (MC-A).
DD / SUB) 37 (step S6)
4). Thereafter, an inverse discrete cosine transform unit (IDCT) 3
5. When the end flag is obtained from each of the quantization / inverse quantization processing unit (Q / IQ) 313 and the motion compensation unit (MC-ADD / SUB) 37 (steps S61, S62,
S65, S66), and proceed to stage 7.

In stage 7, MC-AD for Cb
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S67), and
Is instructed to the inverse discrete cosine transform unit (IDCT) 35 (step S6).
8). When the end flag is obtained from each of the motion compensation unit (MC-ADD / SUB) 37 and the inverse discrete cosine transform unit (IDCT) 35 (steps S69 to S71), C
r is started by the motion compensation unit (MC
-ADD / SUB) 37 (step S72). Then, a motion compensation unit (MC-ADD / SU)
B) When the end flag is obtained from 37 (step S7)
3), proceed to stage 0 of the next macroblock.

Next, the control operation of the decoding process by the controller 31 will be described with reference to the flowcharts of FIGS.

In stage 0, the start of the IQ processing for Y0 is instructed to the quantization / inverse quantization processing unit (Q / IQ) 313 (step S81). When the end flag is obtained from the quantization / dequantization processing unit (Q / IQ) 313 (step S82), the process proceeds to stage 1.

In stage 1, the start of the IDCT process for Y0 is instructed to the inverse discrete cosine transform unit (IDCT) 35 (step S83), and the start of the IQ process for Y1 is determined by the quantization / inverse quantization unit. (Q / I
Q) 313 is instructed (step S84). And
Inverse discrete cosine transform (IDCT) 35 and quantization /
When the end flag is obtained from both of the inverse quantization processing unit (Q / IQ) 313 (steps S85 to S87), the process proceeds to stage 2.

In stage 2, MC-AD for Y0
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S88), and the start of the IDCT process for Y1 is determined by the inverse discrete cosine transform unit (IDC).
T) 35 (step S89), and the start of the IQ processing for Y2 is determined by the quantization / dequantization processing unit (Q /
IQ) 313 (step S90). When the end flag is obtained from each of the motion compensation unit (MC-ADD / SUB) 37, the inverse discrete cosine transform unit (IDCT) 35, and the quantization / inverse quantization processing unit (Q / IQ) 313 (steps S91 to S94). Then, the process proceeds to stage 3.

In stage 3, MC-AD for Y1
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S95), and the start of the IDCT process on Y2 is performed by the inverse discrete cosine transform unit (IDC).
T) 35 (step S96), and the start of the IQ processing for Y3 is determined by the quantization / inverse quantization processing unit (Q /
IQ) 313 (step S97). When the end flag is obtained from each of the motion compensation unit (MC-ADD / SUB) 37, the inverse discrete cosine transform unit (IDCT) 35, and the quantization / inverse quantization processing unit (Q / IQ) 313 (steps S98 to S101). Then, the process proceeds to stage 4 in FIG.

In stage 4, MC-AD for Y2
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S102), and the start of the IDCT processing for Y3 is performed by the inverse discrete cosine transform unit (ID).
CT) 35 (step S103), and C
The start of the IQ processing for b is instructed to the quantization / dequantization processing unit (Q / IQ) 313 (step S10).
4). When the end flag is obtained from each of the motion compensation unit (MC-ADD / SUB) 37, the inverse discrete cosine transform unit (IDCT) 35, and the quantization / inverse quantization processing unit (Q / IQ) 313 (steps S105 to S108). , To stage 5.

In stage 5, MC-AD for Y3
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S109), and the start of the IDCT process on Cb is performed by the inverse discrete cosine transform unit (ID).
CT) 35 (step S110), and C
The start of IQ processing for r is instructed to the quantization / inverse quantization processing unit (Q / IQ) 313 (step S11).
1). When the end flag is obtained from each of the motion compensation unit (MC-ADD / SUB) 37, the inverse discrete cosine transform unit (IDCT) 35, and the quantization / inverse quantization processing unit (Q / IQ) 313 (steps S112 to S115). , To the stage 6.

In stage 6, MC-AD for Cb
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S116), and the start of the IDCT process on Cr is performed by the inverse discrete cosine transform unit (ID).
CT) 35 (step S117).
When the end flag is obtained from each of the motion compensation unit (MC-ADD / SUB) 37 and the inverse discrete cosine transform unit (IDCT) 35 (steps S118 to S120), the Cr
Start of the MC-ADD process for the motion compensation unit (MC-
ADD / SUB) 37 (step S12)
1). Then, a motion compensation unit (MC-ADD / SUB) 3
When the end flag is obtained from No. 7 (step S112),
Move to stage 0 of the next macroblock.

As described above, according to the first embodiment,
During the encoding process, the motion compensation subtraction process (MC-SU
B), discrete cosine transform (DCT), quantization and inverse quantization (Q, IQ), inverse discrete cosine transform (ID
CT) and motion-compensated pixel addition processing (MC-ADD) are performed in parallel. At the time of decoding, the inverse quantization processing (I
Q), inverse discrete cosine transform processing (IDCT), and motion compensation pixel addition processing (MC-ADD) are performed in parallel.

In the first embodiment, as described above, since the processing time of each processing performed in parallel is variable depending on the type of processing and the input image, the processing time of each stage of the pipeline is reduced. After waiting for the end of the encoding or decoding process for the longest processing time, the process proceeds to the next stage. Therefore, the processing time required for one pipeline processing is the sum of the longest processing time in each pipeline stage.

When the encoding and decoding processes are performed using a CPU, the operating frequency of the CPU must be set to an appropriate value. For example, if the processing time per image block is 17000 cycles, the number of image blocks is 99, and the number of frames per second is 10, CP
The operating frequency of U must be greater than about 17 MHz beside these. When performing bi-directional transmission, it is necessary to perform encoding and decoding at the same time, so the operating frequency required for encoding and the decoding frequency required for decoding, as well as variable-length code processing and input / output processing, etc. The sum is the CPU operating frequency.

Here, the case where the quantization / inverse quantization processing section (Q / IQ) 313 is realized by software has been described, but the quantization / inverse quantization processing section (Q / IQ) 313 has been described.
Can be realized as a dedicated hardware module.

(Second Embodiment) FIG. 8 shows a second embodiment of the present invention.
1 shows a configuration of an image encoding / decoding device according to an embodiment.

This image encoding / decoding apparatus differs from the first embodiment shown in FIG. 1 only in the mode of division of the encoding / decoding processing.
Processing and Q processing are performed, and IQ processing and IDCT processing can be executed in the same stage.

That is, the image encoding / coding of the second embodiment
In the decoding device, the quantization / inverse quantization processing unit (Q /
Instead of the IQ) 313, the discrete cosine transform unit (DCT) 34, and the inverse discrete cosine transform unit (IDCT) 35, a discrete cosine / quantization unit (DCT / Q) 44 for performing DCT processing and Q processing, and an IDCT processing And an inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45 for performing IQ processing. These discrete cosine / quantization units (D
CT / Q) 44 and an inverse discrete cosine / inverse quantization unit (I
The DCT / IQ) 45 is realized by dedicated hardware modules independent of each other.

FIG. 9 shows the state of the pipeline operation during the encoding process.

As shown, the luminance blocks (Y0-Y
6) consisting of 3) and color difference blocks (Cb, Cr) are sequentially shifted by one stage each,
SUB processing, DCT / Q processing, IQ / IDCT processing, M
C-ADD processing is performed.

That is, in the stage 0, the DCT process and the Q process are sequentially performed on the luminance block Y0, and the MC process (MC-SUB) is performed on the luminance block Y1 in parallel.

Subsequently, in stage 1, the luminance block Y0
, The IQ and IDCT processes are sequentially performed, and in parallel with this, the DCT process and the Q process are sequentially performed on the luminance block Y1, and the MC process (MC-SUB) is further performed on the luminance block Y2.

Subsequently, in stage 2, the luminance block Y0
In parallel with the MC processing (MC-ADD), the IQ and IDCT processing of the luminance block Y1, the DCT and Q processing of the luminance block Y2, and the MC processing (MC-SUB) of the luminance block Y3 are performed.

Subsequently, in stage 3, the luminance block Y1
In parallel with the MC processing (MC-ADD), the IQ processing and the IDCT processing of the luminance block Y2, the DCT and Q processing of the luminance block Y3, and the MC processing (MC-SUB) of the color difference block Cb are performed.

Subsequently, in stage 4, the luminance block Y2
In parallel with the MC processing (MC-ADD), the IQ processing and the IDCT processing of the luminance block Y3, the DCT and Q processing of the chrominance block Cb, and the MC processing (MC-SUB) of the chrominance block Cr are performed.

Also, during these stages 0 to 4,
A motion detection process (ME) for the next macroblock is performed by the motion detection unit (ME) 36.

Subsequently, in stage 5, the luminance block Y3
In parallel with the MC processing (MC-ADD), the IQ and IDCT processing of the color difference block Cb and the DCT and Q processing of the color difference block Cr are performed. When the MC processing (MC-ADD) for the luminance block Y3 is completed, the processing by the motion compensation unit (MC-ADD / SUB) 37 is performed by the MC processing (MC-ADD) for the luminance block Y0 in the next macroblock. Is switched to the IQ and IDCT processing of the color difference block Cb, and the color difference block Cr.
DCT and Q processing are performed in parallel.

Subsequently, in stage 6, the color difference block Cb
In parallel with the MC processing (MC-ADD), IQ and IDCT processing of the color difference block Cr are performed. When the IDCT processing of the color difference block Cr is completed, the stage 6
The MC processing (MC-ADD) of the chrominance block Cr is continuously performed.

In this stage 6, the encoding mode (INTRA / INTER) for the next macroblock is
R) is determined by the motion detector (ME) 36.

Also in this example, since the number of pipeline stages is K = 2 except for the MC processing, the equation T = N + K-1 holds.

FIG. 10 shows the state of the pipeline operation during the decoding process.

In the decoding process, as shown, the luminance block (Y0-Y3) and the chrominance block (Cb, Cr)
Are sequentially processed with IQ, IDCT processing and MC-ADD processing with a delay of one stage each. Thus, a series of decoding processes for all six blocks in one macroblock is completed in six stages from stage 0 to stage 5. In the last stage 5, IQ / IDCT processing and MC-ADD processing for Cr are sequentially performed. Therefore, since the number of pipeline stages K becomes 1 except for the MC-ADD process, the equation T = N + K−
1 holds.

Next, the control operation of the encoding process by the controller 31 will be described with reference to the flowcharts of FIGS.

First, before entering the pipeline stage from stage 0, the start of the MC-SUB process for Y0 is instructed to the motion compensation unit (MC-ADD / SUB) 37 (step S201). Then, when the end flag is obtained from the motion compensation unit (MC-ADD / SUB) 37 (step S202), the processing shifts from the stage 0 to the pipeline stage.

In stage 0, DCT and Q for Y0
Processing starts with discrete cosine / quantization unit (DCT / Q) 4
4 (step S203) and Y
1 is started by the motion compensation unit (MC
-ADD / SUB) 37 (step S204). Then, a discrete cosine / quantization unit (DCT)
/ Q) 44 and motion compensator (MC-ADD / SUB)
37 (step S2).
05 to S207), and proceeds to stage 1.

In stage 1, IQ and ID for Y0
The start of the CT processing is performed by the inverse discrete cosine / inverse quantization unit (IDC).
T / IQ) 45 (step S20)
8) The start of DCT and Q processing for Y1 is instructed to discrete cosine / quantization section (DCT / Q) 44 (step S209), and the start of MC-SUB processing for Y2 is started by motion compensation section (MC-Q). ADD / SUB) 37 (step S210). Inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45, discrete cosine / quantization unit (DCT / Q) 44, and motion compensation unit (M
When the end flag is obtained from each of the C-ADD / SUB) 37 (steps S211 to S214), the stage 2
Move to

In stage 2, MC-AD for Y0
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S215), and Y
The start of IQ and IDCT processing for 1 is instructed to the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45 (step S216), and the start of DCT and Q processing for Y2 is performed by the discrete cosine / quantization unit (DCT / IDT). Q) 44 is instructed (step S217). Motion compensation unit (MC
−ADD / SUB) 37 (steps S219 and S223), the MC for Y3 is obtained.
The start of the SUB processing is performed by the motion compensation unit (MC-ADD / SU).
B) An instruction is given to 37 (step S218). When the end flag is obtained from each of the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45, the discrete cosine / quantization unit (DCT / Q) 44, and the motion compensation unit (MC-ADD / SUB) 37 (step S220) ~ S222, S
224), and proceed to stage 3.

In stage 3, MC-AD for Y1
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S225), and Y
The start of the IQ and IDCT processing for the signal 2 is instructed to the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45 (step S226), and the start of the DCT and Q processing for Y3 is performed by the discrete cosine / quantization unit (DCT / IQ). Q) 44 is instructed (step S227). Motion compensation unit (MC
−ADD / SUB) 37 (steps S229 and S233), the MC for Cb is obtained.
The start of the SUB processing is performed by the motion compensation unit (MC-ADD / SU).
B) An instruction is given to 37 (step S228). When the end flag is obtained from each of the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45, the discrete cosine / quantization unit (DCT / Q) 44, and the motion compensation unit (MC-ADD / SUB) 37 (step S230) ~ S232, S
234), and shifts to the stage 4 in FIG.

In stage 4, MC-AD for Y2
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S235), and Y
The start of the IQ and IDCT processing for Cb.3 is instructed to the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45 (step S236), and the start of DCT and Q processing for Cb is performed by the discrete cosine / quantization unit (DCT / IQ). Q) 44 is instructed (step S237). Motion compensation unit (MC
−ADD / SUB) 37 (steps S239 and S243), the MC for Cr—
The start of the SUB processing is performed by the motion compensation unit (MC-ADD / SU).
B) An instruction is given to 37 (step S238). When the end flag is obtained from each of the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45, the discrete cosine / quantization unit (DCT / Q) 44, and the motion compensation unit (MC-ADD / SUB) 37 (step S240) ~ S242, S
244), and proceed to stage 5.

In stage 5, MC-AD for Y3
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S245), and C
The start of IQ and IDCT processing for b is instructed to the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45 (step S246), and the start of DCT and Q processing for Cr is performed by the discrete cosine / quantization unit (DCT / IQ). Q) 44 is instructed (step S247). Motion compensation unit (MC
When the end flag is obtained from the (-ADD / SUB) 37 (steps S248 and S251), the start of the MC-SUB for the next macroblock Y0 is determined by the motion compensation unit (MC).
-ADD / SUB) 37 (step S252). Inverse discrete cosine / inverse quantization unit (IDCT /
IQ) 45, discrete cosine / quantization unit (DCT / Q) 4
4, and an end flag is obtained from each of the motion compensation unit (MC-ADD / SUB) 37 (step S24).
9, S250, S253, S254), and proceeds to stage 6.

In stage 6, MC-AD for Cb
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S255), and C
The start of IQ and IDCT processing for r is instructed to the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45 (step S256). Motion compensation unit (MC-ADD / SU
B) 37 and inverse discrete cosine / inverse quantization unit (IDCT)
/ IQ) 45 (steps S257 to S259), the MC-
The start of the ADD processing is performed by the motion compensation unit (MC-ADD / SU).
B) An instruction is given to 37 (step S260). Then, when the end flag is obtained from the motion compensation unit (MC-ADD / SUB) 37 (step S261), the process proceeds to stage 0 of the next macroblock.

Next, the control operation of the decoding process by the controller 31 will be described with reference to the flowcharts of FIGS.

In stage 0, IQ and ID for Y0
The start of the CT processing is performed by the inverse discrete cosine / inverse quantization unit (IDC).
T / IQ) 45 (step S30)
1). Inverse discrete cosine / inverse quantization unit (IDCT / IQ)
When the end flag is obtained from 45, the process proceeds to stage 1.

In stage 1, MC-AD for Y0
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S303), and Y
The start of the IQ and IDCT processing for 1 is instructed to the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45 (step S304). Motion compensation unit (MC-ADD /
SUB) 37 and an inverse discrete cosine / inverse quantization unit (ID)
When the end flag is obtained from both the CT / IQ) 45 (steps S305 to S307), the process proceeds to stage 2.

In stage 2, MC-AD for Y1
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S308), and Y
The start of the IQ and IDCT processing for 2 is instructed to the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45 (step S309). Motion compensation unit (MC-ADD /
SUB) 37 and an inverse discrete cosine / inverse quantization unit (ID)
When the end flag is acquired from both of the CT / IQ) 45 (steps S310 to S312), the process proceeds to stage 3.

In stage 3, MC-AD for Y2
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S313) and Y
The start of the IQ and IDCT processing for No. 3 is instructed to the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45 (step S314). Motion compensation unit (MC-ADD /
SUB) 37 and an inverse discrete cosine / inverse quantization unit (ID)
When the end flag is acquired from both the CT / IQ) 45 (steps S316 to S319), the stage 4 in FIG.
Move to

In stage 4, MC-AD for Y3
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S320), and C
The start of IQ and IDCT processing for b is instructed to the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45 (step S321). Motion compensation unit (MC-ADD /
SUB) 37 and an inverse discrete cosine / inverse quantization unit (ID)
When the end flag is acquired from both of the CT / IQ) 45 (steps S322 to S324), the process proceeds to stage 5.

In stage 5, MC-AD for Cb
The start of D processing is performed by the motion compensation unit (MC-ADD / SUB) 3
7 (step S325), and C
The start of IQ and IDCT processing for r is instructed to the inverse discrete cosine / inverse quantization unit (IDCT / IQ) 45 (step S326). Motion compensation unit (MC-ADD /
SUB) 37 and an inverse discrete cosine / inverse quantization unit (ID)
When the end flag is acquired from both of the CT / IQ) 45 (steps S327 to S329), the MC-
The start of the ADD processing is performed by the motion compensation unit (MC-ADD / SU).
B) 37 is instructed (step S330). And
When the end flag is obtained from the motion compensator (MC-ADD / SUB) 37 (step S331), the process proceeds to stage 0 of the next macro block.

Also in the second embodiment, as described above, since the processing time of each processing performed in parallel is variable depending on the processing type and the input image, the processing time of each stage of the pipeline is different. After waiting for the end of the encoding or decoding process for the longest processing time, the process proceeds to the next stage. Therefore, the processing time required for one pipeline processing is the sum of the longest processing time in each pipeline stage.

When the encoding and decoding processes are performed using the CPU, the operating frequency of the CPU must be set to an appropriate value. For example, if the processing time per image block is 17000 cycles, the number of image blocks is 99, and the number of frames per second is 10, CP
The operating frequency of U must be greater than about 17 MHz beside these. When performing bi-directional transmission, it is necessary to perform encoding and decoding at the same time, so the operating frequency required for encoding and the decoding frequency required for decoding, as well as variable-length code processing and input / output processing, etc. The sum is the CPU operating frequency.

[0109]

As described above, according to the present invention,
A series of processes for encoding / decoding are respectively divided into a plurality of dedicated modules, and the modules control the processes on different image block data in parallel, so that even at a low operating frequency, It is possible to efficiently perform image encoding / decoding processing. In addition, since a redundant configuration is not adopted and only one module having the same function exists, the size of the device can be reduced,
Low power consumption can be achieved, and an encoding / decoding device optimal for mounting on a device requiring low power consumption such as a portable information terminal can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an image encoding / decoding device according to a first embodiment of the present invention.

FIG. 2 is a view showing an example of a pipeline operation at the time of encoding processing in the image encoding / decoding device of the first embodiment.

FIG. 3 is a view showing an example of a pipeline operation at the time of decoding processing in the image encoding / decoding device of the first embodiment.

FIG. 4 is a flowchart illustrating a part of a control procedure of an encoding processing operation in the image encoding / decoding device according to the first embodiment.

FIG. 5 is a flowchart illustrating the remaining part of the control procedure of the encoding processing operation in the image encoding / decoding device according to the first embodiment.

FIG. 6 is a flowchart illustrating a part of a control procedure of a decoding processing operation in the image encoding / decoding device according to the first embodiment.

FIG. 7 is a flowchart for explaining the remaining part of the control procedure of the decoding processing operation in the image encoding / decoding device according to the first embodiment.

FIG. 8 is a block diagram showing a configuration of an image encoding / decoding device according to a second embodiment of the present invention.

FIG. 9 is a diagram showing an example of a pipeline operation at the time of encoding processing in the image encoding / decoding device according to the second embodiment.

FIG. 10 is a view showing an example of a pipeline operation at the time of decoding processing in the image encoding / decoding device of the second embodiment.

FIG. 11 is a flowchart illustrating a part of a control procedure of an encoding processing operation in the image encoding / decoding device according to the second embodiment.

FIG. 12 is a flowchart for explaining the remaining part of the control procedure of the encoding processing operation in the image encoding / decoding device according to the second embodiment.

FIG. 13 is a flowchart illustrating a part of a control procedure of a decoding processing operation in the image encoding / decoding device according to the second embodiment.

FIG. 14 is a flowchart for explaining the remaining part of the control procedure of the decoding processing operation in the image encoding / decoding device according to the second embodiment.

FIG. 15 is a block diagram for explaining a conventional image encoding process.

FIG. 16 is a block diagram for explaining a conventional image decoding process.

FIG. 17 is a diagram illustrating a configuration of a macroblock of an image.

[Explanation of symbols]

 31 controller 32 DMA controller (DMAC) 33 video interface unit (VIDEO-I / F) 34 discrete cosine transform unit (DCT) 35 inverse discrete cosine transform unit (IDCT) 36 motion detector (ME) 37 ... Motion compensation unit (MC-ADD / SUB) 38 ... Variable length coding unit (VLC) 39 ... Variable length decoding unit (VLD) 311 ... Encoding / decoding control unit (Enc / Dec) 312 ... DMA control unit 313: quantization / inverse quantization processing unit (Q / IQ) 44: discrete cosine / quantization unit (DCT / Q) 45: inverse discrete cosine / inverse quantization unit (IDCT / IQ)

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Michiyo Morimoto 70, Yanagicho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Yanagicho Plant Co., Ltd.

Claims (17)

[Claims] A first to an n-th encoding processing means for performing an encoding process on input data composed of a plurality of image block data each composed of a plurality of pixels in each of a vertical direction and a horizontal direction; Encoding processing means processes the image block data in a first to n-th order, and the first to n-th encoding processing means performs processing on different image block data in parallel. An image encoding apparatus comprising: a control unit for controlling each of the encoding processing units. 2. The processing time of each processing performed in parallel by the first to n-th encoding processing means is variably set according to the plurality of image block data to be processed in parallel. The image encoding device according to claim 1. 3. The control means determines whether or not each of the first to n-th encoding processing means has completed the operation for each of the processing performed in parallel by the first to n-th encoding processing means. 3. The image encoding apparatus according to claim 2, wherein the control is performed so as to make a determination and, when the operation end of all encoding processing means is detected, to proceed to the next divided encoding processing. 4. The processing by the first to n-th encoding processing means includes, in order from 1, motion compensation processing, discrete cosine transformation processing, quantization and inverse quantization processing, inverse discrete cosine transformation processing, motion compensation pixel The image encoding device according to claim 1, wherein the image encoding device performs an addition process. 5. The processing by the first to n-th encoding processing means includes, in order from 1, motion compensation processing, discrete cosine transformation and quantization processing, inverse quantization and inverse discrete cosine transformation processing,
2. A motion compensation pixel addition process.
The image encoding device according to any one of claims 1 to 3. 6. A first to n-th decoding processing means for performing a decoding process on input data composed of a plurality of encoded image block data each composed of a plurality of pixels vertically and horizontally, and The n-th decoding processing means processes the respective pixel block data in the first to n-th order, and the first to n-th decoding processing means performs processing on different image block data from each other. Control means for controlling each of the decoding processing means so as to perform the processing in parallel. 7. The processing by the first to n-th decoding processing means is, in order from 1, an inverse quantization processing, an inverse discrete cosine transform processing, and a motion compensation pixel addition processing. An image decoding device according to claim 1. 8. The processing according to claim 6, wherein the processing by the first to n-th decoding processing means is, in order from 1, the inverse quantization, the inverse discrete cosine transform processing, and the motion compensation pixel addition processing. Image decoding device. 9. A first to n-th processing means for performing an encoding process on input data composed of a plurality of image block data each composed of a plurality of pixels vertically and horizontally, and the first to n-th encoding means at the time of encoding. Processing means for processing each of the image block data in the first to n-th order, and the first to n-th processing means perform processing for different image block data in parallel with each other. At the time of decoding, a part of the first to n-th processing means is used to process each of the encoded pixel block data in a predetermined order for decoding. And control means for controlling each processing means so that a part of the first to n-th processing means used for decoding performs processing on different image block data in parallel with each other. You Image encoding / decoding apparatus. 10. The image encoding / decoding apparatus according to claim 1, wherein each of the image block data is composed of 8 pixels vertically × 8 pixels horizontally. 11. An image processing apparatus comprising: first to n-th encoding processing means for performing encoding processing on input data composed of a plurality of image block data each composed of a plurality of pixels vertically and horizontally; And a control means for controlling the pipeline operation so that the first to n-th encoding processing means perform processing on different image block data in parallel with each other. The total number of pipeline stages required for the encoding processing of all target image block data is determined by the number of image block data to be processed and the number of pipeline stages by the first to n-th encoding processing units. An image encoding device, wherein the remaining value is obtained by subtracting 1 from the sum. 12. A first to n-th decoding processing means for performing decoding processing on input data comprising a plurality of encoded image block data each composed of a plurality of pixels vertically and horizontally, and Control means for causing the first to n-th decoding processing means to perform a pipeline operation, and controlling the pipeline operation such that the first to n-th decoding processing means performs processing on different image block data in parallel with each other; The number of all pipeline stages required for the decoding processing of all the image block data to be processed is determined by the number of image block data to be processed and the pipeline by the first to n-th decoding processing means. An image decoding apparatus characterized in that the remaining value is obtained by subtracting 1 from the sum of the number of stages. 13. An image processing apparatus comprising: first to n-th encoding processing means for performing encoding processing on input data composed of a plurality of image block data each composed of a plurality of pixels vertically and horizontally; And a control means for controlling the pipeline operation so that the first to n-th encoding processing means perform processing on different image block data in parallel.
The processing time required for the encoding processing of one pipeline is the first to n-th in each pipeline stage.
An image encoding apparatus characterized in that it is the sum of the longest processing time among the processing times required for the encoding processing by the encoding processing means. 14. An image processing apparatus comprising: first to n-th encoding processing means for performing encoding processing on input data composed of a plurality of image block data each composed of a plurality of pixels in each of the vertical and horizontal directions; And a control means for controlling the pipeline operation so that the first to n-th encoding processing means perform processing on different image block data in parallel. The operating frequency required to perform the encoding process on the image block data is the processing time required to perform the encoding process on all the image block data to be processed, the number of the image block data, and the unit time. An image coding apparatus, which is set based on a product of the number of frames of an image to be displayed per hit. 15. An image processing apparatus comprising: first to n-th decoding processing means for performing a decoding process on input data composed of a plurality of image block data each composed of a plurality of images in each of vertical and horizontal directions; And control means for controlling the pipeline operation so that the first to n-th decoding processing means perform processing on different image block data in parallel with each other. The processing time required for the decoding processing of one pipeline is the sum of the longest processing time among the processing times required for the decoding processing by the first to n-th decoding processing means in each pipeline stage. An image decoding device, comprising: 16. An image processing apparatus comprising: first to n-th decoding processing means for performing a decoding process on input data including a plurality of image block data each composed of a plurality of pixels in the vertical and horizontal directions; control means for causing the n decoding processing means to perform a pipeline operation, and controlling the pipeline operation so that the first to n-th decoding processing means perform processing on different image block data in parallel. The operating frequency required to perform the decoding process on all the image block data, the processing time required to perform the decoding process on all the image block data to be processed, the number of the image block data, An image decoding apparatus, which is set based on a product of the number of frames of an image to be displayed per unit time. 17. An image processing apparatus comprising: first to n-th encoding / decoding processing means for performing encoding / decoding processing on input data composed of a plurality of image block data each composed of a plurality of images each vertically and horizontally, The first to n-th encoding / decoding processing means are operated in a pipeline, and the first to n-th encoding / decoding processing means perform the geography on different image block data in parallel. Control means for controlling the line operation, the operating frequency required to perform the encoding and decoding processing on all the fish block data, the operating frequency required to perform the encoding processing, An image encoding / decoding apparatus, which is set based on a sum of an operating frequency required for performing a decoding process and an operating frequency including at least a variable-length code process.