JPH11252478A - Automatic frequency tuning circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress characteristic drops and image quality drop, scarcely affecting the temperature dependence of AFT voltage by performing frequency conversion of a receiving input signal of a television signal into a video intermediate signal, producing a detection reference signal that synchronizes with a carrier signal of the video intermediate signal, detecting a color signal from a video signal and performing feedback control of an oscillation frequency of a 1st voltage-controlled oscillator circuit. SOLUTION: A counter circuit 34 is reset by a 2nd pulse signal P2 outputted from a pulse signal generation circuit 32, pulse signals that pass through a gate circuit 33 in a period determined by a 1st pulse signal P1 outputted from the circuit 32 are counted, and n-bit count data are outputted. A register circuit 35 fetches the n-bit count data inputted from a counter circuit 34 with a timing of a 3rd pulse signal P3 outputted from the circuit 32. A D/A conversion circuit 36 performs D/A conversion of the count data inputted from the circuit 35 and outputs it as an AFT voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency tuning circuit (AFT circuit), and more particularly to an automatic frequency tuning circuit (AFT circuit) for generating an AFT voltage supplied for feedback control of an oscillation frequency of a local oscillation circuit in an AFT control loop. The present invention relates to an AFT voltage generation circuit, and is used for a video detection system circuit such as a television (TV) receiver and a video playback device with a built-in TV tuner.

[0002]

2. Description of the Related Art In a TV receiver, high frequency (RF)
The allowable frequency drift of the output frequency of the local oscillation circuit is specified so that the image quality of the video signal display image is not impaired when the output frequency of the local oscillation circuit of the stage fluctuates (in the case of a color TV receiver, For example, about ± 50 KHz).

In order to suppress the output frequency of such a local oscillation circuit within an allowable drift range and eliminate the need for fine adjustment at the time of tuning, a loop for performing feedback control of the output frequency of the local oscillation circuit is used. AFT circuit is provided.

FIG. 6 shows an example of a conventional AFT circuit. A video intermediate frequency (PIF) signal obtained by frequency-converting the received input signal (a branch signal thereof) is directly input to a first input terminal of the multiplication circuit 61, and the PIF signal is input to a second input terminal of the multiplication circuit 61. It is input via a resistor 62. Then, a carrier wave component included in the output signal of the multiplication circuit 61 is extracted to generate an AFT voltage, and the output frequency of a local oscillation circuit (not shown) is feedback-controlled.

In order to adjust the center position (the position where the AFT control loop becomes stable) of the relationship (AFT characteristic) between the frequency of the carrier component and the AFT voltage to a predetermined center frequency, the LC resonance circuit 63 operates as follows. The second of the multiplication circuit 61
Connected to input terminal.

However, in the configuration shown in FIG. 6, it is difficult to incorporate the LC resonance circuit 63 into an integrated circuit for a receiver, and the LC resonance circuit 63 is externally connected to the TV receiver. An adjustment step (for example, LC resonance circuit 6) for adjusting the center position of the AFT characteristic at a time before shipment from a factory.
3 manually adjusts the rotational position of the magnetic core of the coil L by a driver). This has a problem in automation (no adjustment) of the manufacturing process of the TV receiver.

FIG. 7 shows a phase locked loop (PLL) for an existing video detection circuit as another example of the conventional AFT circuit.
Shows an AFT circuit using a part of the AFT circuit. The PIF signal is input to the first input terminal of the multiplication circuit 71, and the multiplication circuit 7
An output signal of a voltage controlled oscillator (PIF-VCO) 72 included in a PLL for a video detection circuit is input to a second input terminal of the first. The output signal of the multiplying circuit 71 is smoothed by a loop filter 73 and the PIF-VCO 72
Control voltage. Then, the control voltage of the PIF-VCO 72 is amplified by an AFT amplifier circuit 74 to be an AFT voltage, and the output frequency of a local oscillation circuit (not shown) is feedback-controlled.

An LC resonance circuit (not shown) for adjusting the oscillation frequency characteristic of the PIF-VCO 72
It is externally connected to the V receiver. However, in the configuration shown in FIG. 7, when the oscillation frequency characteristic of the PIF-VCO 72 has temperature dependence, the AFT voltage also has temperature dependence, and the AFT characteristic is reduced. In the worst case, The standard of the AFT characteristic is not satisfied, and the image quality is reduced.

[0009]

As described above, the conventional AFT circuit which amplifies the control voltage of the PIF-VCO included in the PLL for the video detection circuit and uses it as the AFT voltage has the oscillation frequency characteristic of the PIF-VCO. If it has temperature dependence, the AFT voltage will also have temperature dependence,
There is a problem that the AFT characteristic is deteriorated, and in the worst case, the standard of the AFT characteristic is not satisfied, and the image quality is deteriorated.

The present invention has been made to solve the above-mentioned problem. Even when the oscillation frequency characteristic of the PIF-VCO has a temperature dependency, the AFT voltage has almost no influence on the temperature dependency. It is an object of the present invention to provide an automatic frequency tuning circuit capable of suppressing deterioration in characteristics and image quality.

[0011]

SUMMARY OF THE INVENTION An automatic frequency tuning circuit according to the present invention comprises a first voltage for a local oscillator circuit for generating a high frequency signal for frequency-converting a television input signal into a video intermediate signal. A control oscillator circuit, included in a phase locked loop circuit for a video detection circuit for detecting a video signal from the video intermediate signal, for generating a video carrier signal for generating a detection reference signal synchronized with a carrier signal of the video intermediate signal. A second voltage oscillation circuit for generating a color subcarrier signal included in a phase locked loop circuit of a color signal processing system for detecting a color signal from the video signal;
An automatic frequency tuning device for digitally processing an output signal of the second voltage oscillation circuit and an output signal of the third voltage oscillation circuit for feedback controlling an oscillation frequency of the first voltage controlled oscillation circuit; An automatic frequency tuning voltage generation circuit provided for generating the control voltage.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a tuner section and a part of a PIF stage of a TV receiver including an AFT circuit according to a first embodiment of the present invention.

In the tuner section, 11 is a high frequency (RF) amplifier circuit for amplifying a received input signal, 12 is a local oscillator circuit composed of a VCO, 13 is an output signal of the RF amplifier circuit 11 and an output signal of the local oscillator circuit 12. Mixed with PI
This is a frequency conversion circuit that generates an F signal component.

In the PIF stage, reference numeral 14 denotes a PIF signal component (for example, about 58.75 M) from the output signal of the tuner section.
Hz), a PIF filter for amplifying an output signal of the PIF filter 14, and a PIF amplifier 1 for amplifying an output signal of the PIF filter 14.
5 is a video detection circuit for detecting a video signal from the output signal of No. 5.

In the PLL circuit 20 for the video detection circuit,
21 is a PIF amplification circuit for amplifying the PIF signal input, 22
Is a PIF-VCO for generating two detection reference signals synchronized with the PIF carrier signal, and 23 is an automatic phase control (A
PC) a detection circuit, and 24 is an APC filter. The above P
The two detection reference signals generated by the IF-VCO 22 are P
The first detection reference signal has the same phase as that of the IF carrier signal (the phase is 0 °) and the second detection reference signal has a phase different by 90 °.

The APC detection circuit 23 includes the PPC
An amplifier circuit 21 for amplifying the input signal obtained by branching the output signal of the IF amplifier circuit 15 at a constant gain and the same phase, and a second signal output from the amplifier circuit 21 and a phase output from the PIF-VCO 22 differing by 90 degrees from each other. A multiplication circuit for mixing (multiplying) the detection reference signal and generating an APC detection output signal corresponding to a phase error and a frequency error is used.

The low-frequency component of the detection output signal of the APC detection circuit 23 is smoothed by the APC filter 24 and supplied as a control voltage of the PIF-VCO 22. That is, the APC detection circuit 23, the APC filter 2
4. The PIF-VCO 22 forms a PLL circuit,
And controlling the output signal of the VCO 22 to have a predetermined phase at the same frequency as the PIF carrier signal.

The video detection circuit 16 receives 0 ° from the PIF-VCO 22 whose phase is controlled by the PLL circuit.
The video signal is detected from the PIF signal based on the phase detection reference signal.

It is to be noted that the synchronization state of the PLL circuit is determined based on the result of determining whether or not the average level of the video detection output signal is equal to or higher than a predetermined reference level. In order to stabilize the pull-in operation, the time constant of the APC filter 24 in the PLL circuit is increased, and when the synchronous pull-in operation is not performed, the time constant of the APC filter 24 in the PLL circuit is increased. A pull-in detection circuit (not shown) for controlling the constant to be small is provided.

Further, an AFT voltage generation circuit 30 for generating a control voltage (AFT voltage) for feedback controlling the oscillation frequency of the local oscillation circuit 12 is provided. The AFT voltage generation circuit 30 is provided with the PIF-VC
O22 output signal and P of the color signal processing system of the TV receiver
The output signal of the VCO 17 for generating a color subcarrier signal used in an LL loop (not shown) is partially digitalized so as to be digitally processed.

The local oscillation circuit 12, the frequency conversion circuit 1
3, PIF filter 14, PIF amplification circuit 15, APC
The detection circuit 20 and the AFT voltage generation circuit 30
Constructs a control loop.

Here, the VC for generating the chrominance subcarrier signal is used.
O17 is a signal having a relatively high frequency accuracy using, for example, a quartz oscillator (for example, about 3.58 in the NTSC system).
MHz ± 1 KHz). Also,
The frequency pull-in range of the PIF-VCO 22 is usually, for example, about ± 1.5 MHz.

Next, the AFT voltage generation circuit 30 in FIG. 1 will be described. Reference numeral 31 denotes a 1 / N frequency dividing circuit for reducing the frequency of a signal into which the output signal of the PIF-VCO 22 branches and is input to 1 / N. This 1 / N frequency dividing circuit 3
1 is selectively provided for simplifying a circuit configuration when performing signal processing in a digital circuit in a subsequent stage.

Reference numeral 32 denotes a VCO for generating the chrominance subcarrier signal.
17 output pulse signals having relatively high frequency accuracy are branched and input, and the first pulse signal P1 to the third pulse signal P3 having relatively high timing are generated based on the input signals. It is a generating circuit.

The reference numeral 33 denotes a first pulse signal P1 supplied from the pulse signal generating circuit 32,
A gate circuit for permitting / prohibiting the passage of the output signal (pulse signal) of the / N frequency dividing circuit 31.

Numeral 34 denotes a counter circuit. The second pulse signal P2 supplied from the pulse signal generating circuit 32 is input to a reset input terminal R, and the pulse signal passed through the gate circuit 33 is used as a clock input as a count input. Edge C
K and outputs n-bit count data.

Numeral 35 denotes an n-bit register circuit, to which n-bit count data is inputted from the counter circuit 34 and a third signal supplied from the pulse signal generating circuit 32 is provided.
When the pulse signal P3 is input, the count data is fetched.

Numeral 36 denotes an n-bit digital / analog (D
/ A) a conversion circuit for receiving output data (count data) of the register circuit 35 and performing D / A conversion on the input data.

Next, an outline of the operation of the AFT voltage generation circuit 30 will be described. The counter circuit 34 resets the gate circuit 33 within a period determined by the first pulse signal P1 output from the pulse signal generation circuit 32 after being reset by the second pulse signal P2 output from the pulse signal generation circuit 32. The passed pulse signals are counted, and n-bit count data is output.

The register circuit 35 receives the n-bit count data input from the counter circuit 34 at the timing of the third pulse signal P3 output from the pulse signal generation circuit 32. Then, the D / A conversion circuit D / A converts the count data input from the register circuit 35 and outputs it as an AFT voltage.

In the operation described above, the PIF-V
A value obtained by counting a signal obtained by dividing the output signal of the CO 22 by the 1 / N frequency dividing circuit 31 during a predetermined period determined by the first pulse signal P1 corresponds to the magnitude of the frequency of the carrier component of the PIF signal. And the count value and D /
The relationship with the A-converted AFT voltage indicates the AFT characteristic, and in the stable state of the AFT control loop, the final value counted during the fixed period substantially corresponds to the center frequency of the AFT characteristic.

In the above operation, the pulse signals P1 and P3 having relatively high precision timing generated by the pulse signal generation circuit 32 based on the output signal of the VCO 17 for generating the color subcarrier signal having relatively high frequency precision. Thus, the AFT voltage is generated by performing D / A conversion of the count data in which the pulse signal is counted during the counting period and the fetch timing, and the level fluctuation width of the AFT voltage is determined by the fluctuation width of the oscillation frequency of the local oscillation circuit 12. For example, it can be suppressed to about ± 10 KHz. Since this value is sufficiently narrower than the allowable fluctuation range of the oscillation frequency of the local oscillation circuit 12, which is about ± 50 KHz, the AFT control operation can be reliably performed.

FIG. 2 shows the AFT voltage generation circuit 30 shown in FIG.
1 shows a specific example. In this AFT voltage generation circuit, a gate decode circuit 32 using, for example, a 9-bit counter corresponding to the pulse signal generation circuit 32 in FIG.
Is a signal output from the VCO 17 for generating the color subcarrier signal, for example, about 4.43 MHz (44
(33619 KHz) A signal having a relatively high frequency accuracy of about ± 1 KHz is input, and the first pulse signal P1
To generate the third pulse signal P3. In this case, the pulse width of the first pulse signal P1 is constant, and the second pulse signal P2 and the third pulse signal P3 are generated at a timing related to the pulse width of the first pulse signal P1.

For example, a 1/4 frequency divider 31 corresponding to the 1 / N frequency divider 31 in FIG. 1 divides the signal output from the PIF-VCO 22 by 1/4 to generate a clock signal. AND circuit 33 corresponding to gate circuit 33 in FIG.
Means that the pulse width period of the first pulse signal P1 is 1
The clock signal from the ４ frequency dividing circuit 31 is passed.

The 8-bit counter 34 corresponding to the counter circuit 34 in FIG. 1 is reset by the second pulse signal P2 supplied from the gate decode circuit 32, and thereafter, is input from the AND circuit 33. A clock signal is counted, and a counter having a small number of bits is used to simplify a circuit configuration.

FIG. 3 shows a change in the count data value of the 8-bit counter 34. That is, this 8-bit counter has a count data value of 255 during the count operation.
After counting up to 0, an operation of returning to 0 and counting up again is performed.

For the reasons (1) and (2) described below, the 8-bit counter 34 operates as shown in FIG. 3 before the count-up operation (the second pulse). A counter capable of presetting to a predetermined preset value in advance (when reset by the signal P2) is used.

(1) The final value of the count data obtained by the counter 34 counting all the clock signals that have passed through the AND circuit 33 during the fixed pulse width period of the first pulse signal P1 is substantially equal to the center position of the AFT characteristic ( It is desirable to set a value corresponding to (a frequency position at which the AFT control loop becomes stable).

(2) Even if conditions such as the output frequency of the PIF-VCO 22 are changed, the counter 34
Is desirably set so that the final count value of the AFT characteristic becomes a value substantially corresponding to the center position of the AFT characteristic. In order to realize this, for example, a mask ROM 37 for preset data for storing appropriate preset value data for each of a large number of conditions is prepared.
7, data of an appropriate preset value is read for each condition and preset to the presettable counter.

The 8-bit register 35 corresponding to the register circuit 35 in FIG. 1 stores the 8-bit counter 34 according to the timing of the third pulse signal P3 (data load signal) supplied from the gate decode circuit 32.
Of the last count data.

The output characteristics of the AFT voltage are as follows.
For example, as shown in FIG. 4, although the characteristics are substantially linear in a frequency range within a predetermined range from the characteristic center frequency fo, the AFT voltage is limited (clamped) to a constant value of 0 V in a frequency range lower than the predetermined range. In a frequency range higher than the predetermined range, it is desirable to provide a characteristic such that the AFT voltage is limited (clamped) to a constant value of, for example, 5V.

In order to provide the above-described limit (clamp) characteristics, a data limit circuit 38 for monitoring the count data of the counter 34 and providing the limit characteristics is provided.

That is, the data limit circuit 38 receives the 8-bit output data of the register 35 and, in an area where the data content is lower than a predetermined range, applies the first output data to the first data.
The logic is such that the output data is limited to a second constant value and output in a region higher than the predetermined range, and the output data is output as it is when the data content is within a predetermined range. It is configured.

The output data of the data limit circuit 38 is D / A converted by the D / A conversion circuit 36. To simplify the circuit configuration of the D / A conversion circuit 36 and the data limit circuit 38, The D / A conversion circuit 36 is, for example, a 3-bit D / A conversion circuit, and the data limit circuit 38 is configured to perform data processing as described below.

That is, the data limit circuit 38 limits and outputs the lower 3 bits of the 8-bit output data in an area where the data content is lower or higher than a predetermined range, and outputs the data content when the data content is lower than a predetermined range. Within the range, the lower 3 bits of data are output as they are, and the D / A conversion circuit 36 converts the lower 3 bits of data to D
/ A conversion.

In this case, for example, as shown in FIG.
The data limit circuit 38 determines that the most significant bit (MSB) of the 8-bit count data is "1" and all four bits except the lower three bits are "1". If it is "0", the lower 3 bits of the 8-bit count data are output as output data as they are.

On the other hand, when the MSB of the 8-bit count data is "0", all the lower three bits are set to "0" and output as output data. The AFT voltage output from the D / A conversion circuit 36 after receiving the output data is limited (clamped) to a constant value of, for example, 5V.

When the MSB of the 8-bit count data is "1" and any of the 4 bits excluding the lower 3 bits is "1", all the lower 3 bits are set to "1". Set to “1” and output as output data. The AFT voltage output from the D / A conversion circuit 36 after receiving the output data is limited (clamped) to a constant value of, for example, 0V.

The D / A conversion circuit 36 changes to a level corresponding to a change in the contents of the lower 3 bits of the 8-bit count data. The AFT voltage changes in seven steps from 5 to 0 V, for example (about 0.7 V per step).

If the oscillation frequency changes by about 70 KHz per 1 V change of the control voltage input, the local oscillation circuit 12 changes the AFT voltage input from the D / A conversion circuit 36 by about one step, and the local oscillation circuit 12 changes by about 50 KHz. Change.

The pulse width of the first pulse signal P1 is, for example, 86.61 μs, and the frequency of the output signal of the PIF-VCO 22 is, for example, 58.75 MHz.
The frequency of the clock signal divided by / 4 is 14.6875
If the AFT control loop is in a stable state at almost the center position of the AFT characteristics, the first pulse is set by setting 140 as the preset value of the presettable counter 34 if the frequency is set to MHz. Signal P
The counter 34 counts all the clock signals (1272) that have passed through the AND circuit 33 during one fixed pulse width period, and the final value of the count data becomes 132.
In addition, the present invention provides an NTSC system, a PAL system, etc.
It is applicable to various TV systems.

[0052]

As described above, according to the present invention, the PIF
-Even if the oscillation frequency characteristic of the VCO has a temperature dependency, the
It is possible to provide an automatic frequency tuning circuit capable of suppressing deterioration in characteristics and deterioration in image quality.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a tuner section and a part of a PIF stage of a TV receiver including an AFT circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific example of an AFT voltage generation circuit in FIG.

FIG. 3 is a diagram showing a change in a count data value when an 8-bit counter is used as the counter circuit in FIG. 2;

4 is a diagram showing an example of an AFT voltage generation characteristic of the AFT voltage generation circuit in FIG.

FIG. 5 is a view shown for explaining an example of a limit characteristic of the data limit circuit in FIG. 2;

FIG. 6 is a block diagram showing an example of a conventional AFT circuit.

FIG. 7 is a block diagram showing another example of the conventional AFT circuit.

[Explanation of symbols]

 11: RF amplification circuit, 12: Local oscillation circuit (VCO), 13: Frequency conversion circuit, 14: PIF filter (for example, surface acoustic wave filter), 15: PIF amplification circuit, 16: Video detection circuit, 17: Color subcarrier VCO for signal generation, 20 PLL for video detection circuit, 21 PIF amplification circuit, 22 PIF-VCO, 23 APC detection circuit, 24 APC filter, 30 AFT voltage generation circuit, 31 1 / N Peripheral circuit, 32: pulse signal generation circuit, 33: gate circuit, 34: counter circuit, 35: register circuit, 36: D / A conversion circuit.

Claims (8)

[Claims] A first voltage-controlled oscillation circuit for a local oscillation circuit for generating a high-frequency signal for frequency-converting a reception input signal of a television signal into a video intermediate signal; and a video signal from the video intermediate signal. A second voltage oscillation circuit for generating a video carrier signal for generating a detection reference signal synchronized with a carrier signal of the video intermediate signal, which is included in a phase locked loop circuit for a video detection circuit for detecting, Third color generation subcarrier signal included in a phase locked loop circuit of a color signal processing system for detecting a color signal
And a digital circuit that digitally processes an output signal of the second voltage oscillation circuit and an output signal of the third voltage oscillation circuit, and feeds back an oscillation frequency of the first voltage controlled oscillation circuit. An automatic frequency tuning voltage generation circuit provided for generating an automatic frequency tuning control voltage for controlling the automatic frequency tuning control voltage. 2. The automatic frequency tuning circuit according to claim 1, wherein the automatic frequency tuning voltage generation circuit has first to third pulses having a predetermined timing based on an output signal of the third voltage oscillation circuit. A pulse signal generation circuit for generating a signal, and a pulse width supplied from the pulse signal generation circuit is controlled by a constant first pulse signal, and the passage of an output signal of the second voltage oscillation circuit is permitted / prohibited. A gate circuit, a second pulse signal supplied from the pulse signal generation circuit is input to a reset input terminal, a pulse signal passed through the gate circuit is input to a clock input terminal as a count input, and n bits are output to an output terminal. A counter circuit that outputs count data of n bits, and n-bit count data is input from the counter circuit and supplied from the pulse signal generation circuit. An n-bit register circuit that takes in the count data when a third pulse signal is input to a clock input terminal, and a digital / analog conversion circuit that performs digital / analog conversion on output data of the register circuit. Automatic frequency tuning circuit. 3. The automatic frequency tuning circuit according to claim 2, wherein said automatic frequency tuning voltage generation circuit further comprises:
1 / N to divide the output signal of the voltage oscillation circuit 1 / N
An automatic frequency tuning circuit comprising an N frequency dividing circuit, wherein an output signal of the 1 / N frequency dividing circuit is input to the gate circuit. 4. The automatic frequency tuning circuit according to claim 1, wherein said automatic frequency tuning voltage generation circuit comprises: a first pulse signal having a constant pulse width based on an output signal of said third voltage oscillation circuit; A pulse signal generation circuit for generating a second pulse signal and a third pulse signal at a timing related to the pulse width of the first pulse signal; and dividing the output signal of the second voltage oscillation circuit by 1 / N A 1 / N divider circuit for generating a clock signal, and a gate controlled by a first pulse signal supplied from the pulse signal generator circuit, for permitting / prohibiting passage of an output signal of the 1 / N divider circuit. A predetermined preset value data is preset at a timing of a second pulse signal supplied from the pulse signal generation circuit, and counts the number of pulse signals passing through the gate circuit. A presettable counter circuit that outputs n-bit count data to an output terminal; and a timing of a third pulse signal supplied from the pulse signal generation circuit, the input of n-bit count data from the counter circuit. 1. An automatic frequency tuning circuit, comprising: an n-bit register circuit that takes in the count data according to the data; and a digital / analog conversion circuit that performs digital / analog conversion on output data of the register circuit. 5. The automatic frequency tuning circuit according to claim 4, further comprising receiving n-bit output data of said register circuit, and limiting said output data to a first constant value in a region where the data content is lower than a predetermined range. An automatic frequency tuning circuit comprising a data limit circuit for limiting the output data to a second constant value in an area higher than the predetermined range. 6. The automatic frequency tuning circuit according to claim 5, further comprising: a data limit circuit configured to output lower m bits of n bits of output data in an area where the data content is lower or higher than a predetermined range. When the data content is within a predetermined range, the lower m-bit data is output as it is, and the digital / analog conversion circuit performs digital / analog conversion on the lower m-bit data. Automatic frequency tuning circuit. 7. The automatic frequency tuning circuit according to claim 5, wherein the presettable counter circuit counts all clock signals that have passed through the gate circuit during a period of a pulse width of the first pulse signal. An automatic frequency tuning circuit characterized in that preset value data is preset so that the final value of the count data becomes a value substantially corresponding to the center position of the AFT characteristic. 8. The automatic frequency tuning circuit according to claim 1, wherein the third voltage-controlled oscillation circuit has a higher frequency accuracy than the second voltage oscillation circuit. Generating an automatic frequency tuning circuit.