JPH11252203A - Digital signal transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To map an MPEG 2(moving picture experts group)-TS(transport stream) at an optional bit rate on a leased DS3 channel, to transmit the result and to reduce a scale of a realized circuit by decreasing a fixed delay in the signal transmission through the DS 3 channel. SOLUTION: The transmitter is provided with a storage circuit 1 that temporarily stores digital data from a data generator 6, an invalid data generating circuit 2 that generates invalid data, a storage state detection circuit 3 that detects a storage state of the storage circuit 1, and a mapping pattern control circuit 5. Then the control circuit 5 applies switching control to a changeover switch 4 to select an output of the invalid data generating circuit 2 or a read output from the storage circuit 1 to generate a transmission format where a band shared by a digital signal with respect to a transmission band is a little higher than an input bit rate and a transmission format where the band shared by the digital signal is a little lower and either of the two transmission formats is selected adaptively depending on a detection output denoting a storage state by the storage state detection circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission line having a band higher than the transmission rate of digital data to be transmitted, absorbing a difference in transmission rate, efficiently allocating a band, and transmitting a digital signal. The present invention relates to a digital signal transmission device.

[0002]

2. Description of the Related Art In recent years, image communication has become active due to an increase in network capacity / advanced image technology. Particularly for images, MPEG2 (Moving Picture Experts Groove) defined by the ISO / IEC 13818 standard.
The image compression technique called up) has spread widely and is rapidly spreading.

[0003] There are two types of transmission formats in MPEG2: Program Stream and Transport Stream (hereinafter referred to as TS), but the most widely used transmission media such as satellite digital broadcasting and terrestrial digital broadcasting are 18 types.
This is a TS composed of 8-byte fixed-length packets.

On the other hand, in communication, AT
M, LAN, dedicated lines (T1, DS3, etc.), etc. exist, and how to load the MPEG2-TS on these lines (hereinafter referred to as mapping) uses the lines for digital TV broadcasting. Important in doing so.

FIG. 12 shows a conventional apparatus for mapping and transmitting MPEG2-TS to a DS3 line which is widely used mainly in North America among the above lines. In FIG. 12, reference numeral 6 denotes an MPEG2-TS generation device, and reference numeral 34 denotes an MPEG ove.
r ATM mapping device, 35 is Physical Layer Converge
nce Protocol (PLCP) framing device, 7 is D
S3 line.

Next, the operation will be described. The MPEG2-TS generated by the MPEG2-TS generator 6 from a video source (not shown) such as a television signal is an MPEG2-TS.
It is sent to the over ATM mapping device 34.

[0007] The MPEG2-TS to ATM cell mapping device 34 divides and maps the 188-byte MPEG2-TS packet into a payload portion of a 48-byte ATM cell. The mapping method is the US ATM LAN
The ATM Forum, a standards organization, specifies the specifications (Aud
io / Visual Multimedia Services: Video on Demandv1.
1). According to this specification, two TS packets of 376 bytes have an ATM adaptation layer 5 (hereinafter, AAL).
384 bytes to which an 8-byte header defined by the above-mentioned method (5) is added is mapped to eight ATM cells. FIG. 13 shows the format of MPEG over ATM.

[0008] The MPEG2-TS mapped to the ATM cell as described above is sent to the PLCP framing device 35. ATM Fo on DS3 line
rum (ATM User-Network Inter
face Specification V3.1), which stipulates that 12 ATM cells are mapped per PLCP frame having a frame rate of 125 μs. MPE
G2-TS rate adjustment is performed by inserting idle cells into ATM cells. FIG. 14 shows DS3.
4 shows a PLCP frame structure.

[0009] As described above, the conventional apparatus uses the existing MPEG o.
ver By combining the ATM and PLCP DS3 frame format, MPEG2-TS is mapped to a DS3 line for transmission.

[0010]

The conventional transmission apparatus as described above has a two-stage process in which an MPEG2-TS is once mapped to an ATM cell, and then the ATM cell is mapped to a PLCP frame and transmitted over a DS3 line. However, there is a problem that the fixed delay is increased due to the above-mentioned process, and the circuit scale is increased due to more complicated format processing.

Also, two formats (ATM cell,
PLCP frame), the overhead increases, and MPEG2-TS that can be sent to the line bandwidth
However, there is a problem that the bit rate is limited, and the line use efficiency is deteriorated.

At the present time, MPEG2-TS is converted to DS
A method of directly mapping to three lines is not disclosed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has been developed in consideration of MPEG having an arbitrary bit rate.
2-TS can be efficiently mapped to a DS3 line and transmitted, and in signal transmission over a DS3 line, an MPEG having a small fixed delay and a small circuit size is realized.
An object is to provide a digital signal transmission device suitable as a 2-TS transmission device.

[0014]

A digital signal transmitting apparatus according to the present invention is a digital signal transmitting apparatus for transmitting digital data from a data generating apparatus for generating digital data of a predetermined bit rate through a digital transmission path having a higher bandwidth. In the signal transmission device, storage means for temporarily storing digital data from the data generation device, invalid data generation means for generating invalid data, accumulation state detection means for detecting the accumulation state of the storage means, Switching means for switching any of the output of the invalid data generating means and the storage means to the digital transmission path; and controlling the switching of the switching means to output the invalid data generating means and the read output from the storage means. The band occupied by the digital signal with respect to the transmission line band is determined by the input bit rate. Mapping pattern control means for generating a slightly higher transmission format and a slightly lower transmission format, and adaptively switching between the two transmission formats in accordance with the detection output indicating the accumulation state by the accumulation state detection means. It is assumed that.

Further, the mapping pattern control means is characterized in that a transmission format is generated in frame units that match the hierarchical structure of the digital transmission path.

Further, the mapping pattern control means generates a transmission format for inserting and removing invalid data in units of 1 byte.

Also, an identification signal generation means for generating an identification signal for identifying the two transmission formats, and an output from the identification signal generation means or an output from the invalid data generation means for switching to the switching means And a second switching means for outputting to the second transmission means, the mapping pattern control means switchingly controlling the second switching means to use a part of the invalid data in a transmission format. It is characterized by adding an identification signal for identifying a format.

The storage state detection means includes an upper limit value counter for counting a signal indicating an upper limit value when the remaining data amount of the storage means exceeds an upper limit value; A lower limit value counter that counts a signal indicating a lower limit value when the value falls below, and a determination unit that outputs a comparison determination result between the count value of these counters and a set value. The timing for switching the transmission format is determined based on the determination result.

Further, the accumulation state detecting means includes a sampling means for sampling the remaining amount of data in the storage means at fixed time intervals, a difference calculating means for calculating a difference between a current sampling value and a past sampling value, Determining means for determining a temporal displacement of the remaining amount of stored data in the storage means based on a value of the difference from the difference calculating means,
The mapping pattern control means determines a timing for switching the transmission format based on the comparison result.

The storage state detecting means includes an upper limit value counter for counting a signal indicating an upper limit value when the remaining data amount of the storage means exceeds an upper limit value; A lower limit value counter that counts a signal indicating a lower limit value when the value falls below, a sampling unit that samples the remaining amount of data in the storage unit at fixed time intervals, and a difference between a current sampling value and a past sampling value. The difference calculation means to be determined, and when the count value of the upper limit value counter reaches a predetermined value or more and the value of the difference takes a positive value, the accumulation state of the storage means is determined to be increasing and the lower limit value is determined. Determining means for determining that the accumulation status of the storage means is decreasing when the count value of the counter reaches a predetermined value or more and the value of the difference is a negative value. The mapping pattern control means are those based on the comparison determination result and determines the timing for switching the transmission format.

Further, an error correction code generating means for generating an error correction code from the digital data output from the data generation device, and one of the output from the error correction code generation means and the output from the invalid data generation means And a third switching means for switching the invalid data to a transmission format by controlling the switching of the third switching means. Is used to add an error correction code.

Further, the mapping pattern control means generates a transmission format in which invalid data is inserted uniformly over time.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 relates to the first embodiment of the present invention, in which MPEG2-TS is connected to DS3.
FIG. 2 is a configuration diagram of a digital signal transmission device that maps and transmits the transmission signal on a transmission path. In FIG. 1, 1 is an MPEG2-TS
Storage circuit, 2 is an invalid data generation circuit, 3 is an accumulation state detection circuit, 4 is a switch for switching between data output from the storage circuit 1 and invalid data output from the invalid data generation circuit 2, and 5 is an accumulation state detection circuit. This is a circuit that generates a mapping pattern to be described later based on the output of the circuit 3 and controls the changeover switch 4.

Next, the operation will be described. The DS3 line 7 assumed as a transmission path is 44.736 Mbit /
There are s bands, and a frame format as shown in FIG. 3 is defined (ANSI T1.107). DS3 is shown in FIG.
As shown in (1), a bit string of 4760 bits is defined as one frame, and the frame is divided into seven 680-bit blocks (hereinafter referred to as subframes). Further, each sub-frame is divided into eight 85-bit blocks. As shown in the figure, there are 54 bits (one bit per block) of overhead bits in one frame, and 4704 bits per frame can actually carry data.

On the other hand, what is assumed as the MPEG2-TS to be transmitted is the American Advanced Television System (ATSC).
stem committee) ATV (Advanced T
elevision) signal of 19.39 Mbit / s MP
EG2-TS. The TS is packetized every 188 bytes as described in the section of the related art.

The following description is based on the case where the DS3 line 7 is used for 19.
It is assumed that 39-Mbit / s MPEG2-TS is mapped. However, if the bit rate is equal to or less than the DS3 payload band, it should be noted that this method can be applied to a TS having an arbitrary speed.

The storage circuit 1 of FIG. 1 has 19.39 Mbi
MPE from the MPEG2-TS generator 6 at a speed of t / s
G2-TS is written. On the other hand, 44.736 Mbi
Data is read from the storage circuit 1 in order to put it on the DS3 line 7 of t / s, but it is 44.736 Mbit as it is.
When reading at / s, the data in the storage circuit 1 underflows due to the difference in transmission speed. Accordingly, the mapping pattern control circuit 5 inserts the invalid data output from the invalid data generating circuit 2 between the data as appropriate by the changeover switch 4 so that the storage circuit 1 does not cause underflow.

The mapping pattern control circuit 5 controls the changeover switch 4 to convert the DS3-frame into the MPEG2-T
A transmission format (hereinafter referred to as a mapping pattern) in which S and invalid data are distributed at a fixed ratio is generated. The mapping pattern is switched by the output of the accumulation state detection circuit 3 to adjust the transmission rate. The following is a description of this mapping pattern.

FIG. 2 shows a 19.39 Mb to DS3 frame.
It shows an MPEG2-TS mapping pattern of it / s. As described above, the payload portion in which information is put in the 4760-bit DS3 frame is 4704 bits. The TS is mapped using 8 frames as one unit (4704 bytes, hereinafter referred to as a large frame). The use of eight frames as one unit is described in 19.
This is because a break in mapping the MPEG2-TS of 39 Mbit / s is good. Of course, how many frames are treated as one unit can be arbitrarily set according to the rate of the TS to be transmitted.

The mapping pattern (a) is obtained by mapping 11 TS packets to one large frame. The TS rate at this time is obtained by the following equation. 44.736Mbit / s × 4704/4760 × 188 × 11/4704 = 19.
434357..Mbit / s

On the other hand, the mapping pattern (b) is obtained by mapping ten TS packets to one large frame. The TS rate at this time is similarly obtained by the following equation. 44.736Mbit / s × 4704/4760 × 188 × 10/4704 = 17.
6688..Mbit / s

Since the TS rate of the mapping pattern (a) is higher than the transmission side TS rate of 19.39 Mbit / s, if the reading is continued according to the pattern (a), the remaining amount of data in the storage circuit 1 underflows and the mapping pattern (b) )
Since the TS rate is lower than the rate on the transmitting side, if reading is continued in the pattern (b), the remaining amount of data in the storage circuit 1 overflows and data is lost.

Therefore, the storage state detection circuit 3 uses the storage circuit 1
The mapping pattern control circuit 5 controls the changeover switch 4 so that the data in the storage circuit 1 does not underflow or overflow by detecting the remaining data amount of the mapping patterns (a) and ( b)
Switch. In this way, by switching the two mapping patterns at appropriate timing, the bandwidth of the MPEG2-TS occupying the DS3 line can be changed.
The bit rate of the TS output from the generator 6 is set equal to the bit rate.

As described above, the mapping is controlled by the mapping pattern control circuit 5 according to the storage state of the storage circuit 1 by preparing a mapping higher and a mapping lower than the data rate of the MPEG2-TS transmitting side. MP at the same bit rate as the transmission speed of the
The EG2-TS can be put on the DS3 transmission line. Further, if the mapping pattern is known in advance on the receiving side, a TS can be easily extracted (invalid data is deleted) as long as only a DS3 frame can be detected, and the circuit on the receiving side can be simplified. Further, in the mapping pattern in such a configuration, since the TS packet and the DS3 frame are synchronized, if only the DS3 frame can be detected, there is no need to provide a TS packet header detection circuit on the receiving side, and the circuit on the receiving side can be simplified.

Embodiment 2 In the first embodiment,
In this example, eight DS3 frames are grouped and a TS is mapped. As another mapping example, DS3 is used.
An embodiment in which a TS is mapped to one frame will be described. This corresponds to the case where the DS31 frame is treated as one unit in the first embodiment. That is, in the second embodiment, the transmission pattern is generated by the mapping pattern control circuit 5 in frame units that match the hierarchical structure of the digital transmission path.

FIG. 4 shows a mapping pattern in such a case. Mapping pattern (a) is 1
This is obtained by mapping two TS packets to one DS3 large frame. The TS rate at this time is obtained by the following equation. 44.736Mbit / s × 4704/4760 × 188 * 2/588 = 28.2701
4..Mbit / s

On the other hand, the mapping pattern (b) is obtained by mapping one TS packet to one frame. The TS rate at this time is similarly obtained by the following equation. 44.736Mbit / s × 4704/4760 × 188/588 = 14.13507 ..
Mbit / s

As described above, the mapping pattern control circuit 5 controls the DS2-MPEG2-TS rate as in the first embodiment by generating mappings higher and lower than the transmission-side TS rate of 19.39 Mbit / s. can do. Further, since the mapping is performed in a small unit of one DS3 frame, the capacity of the storage circuit 1 can be reduced. In addition, as long as a DS3 frame structure can be established in a network hierarchical structure of a digital transmission path, a mapping pattern is guaranteed, so that the degree of freedom on a network is high.

Embodiment 3 In the first and second embodiments, the mapping pattern is a TS packet unit. However, as another mapping example, an embodiment in which an MPEG2-TS is mapped to a DS3 frame in a byte unit will be described. That is, in the third embodiment, the mapping pattern control circuit 5 generates a transmission format for inserting and removing invalid data in units of 1 byte.

FIG. 5 shows a mapping pattern in such a case. Mapping pattern (a) is D
This is obtained by mapping 258-byte MPEG2-TS data to the S3 frame. The TS rate at this time is 44.736 Mbit / s × 4704/4760 × 258/588 = 19.39813 ..
Mbit / s

On the other hand, the mapping pattern (b) is obtained by mapping 257 bytes of MPEG2-TS data in one frame, and the TS rate at this time is similarly obtained by the following equation. 44.736Mbit / s × 4704/4760 × 257/588 = 19.32294 ..
Mbit / s

As described above, the TS rate of the transmitting side is 19.39 Mbi.
By generating mappings higher and lower than t / s, as in Embodiment 1 or 2,
The PEG2-TS rate can be controlled. Also,
Both of the two mapping patterns have a transmission rate of 19.39M
The rate is close to bit / s. That is, the change in the transmission rate is small when switching to either mapping, the capacity of the storage circuit 1 that absorbs the change can be reduced, and the fixed delay can be suppressed.

Embodiment 4 FIG. In the fourth embodiment, an embodiment will be described in which the above-described first, second, and third embodiments further include a unit for adding identification data for identifying a mapping pattern selected on the transmission side.

FIG. 6 is a block diagram of a digital signal transmission device in such a case. In FIG. 6, 8 is an identification data generation circuit, and 9 is a switch for switching between identification data and invalid data.

Next, the operation will be described. Controlling the transmission rate by switching the mapping pattern is the same as in the first embodiment. However, when the mapping pattern is switched, data for identifying the mapping pattern output from the identification data generating circuit 8 is transmitted to the mapping pattern control circuit 5. Controls the changeover switch 9 to insert the invalid data at a specific position in the frame instead of the invalid data.

With the above configuration, the receiving side can easily identify the mapping pattern and extract the TS data. Further, since the part which is originally invalid data is used, the line use efficiency does not decrease.

Embodiment 5 Embodiments 1, 2, and 3
In the above, the mapping pattern is switched according to the output of the storage state detection. However, an embodiment including a means for detecting the boundary value of the remaining storage amount as a circuit for detecting the storage state will be described.

FIG. 7 shows a storage state detection circuit in such a case. In FIG. 7, 1 is a storage circuit, 3 is an accumulation state detection circuit, 10 is a signal indicating an upper limit value of the remaining data amount, 11 is an upper limit value counter, 12 is a signal indicating a lower limit value of the remaining data amount, and 13 is a lower limit value. The counter 14 is a determination circuit.

Next, the operation will be described. Since data is written into the storage circuit 1 from the MPEG2-TS generation device side and data is read from the DS3 line side, the remaining data amount constantly fluctuates. However, as mentioned above, if there is any speed difference between writing and reading,
The data remaining amount shows a gradually increasing or decreasing tendency. For example, when the writing speed is faster than the reading speed, the remaining data amount tends to increase.

Therefore, an upper limit value of the remaining data amount in the storage circuit 1 is set, and when the remaining amount exceeds the upper limit value, a signal 10 indicating the upper limit value of the remaining data amount is output. The value counter 11 counts how many times the remaining data amount has reached the upper limit value. When the number of counts reaches a certain value, the determination circuit 14 determines that the remaining data amount is increasing, that is, that the writing speed is faster. Judgment by counting multiple times is because the remaining amount of data in the storage circuit 1 is constantly fluctuating as described above, so it is determined whether the remaining amount of data tends to increase only by exceeding the upper limit once. Because it is difficult to do. The mapping pattern control circuit receives the determination result and switches to the mapping with the higher read speed (higher transmission rate) before the data overflows.

Conversely, when the writing speed is lower than the reading speed, the remaining data amount tends to decrease. When the remaining amount of data in the storage circuit falls below a specified value, a signal 12 indicating the lower limit of the remaining amount of data is output, and the lower limit value counter 13 in the accumulation state detecting circuit 3 counts. When the number of counts reaches a certain value, the determination circuit 14 informs the mapping pattern control circuit 5 of the determination that the remaining amount of data is decreasing, that is, the writing speed is slower.

By adopting the circuit configuration for detecting the accumulation state as described above, the mapping pattern can be switched at an appropriate timing without causing the data remaining amount of the storage circuit to overflow or underflow.

Embodiment 6 FIG. In the fifth embodiment, as a circuit for detecting the accumulation state, means for detecting a boundary value of the remaining amount of accumulation is provided. As another example of the circuit for detecting the accumulation state, the data remaining in the storage circuit 1 is used. 1 shows an embodiment with means for detecting the temporal displacement of an amount.

FIG. 8 shows an accumulation state detection circuit in such a case. 8, reference numeral 15 denotes a signal indicating the remaining amount of data in the storage circuit 1, 16 denotes a sampling circuit, 17 denotes a shift register, 18 denotes a subtractor, and 19 denotes a determination circuit.

Next, the operation will be described. Reference numeral 15 denotes a signal that constantly outputs the remaining data amount of the storage circuit 1. The sampling circuit 16 samples the signal 15 at a constant time interval ΔT. The shift register 17 temporarily stores the sampling value obtained by the sampling circuit 16. For example, the register (a) stores the value of the time T, and the register (b) stores the time (T−Δ
T) is stored. The subtractor 18 is a register (a)
And the difference between (b). If the remaining amount of data in the storage circuit 1 tends to decrease, that is, if the reading speed is too fast, the sampling value of the remaining amount of data at the time T (stored in the register (a)) is the sampling value of the past (T-ΔT) (( b), the value of the register (a) −the value of the register (b) <0. Conversely, if the remaining data amount tends to increase, that is, if the read speed is too slow, the value of the register (a) −the value of the register (b)>
It becomes 0. That is, by examining the sign of the subtracter 18, the temporal displacement of the remaining amount of data in the storage circuit 1 can be measured. The judgment circuit 19 compares this result with the mapping pattern control circuit 5
Tell

By adopting a circuit configuration for detecting the accumulation state as described above, the mapping pattern can be switched at an appropriate timing without causing the data remaining amount of the storage circuit 1 to overflow or underflow.

Embodiment 7 FIG. In the sixth embodiment, the circuit for detecting the accumulation state is provided with a unit for storing the remaining amount of the storage circuit 1. However, as another example of the circuit for detecting the accumulation state, the circuit according to the fifth embodiment may be used. 6 shows an embodiment provided with means for judging the accumulation state in a complex manner by using FIG.

FIG. 9 shows an accumulation state detection circuit in such a case. In FIG. 9, reference numerals 20 to 23 denote Embodiment 5,
24 to 27 are the same as in the sixth embodiment. 28 is a judgment circuit, 29 is an output signal of the upper limit value counter 21, 30 is an output signal of the subtracter 27, and 31 is an output signal of the lower limit value counter 23.

Next, the operation will be described. The operation until the upper limit value counter signal 29 and the lower limit value counter signal 31 are output is the same as in the fifth embodiment. The operation until the sampling value difference signal 30 is output is the same as in the sixth embodiment.

The determination circuit 28 operates as follows for the storage circuit 1
Is determined. (1) When the upper limit value counter signal 29 reaches a certain value or more and the sampling value difference signal 30 takes a positive value, it is determined that the accumulation state of the storage circuit 1 is increasing. (2) When the lower limit value counter signal 31 reaches a certain value or more and the sampling value difference signal 30 takes a negative value, the storage state of the storage circuit 1 is determined to be decreasing. Judgment circuit 2
8 informs the mapping pattern control circuit 5 of this determination result.

By using the configuration of the circuit for detecting the accumulation state as described above and using both the boundary value of the remaining amount of data and the temporal displacement as the judgment information, the accumulation state of the data can be grasped more accurately. The mapping pattern can be switched at a more accurate timing.

Embodiment 8 FIG. In the eighth embodiment, there is shown an embodiment further including means for inserting an error correction code using a part or all of invalid data.

FIG. 10 is a block diagram of a digital signal data transmission apparatus in such a case. In FIG. 10, reference numeral 32 denotes an error correction code generation circuit, and reference numeral 33 denotes a switch for switching between an error correction code and invalid data.

Next, the operation will be described. Controlling the transmission rate by switching the mapping pattern is the same as in the first, second, and third embodiments.
The data from the TS generator is sent to the error correction code generator 3
2 is also input. The error correction code generation circuit 32 generates an error correction code from the input data. Then, the mapping pattern control circuit 5 controls the changeover switch 33 to
An error correction code is inserted in place of invalid data at a specific position in three frames.

With the above configuration, even if the line quality is slightly deteriorated, it is possible to transmit the MPEG2-TS with no error or with few bit errors without retransmission. Further, since the part which is originally invalid data is used, the line use efficiency does not decrease.

The same effect can be obtained by inserting an error detection code such as CRC instead of inserting an error correction code as described above.

Embodiment 9 In the first, second and third embodiments, a mapping pattern in which MPEG2-TS and invalid data are completely separated in a frame is used. As another example of the mapping pattern, invalid data is interposed between TS packets. The following shows a form in which is inserted after being sorted.

FIG. 11 shows a TS mapping to a DS3 large frame as an example of a mapping pattern in such a case.

The mapping pattern (a) is as follows. In a large frame of 4704 bytes, TS is 2068 bytes (188 × 11),
The invalid data has 2,636 bytes, and is a mapping in which the TS and the invalid data are completely separated in the large frame.
On the other hand, the mapping pattern (b) indicates that this invalid data is 1
It is divided into one and allocated almost equally after the TS packet.

As described above, the configuration in which invalid data is evenly distributed to large frames makes it possible to store MPEG2-T
S can be prevented from being transmitted in a burst. When the TS is transmitted in bursts, there is a high probability that the number of packets that are damaged when high-level noise occurs momentarily increases. By distributing the TS packets evenly in the frame, resistance to noise that may occur instantaneously is improved. Further, by dispersing the TS packets evenly in the frame, the TS rate fluctuation is reduced, and the buffer capacity for absorbing the rate fluctuation can be reduced.

[0071]

As described above, according to the digital signal transmission apparatus of the present invention, a mapping higher than the transmission rate on the transmission side and a mapping lower than the transmission rate are prepared, and the mapping is switched according to the storage state of the storage circuit. By doing so, DS at the same bit rate as the data transmission rate on the transmitting side
There is an effect that it can be placed on three transmission paths. In addition, if the mapping pattern is known in advance on the receiving side, the TS can be easily obtained by simply detecting the head of the DS3 frame.
Can be extracted, and the circuit on the receiving side can be simplified.
In addition, by adopting such a configuration, it is possible to synchronize the TS and the DS3 frame. Therefore, if only the DS3 frame can be detected, there is no need to provide a TS header detection circuit on the receiving side, and the circuit on the receiving side can be simplified. .

Further, by generating the transmission format in frame units that match the hierarchical structure of the digital transmission path, there is an effect that the capacity of the storage circuit can be reduced. In addition, if only the DS3 frame structure can be established in the hierarchical structure of the digital transmission path, the mapping pattern is guaranteed, so that the degree of freedom on the network is high.

Further, in the transmission format, by generating a mapping pattern for inserting invalid data in units of 1 byte, both of the generated two mapping patterns are close to the data rate of the transmission source. Therefore, there is an effect that the fluctuation of the transmission rate due to the above can be reduced, and the capacity of the storage circuit for absorbing the fluctuation of the transmission rate can be reduced.

Further, by providing means for adding identification data for identifying the mapping pattern selected on the transmitting side, the receiving side can easily identify the mapping pattern and extract TS data. Since the part which is originally invalid data is used, it does not contribute to the reduction of the line use efficiency.

Further, since the circuit for detecting the storage state is configured to detect the boundary value of the remaining amount of storage, the mapping pattern can be switched without causing the overflow or underflow of the remaining amount of data in the storage circuit. . That is, there is an effect that the transmission rate of the MPEG2-TS on the transmission side and the TS transmission rate of the DS3 line are made equal on average.

Further, since the circuit for detecting the accumulation state is configured to detect the temporal displacement of the remaining data amount of the storage circuit, the mapping pattern can be changed without causing the remaining data amount of the storage circuit to overflow or underflow. Can be switched. That is, the transmitting side MP
There is an effect that the EG2-TS transmission rate and the TS transmission rate of the DS3 line are made equal on average.

Further, as a circuit for detecting the accumulation state, the boundary value of the remaining amount of data is detected and the temporal displacement of the remaining amount of data in the storage circuit is detected. By using both the temporal displacements as the determination information, the data accumulation state can be determined more accurately, and the mapping pattern can be switched more accurately. And the capacity of the storage circuit can be reduced.

Further, by inserting an error correction code using a part or all of the invalid data,
Even if the line quality deteriorates slightly, without retransmission,
MPEG2 with error-free or few bit errors
-There is an effect that the TS can be transmitted.

Further, by adopting a mapping pattern in which invalid data is equally distributed and inserted between TS packets, there is an effect of improving noise resistance performance. Further, the TS rate fluctuation is reduced, and the buffer capacity for absorbing the rate fluctuation can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a digital signal transmission device according to Embodiment 1 of the present invention.

FIG. 2 is an explanatory diagram showing a mapping pattern according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a DS3 frame structure.

FIG. 4 is an explanatory diagram showing a mapping pattern according to Embodiment 2 of the present invention.

FIG. 5 is an explanatory diagram showing a mapping pattern according to Embodiment 3 of the present invention.

FIG. 6 is a block diagram showing a digital signal transmission device according to Embodiment 4 of the present invention.

FIG. 7 is a block diagram of an accumulation state detection circuit according to Embodiment 5 of the present invention.

FIG. 8 is a block diagram of an accumulation state detection circuit according to Embodiment 6 of the present invention.

FIG. 9 is a block diagram of an accumulation state detection circuit according to a seventh embodiment of the present invention.

FIG. 10 is a block diagram of a digital signal transmission apparatus according to Embodiment 8 of the present invention.

FIG. 11 is an explanatory diagram showing a mapping pattern according to Embodiment 9 of the present invention.

FIG. 12 is a block diagram of a digital signal transmission device showing a configuration of a conventional example.

FIG. 13 is an explanatory diagram showing a mapping pattern of MPEG over ATM.

FIG. 14 is an explanatory diagram showing a PLCP frame structure.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 storage circuit, 2 invalid data generation circuit, 3 accumulation state detection circuit, 4 changeover switch, 5 mapping pattern control circuit, 6 MPEG2-TS generation device, 7
DS3 line, 8 mapping identification data generation circuit, 9,
33 changeover switch, 11, 21 upper limit value counter, 13, 23 lower limit value counter, 14, 19, 28
Judgment circuit, 16, 25 Sampling circuit, 17, 26
Shift register, 18, 27 subtractor, 32 error correction code generation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04Q 3/00

Claims (9)

[Claims] 1. A digital signal transmission device for transmitting digital data from a data generation device for generating digital data of a predetermined bit rate through a digital transmission line having a higher bandwidth, wherein the digital data from the data generation device is Storage means for temporarily storing, invalid data generation means for generating invalid data, accumulation state detection means for detecting the accumulation state of the storage means, and output of one of the invalid data generation means and the storage means Switching means for switching to the digital transmission path, and switching control of the switching means to switch between the output of the invalid data generation means and the readout output from the storage means so that the band occupied by the digital signal with respect to the transmission path band Is slightly higher and lower than the input bit rate It generates and bets, the digital signal transmission device is characterized in that a mapping pattern control means for switching the two transmission formats adaptively in accordance with the detection output indicating the storage state by the accumulation state detection means. 2. The digital signal transmission apparatus according to claim 1, wherein said mapping pattern control means generates a transmission format for each frame conforming to a hierarchical structure of said digital transmission path. apparatus. 3. The digital signal transmission device according to claim 1, wherein said mapping pattern control means comprises:
A digital signal transmission device for generating a transmission format for inserting and removing invalid data in units of 1 byte. 4. The digital signal transmission device according to claim 1, wherein an identification signal generating means for generating an identification signal for identifying said two transmission formats, and an output from said identification signal generating means. Second switching means for switching any one of the outputs from the invalid data generating means and outputting to the switching means, wherein the mapping pattern control means switches the second switching means to transmit A digital signal transmission device, wherein an identification signal for identifying the two transmission formats is added to a format by using a part of the invalid data. 5. The digital signal transmission device according to claim 1, wherein said storage state detection means outputs a signal indicating an upper limit value when the remaining amount of data in said storage means exceeds an upper limit value. An upper limit counter for counting,
A lower limit counter that counts a signal indicating a lower limit when the remaining amount of data in the storage unit falls below the lower limit; and a determination unit that outputs a comparison determination result between the count value of the counter and a set value. A digital signal transmission device, wherein the mapping pattern control means determines a timing of switching the transmission format based on the comparison determination result. 6. The digital signal transmission device according to claim 1, wherein said storage state detection means includes: a sampling means for sampling a data remaining amount of said storage means at a fixed time interval; A difference calculating means for calculating a difference between the sampled value and a past sampling value; and a determining means for determining a temporal displacement of the remaining amount of stored data in the storage means based on a difference value from the difference calculating means, A digital signal transmission device, wherein the mapping pattern control means determines the timing of switching the transmission format based on the comparison determination result. 7. The digital signal transmission device according to claim 1, wherein said storage state detection means outputs a signal indicating an upper limit value when the remaining data amount of said storage means exceeds an upper limit value. An upper limit counter for counting,
A lower limit counter that counts a signal indicating a lower limit when the remaining amount of data in the storage unit falls below the lower limit value; a sampling unit that samples the remaining amount of data in the storage unit at fixed time intervals; Difference calculating means for calculating a difference between the value and a past sampling value; and when the count value of the upper limit counter reaches a predetermined value or more and the value of the difference takes a positive value, the accumulation state of the storage means is When the count value of the lower limit counter reaches a predetermined value or more and the value of the difference takes a negative value, the determination unit determines that the accumulation status of the storage unit is a decrease trend. Wherein the mapping pattern control means determines the timing of switching the transmission format based on the comparison determination result. No. transmission equipment. 8. The digital signal transmission device according to claim 1, wherein said digital signal output from said data generation device generates an error correction code from digital data, and said error correction code generation unit generates said error correction code. A third switching unit that switches between the output from the generation unit and the output from the invalid data generation unit and outputs the output to the switching unit, wherein the mapping pattern control unit includes:
A digital signal transmission device, characterized in that the third switching means is switch-controlled to add an error correction code to a transmission format by using part or all of the invalid data. 9. The digital signal transmission device according to claim 1, wherein said mapping pattern control means generates a transmission format for inserting invalid data uniformly in time. Signal transmission device.