JPH11252185A - Signal transmission circuit - Google Patents

Signal transmission circuit

Info

Publication number
JPH11252185A
JPH11252185A JP10046695A JP4669598A JPH11252185A JP H11252185 A JPH11252185 A JP H11252185A JP 10046695 A JP10046695 A JP 10046695A JP 4669598 A JP4669598 A JP 4669598A JP H11252185 A JPH11252185 A JP H11252185A
Authority
JP
Japan
Prior art keywords
circuit
signal transmission
signal
waveform
transmitted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10046695A
Other languages
Japanese (ja)
Inventor
Kazuhiko Sato
和彦 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP10046695A priority Critical patent/JPH11252185A/en
Publication of JPH11252185A publication Critical patent/JPH11252185A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To transmit a high speed signal without deterioration the waveform of the signal even in a CMOS-type driving circuit by connecting a series circuit composed of a terminal resistance and a coil to the reception terminal-side of a signal transmission line in parallel. SOLUTION: A signal transmission lines 14 are connected to the output terminals T1 and T2 of a driving circuit 13 constituted of field effect transistors FET1 -FET3 installed in a main circuit 10 constituted of a CMOS-type circuit. A signal is transmitted to the unit B of a reception side through the signal transmission line 14. The series circuit constituted of a terminal resistance R7 and a coil L1 is connected to reception terminals T3 and T4 in parallel. Thus, the rounding of the rise/fall waveforms of a rectangular wave to be transmitted is dissolved and the deterioration of the waveform is suppressed. Thus, the correct waveform can be transmitted to a reception circuit even if it is driven by the CMOS-type driving circuit, and the form of the board of a unit on a transmission side can be miniaturized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は各種の電子機器に
用いることができる信号伝送回路に関する。
The present invention relates to a signal transmission circuit that can be used for various electronic devices.

【0002】[0002]

【従来の技術】一般にデジタルIC等では電力消費量が
小さく、集積度が高く形状も小さく作ることができるこ
とから、CMOS型半導体集積回路が主流である。従っ
て、電子機器の各ユニットの内部は主にCMOS型IC
によって構成されるのが普通である。
2. Description of the Related Art In general, CMOS type semiconductor integrated circuits are mainly used for digital ICs and the like, since power consumption is small, the degree of integration is high, and the size can be reduced. Therefore, the inside of each unit of the electronic device is mainly a CMOS IC.
It is usually constituted by

【0003】ところで、電子機器の内部において、例え
ばユニット間等で信号の授受を行う信号伝送回路では信
号伝送線路に信号を出力する回路としてECL型デバイ
スが用いられている。つまり、図4に示すようにユニッ
トAからユニットBに信号を伝送する信号伝送回路にお
いて、ユニットAの主回路10はCMOS型で構成され
るICによって構成され、この主回路10の出力側にE
CL回路で構成されるECL型駆動回路12を配置し、
このECL型駆動回路12を通じて信号伝送線路14を
接続し、信号伝送線路14を通じて受信側のユニットB
に信号を伝送している。受信側のユニットBでも受信回
路16はECL回路によって構成される。
In an electronic device, an ECL device is used as a circuit for outputting a signal to a signal transmission line in a signal transmission circuit for exchanging signals between units, for example. That is, as shown in FIG. 4, in a signal transmission circuit for transmitting a signal from the unit A to the unit B, the main circuit 10 of the unit A is constituted by an IC constituted by a CMOS type.
An ECL type driving circuit 12 composed of a CL circuit is arranged,
The signal transmission line 14 is connected through the ECL type driving circuit 12, and the reception side unit B is connected through the signal transmission line 14.
Is transmitting the signal. In the unit B on the receiving side, the receiving circuit 16 is also configured by an ECL circuit.

【0004】図5にECL型駆動回路12の具体的回路
の一例を示す。ECL回路は周知のようにバイポーラト
ランジスタQ1 ,Q2 等によって構成される。図5の例
ではバイポーラトランジスタQ1 ,Q2 がエミッタフォ
ロワ回路を構成し、エミッタフォロワ回路の出力端子T
1 ,T2 に信号伝送線路14を接続し、例えば50Ωの
特性インピーダンスに整合させた状態で信号伝送線路1
4を駆動し、受信側のユニットBに信号を伝送する回路
構成とした場合を示す。
FIG. 5 shows an example of a specific circuit of the ECL type driving circuit 12. As is well known, the ECL circuit includes bipolar transistors Q 1 , Q 2, and the like. In the example of FIG. 5, the bipolar transistors Q 1 and Q 2 form an emitter follower circuit, and the output terminal T of the emitter follower circuit
1 and T 2 , the signal transmission line 14 is connected, and the signal transmission line 1 is matched with a characteristic impedance of, for example, 50Ω.
4 is driven, and a circuit configuration for transmitting a signal to the unit B on the receiving side is shown.

【0005】なお、R1 はエミッタフォロワの負荷抵抗
器、R2 はインピーダンス整合用の抵抗器、R3 は終端
抵抗をそれぞれ示す。この回路構成とした場合、ユニッ
トAの出力端子T1 ,T2 の出力波形が図7Aに示す波
形であったとすると、受信端子T3 ,T4 の受信波形は
図7Bに示す波形が得られる。この受信端子T3 ,T4
の受信波形は出力端子T1 ,T2 の送信波形にほゞ一致
し、立上がり及び立下りのタイミングの変動及びパルス
幅Pw 1 =Pw2 の変動もなく、安定に信号を伝送する
ことができる。特にECL回路を用いることにより周波
数が高い信号であっても波形の劣化を来すことなく信号
を安定に伝送することができる。
Note that R1Is the load resistance of the emitter follower
Vessel, RTwoIs a resistor for impedance matching, RThreeIs the end
The resistance is shown. With this circuit configuration, the unit
A output terminal T1, TTwoOutput waveform of FIG. 7A
Assuming that the receiving terminal TThree, TFourThe received waveform of
The waveform shown in FIG. 7B is obtained. This receiving terminal TThree, TFour
The received waveform at the output terminal T1, TTwoAlmost matches the transmission waveform of
And fluctuation of rising and falling timing and pulse
Width Pw 1= PwTwoStable signal transmission without fluctuation
be able to. Especially, by using the ECL circuit,
Even if the number of signals is high, the signal can be
Can be transmitted stably.

【0006】これに対し、図6に示すようにCMOS型
駆動回路13で信号伝送線路14を高速駆動した場合に
は受信端子T3 ,T4 の波形は図7Cに示すように波形
が劣化し、立上がりのタイミング及び立下りのタイミン
グは正規のタイミングから変動し、パルス幅もPw1
Pw3 のように狭くなってしまう不都合が生じる。この
波形劣化はCMOS型駆動回路の能動素子が比較的オン
抵抗が大きい電界効果トランジスタFET1 ,FE
2 ,FET3 等によって構成される点と、これら電界
効果トランジスタFET1 ,FET2 ,FET3 によっ
て構成される駆動回路の出力インピーダンスが高いこと
等に起因するものと考えられる。
On the other hand, when the signal transmission line 14 is driven at high speed by the CMOS type driving circuit 13 as shown in FIG. 6, the waveforms at the receiving terminals T 3 and T 4 are deteriorated as shown in FIG. 7C. , The rising timing and the falling timing fluctuate from the regular timing, and the pulse width also becomes Pw 1 >
An inconvenience of narrowing such as Pw 3 occurs. This waveform deterioration is caused by the fact that the active elements of the CMOS type driving circuit have relatively large on-resistance of the field effect transistors FET 1 , FE
This is considered to be due to the fact that it is composed of T 2 , FET 3 and the like, and that the output impedance of the drive circuit composed of these field effect transistors FET 1 , FET 2 and FET 3 is high.

【0007】[0007]

【発明が解決しようとする課題】上述したように、EC
L型駆動回路12を用いた場合は、高速信号でも信号の
波形を劣化させずに伝送することができる。しかしなが
ら、ECL型駆動回路12をユニットA側に実装しなけ
ればならないことから、ユニットAを構成するボード上
の部品実装密度を高めることができない不都合が生じ
る。つまり、ECL回路は比較的形状が大きいため、伝
送すべき信号のチャンネル数が多い場合はECL駆動回
路12の占める占有面積が大きくなり、ボードの形状も
大型になってしまう欠点がある。
As described above, the EC
When the L-type drive circuit 12 is used, even a high-speed signal can be transmitted without deteriorating the signal waveform. However, since the ECL drive circuit 12 must be mounted on the unit A side, there is a disadvantage that the component mounting density on the board constituting the unit A cannot be increased. That is, since the ECL circuit has a relatively large shape, if the number of channels of a signal to be transmitted is large, the occupied area occupied by the ECL drive circuit 12 becomes large, and the size of the board becomes large.

【0008】これに対し図6に示したCMOS型駆動回
路13を用いる場合は、主回路10から直接信号伝送線
路14を駆動できるからボードの形状を小さくできる利
点が得られる。しかしながら、CMOS型駆動回路13
では周波数の高い信号に対しては上述したように信号波
形の劣化が著しく、実用に供し得ない欠点がある。この
発明の目的は、CMOS型駆動回路でも高速信号の波形
を劣化させることなく伝送することができる信号伝送回
路を提供しようとするものである。
On the other hand, when the CMOS type driving circuit 13 shown in FIG. 6 is used, the signal transmission line 14 can be directly driven from the main circuit 10, so that the advantage that the board shape can be reduced is obtained. However, the CMOS type driving circuit 13
As described above, there is a disadvantage that the signal waveform is significantly deteriorated for a signal having a high frequency as described above, and the signal cannot be put to practical use. SUMMARY OF THE INVENTION An object of the present invention is to provide a signal transmission circuit capable of transmitting a high-speed signal without deteriorating a waveform even in a CMOS type driving circuit.

【0009】[0009]

【課題を解決するための手段】この発明ではCMOS型
駆動回路の出力端子に信号伝送線路を接続し、CMOS
型駆動回路によって受信側ユニットに信号を伝送する信
号伝送回路において、信号伝送線路の受信端子側に終端
抵抗とコイルから成る直列回路を並列接続した構成とす
るものである。
According to the present invention, a signal transmission line is connected to an output terminal of a CMOS type driving circuit, and a CMOS type driving circuit is provided.
In a signal transmission circuit for transmitting a signal to a receiving unit by a mold driving circuit, a series circuit composed of a terminating resistor and a coil is connected in parallel to a receiving terminal of the signal transmission line.

【0010】コイルのインダクタンス値Lは伝送しよう
とする信号の周波数をf,補償しようとする電圧をΔV
とすると、L=ΔV/2πfで与えられる。この発明の
構成によれば伝送しようとする信号の周波数に対してコ
イルが共振し、信号伝送線路の周波数特性が高域側にお
いて利得が強調される。この結果、伝送しようとする矩
形波の立上がり及び立下りの波形のなまりが解消され、
波形の劣化が抑えられる。この結果、CMOS型駆動回
路で駆動しても正しい波形を受信回路に伝送することが
でき、送信側のユニットのボードの形状を小さくできる
利点が得られる。
The inductance value L of the coil is f, the frequency of the signal to be transmitted, and ΔV, the voltage to be compensated.
Then, L = ΔV / 2πf. According to the configuration of the present invention, the coil resonates at the frequency of the signal to be transmitted, and the frequency characteristic of the signal transmission line emphasizes the gain on the high frequency side. As a result, the rounding of the rising and falling waveforms of the rectangular wave to be transmitted is eliminated,
Waveform deterioration is suppressed. As a result, the correct waveform can be transmitted to the receiving circuit even when driven by the CMOS type driving circuit, and the advantage that the shape of the board of the unit on the transmitting side can be reduced is obtained.

【0011】[0011]

【発明の実施の形態】図1にこの発明による信号伝送回
路の一実施例を示す。図6と対応する部分には同一符号
を付して示す。この発明においてはCMOS型回路で構
成される主回路10の内部に設けられた電界効果トラン
ジスタFET1 ,FET2 ,FET3 等によって構成さ
れる駆動回路13の出力端子T1 とT2 に信号伝送線路
14を接続し、この信号伝送線路14を通じて受信側の
ユニットBに信号を伝送する信号伝送回路において、受
信端子T3 とT4 に終端抵抗R7 とコイルL1 とによっ
て構成される直列回路を並列接続する構成としたもので
ある。図1に示す終端抵抗R7 は図6に示した終端抵抗
6 の抵抗値を二分割し、コイルL1 の両端に1/2の
抵抗に分割した終端抵抗R7 を接続し、これら3個の素
子から成る直列回路を受信端子T3 とT4の間に接続し
た構成とした場合を示す。
FIG. 1 shows an embodiment of a signal transmission circuit according to the present invention. Parts corresponding to those in FIG. 6 are denoted by the same reference numerals. Field effect transistor FET 1 which is provided in the configured main circuit 10 in the CMOS circuit in the present invention, FET 2, FET 3 such as the signal transmitted to the output terminal T 1 and T 2 of the configured drive circuit 13 by connect the line 14, the series circuit composed of the signal transmission circuit for transmitting a signal to the unit B of the receiving side through the signal transmission line 14, and the terminating resistor R 7 to the reception terminal T 3 and T 4 and the coil L 1 Are connected in parallel. Termination resistor R 7 shown in FIG. 1 is a resistance of the terminating resistor R 6 shown in FIG. 6 divided into two parts, connect a terminator R 7 divided to 1/2 of the resistance across the coil L 1, these 3 shows the case of the configuration of connecting the series circuit consisting of pieces of element between the receiving terminals T 3 and T 4.

【0012】コイルL1 のインダクタンス値Lは伝送し
ようとする信号の周波数をf,伝送しようとする矩形波
の波形を改善しようとする補償電圧をΔV(図2参照)
とした場合、L=ΔV/2πfで与えられる。コイルL
1 のインダクタンス値Lを適当値に設定することによ
り、伝送しようとする信号の周波数fに対してコイルL
1 が共振し、信号伝送線路14の周波数特性は周波数f
において強調される。従って、出力端子T1 ,T2 に図
3Aに示す波形の信号を出力した場合、受信端子T3
4 には図3Bに示す波形を得ることができた。図3B
に示す波形は立上がりのタイミング及び立下りのタイミ
ングは図3Aに示した送信波形とほゞ同一となる。また
パルス幅PWも送信波形とほゞ同一となり、正しい波形
を受信側のユニットBに伝送することができた。
The inductance value L of the coil L 1 is f, the frequency of the signal to be transmitted, and ΔV, the compensation voltage for improving the waveform of the rectangular wave to be transmitted (see FIG. 2).
Is given by L = ΔV / 2πf. Coil L
By setting the inductance value L of 1 to an appropriate value, the coil L can be adjusted with respect to the frequency f of the signal to be transmitted.
1 resonates, and the frequency characteristic of the signal transmission line 14 is the frequency f
It is emphasized in. Therefore, when a signal having the waveform shown in FIG. 3A is output to the output terminals T 1 and T 2 , the reception terminals T 3 and T 2
The T 4 could be obtained waveform shown in Figure 3B. FIG. 3B
3A has almost the same rising and falling timings as the transmission waveform shown in FIG. 3A. Also, the pulse width PW was almost the same as the transmission waveform, and a correct waveform could be transmitted to the unit B on the receiving side.

【0013】[0013]

【発明の効果】以上説明したように、この発明によれば
集積度の高い回路で構成されるCMOS型ICの駆動回
路によって信号伝送線路14を高速駆動しても、受信側
のユニットBに波形を劣化させることなく信号を伝達す
ることができた。コイルL1 は伝送しようとする信号の
周波数が高ければ高い程インダクタンス値は小さくな
り、この結果、コイルL1 は安価に作ることができる。
よって安価な部品L1 を付加するだけで、CMOS型駆
動回路を実用することができ、これにより送信側ユニッ
トAの形状を小さくできる利点が得られる。
As described above, according to the present invention, even when the signal transmission line 14 is driven at a high speed by a CMOS-type IC driving circuit composed of a highly integrated circuit, the waveform on the receiving side unit B is not changed. Could be transmitted without deteriorating the signal. Coil L 1 is the inductance value higher the frequency of the signal to be transmitted is reduced, as a result, the coil L 1 can be made inexpensive.
Therefore only by adding inexpensive parts L 1, it is possible to practically the CMOS type drive circuit, it has the advantage that thereby reduce the shape of the transmitting side unit A is obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の一実施例を説明するための接続図。FIG. 1 is a connection diagram for explaining an embodiment of the present invention.

【図2】この発明の動作を説明するための波形図。FIG. 2 is a waveform chart for explaining the operation of the present invention.

【図3】図2と同様の波形図。FIG. 3 is a waveform diagram similar to FIG. 2;

【図4】従来の技術を説明するためのブロック図。FIG. 4 is a block diagram for explaining a conventional technique.

【図5】ECL型駆動回路によって信号伝送線路を駆動
する回路構造を説明するための接続図。
FIG. 5 is a connection diagram for explaining a circuit structure for driving a signal transmission line by an ECL type driving circuit.

【図6】CMOS型駆動回路によって信号伝送線路を駆
動する回路構造を説明するための接続図。
FIG. 6 is a connection diagram for explaining a circuit structure for driving a signal transmission line by a CMOS type driving circuit.

【図7】図5と図6の動作を説明するための波形図。FIG. 7 is a waveform chart for explaining the operations of FIGS. 5 and 6;

【符号の説明】[Explanation of symbols]

10 CMOS型回路で構成された主回路 14 信号伝送線路 T1 ,T2 出力端子 T3 ,T4 受信端子 R7 終端抵抗 L1 コイル10 main circuit composed of a CMOS-type circuit 14 the signal transmission line T 1, T 2 output terminals T 3, T 4 reception terminal R 7 terminating resistor L 1 coil

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 CMOS型半導体集積回路素子に形成さ
れたCMOS型駆動回路の出力端子に信号伝送線路を接
続し、この信号伝送線路を通じて他のユニットに信号を
伝送する信号伝送回路において、 上記他のユニットの受信端子に終端抵抗器と補償用コイ
ルを直列接続した回路を並列に接続した構成としたこと
を特徴とする信号伝送回路。
1. A signal transmission circuit for connecting a signal transmission line to an output terminal of a CMOS type driving circuit formed in a CMOS type semiconductor integrated circuit device and transmitting a signal to another unit through the signal transmission line. A signal transmission circuit, wherein a circuit in which a terminating resistor and a compensation coil are connected in series to a receiving terminal of the unit is connected in parallel.
JP10046695A 1998-02-27 1998-02-27 Signal transmission circuit Pending JPH11252185A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10046695A JPH11252185A (en) 1998-02-27 1998-02-27 Signal transmission circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10046695A JPH11252185A (en) 1998-02-27 1998-02-27 Signal transmission circuit

Publications (1)

Publication Number Publication Date
JPH11252185A true JPH11252185A (en) 1999-09-17

Family

ID=12754527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10046695A Pending JPH11252185A (en) 1998-02-27 1998-02-27 Signal transmission circuit

Country Status (1)

Country Link
JP (1) JPH11252185A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004096351A (en) * 2002-08-30 2004-03-25 Canon Inc Terminating circuit for differential signal transmission line
JP2006254303A (en) * 2005-03-14 2006-09-21 Renesas Technology Corp Signal transmission circuit, ic package, mounting substrate and ic chip
WO2016079798A1 (en) * 2014-11-18 2016-05-26 株式会社ソシオネクスト Clock transmission circuit and semiconductor integrated circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004096351A (en) * 2002-08-30 2004-03-25 Canon Inc Terminating circuit for differential signal transmission line
JP2006254303A (en) * 2005-03-14 2006-09-21 Renesas Technology Corp Signal transmission circuit, ic package, mounting substrate and ic chip
WO2016079798A1 (en) * 2014-11-18 2016-05-26 株式会社ソシオネクスト Clock transmission circuit and semiconductor integrated circuit
JPWO2016079798A1 (en) * 2014-11-18 2017-04-27 株式会社ソシオネクスト Clock transmission circuit and semiconductor integrated circuit
US9748938B2 (en) 2014-11-18 2017-08-29 Socionext Inc. Clock transmission circuit and semiconductor integrated circuit

Similar Documents

Publication Publication Date Title
JP3828652B2 (en) Differential signal transmission circuit
EP2056547B1 (en) An interface circuit that can switch between single-ended transmission and differential transmission
US5111080A (en) Complementary signal transmission circuit with impedance matching circuitry
US4713827A (en) Terminator for a cmos transceiver device
US7495474B2 (en) Integrated circuit device and electronic instrument
US6812741B2 (en) Bidirectional signal transmission circuit and bus system
US6838900B2 (en) Middle pull-up point-to-point transceiving bus structure
JPH11252185A (en) Signal transmission circuit
US6980019B2 (en) Output buffer apparatus capable of adjusting output impedance in synchronization with data signal
US20060200689A1 (en) Signal transmitting circuit
KR20040068719A (en) Termination circuit for reducing consumption of power
ATE387030T1 (en) IMPROVEMENTS TO RESONANCE LINE DRIVERS
KR100296452B1 (en) Synchronous semiconductor memory device having data input buffers
US20050083289A1 (en) [cascade driving circuit for liquid crystal display]
US20060152275A1 (en) Signal transmitting circuit
JPH09247217A (en) Signal transmission circuit
US20080074206A1 (en) Frequency-selective oscillator
KR100533561B1 (en) Semiconductor memory device
JP4542367B2 (en) Receiver circuit for ultrasonic diagnostic equipment
JP2003224487A (en) High-frequency signal transmitter and electronic tuner using the same
US20070170971A1 (en) Signal transmitting circuit
JPH09149085A (en) Multi-connection device
US6384642B1 (en) Switched positive feedback for controlled receiver impedance
JPH1065744A (en) Bus interface circuit
JP2000151721A (en) Bus line terminating circuit for electronic equipment

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040721

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20051104

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060216

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060328

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20060725