JPH11251880A - Clock multiplying circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a clock multiplying circuit which reduces power consumption and generates a multiplying clock signal with a correct duty ratio by suppressing the variation owing to an operation condition, such as temperature. SOLUTION: An inputted clock signal F and a delay clock signal delayed by a delay adjustment delay line 11 are inputted to an exclusive OR circuit 12 to take exclusive OR. A multiplying clock signal H according to the phase difference between the signals F and G is outputted from the circuit 12, electric charge is charged and discharged by a loop filter 13 to generate a delay quantity adjusting signal, to adjust the delay quantity of the line 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock multiplying circuit for multiplying a clock signal input from the outside.

[0002]

2. Description of the Related Art Conventionally, a clock multiplication circuit composed of a logic circuit and a clock multiplication circuit using a PLL circuit have been known. FIG. 10 is a diagram showing a conventional clock multiplication circuit constituted by a logic circuit, and FIG.
6 is a timing chart of the clock multiplication circuit shown in FIG.

A clock multiplication circuit 110 shown in FIG.
It comprises a delay circuit 111 composed of multi-stage gate circuits and an exclusive OR circuit 112. The clock multiplying circuit 110 includes a clock signal A having a frequency _fCLK.
Is entered. The input clock signal A is delayed by a predetermined delay amount by a multi-stage gate circuit constituting the delay circuit 111, and a delayed clock signal B as shown in FIG. 11 is generated. These delayed clock signal B and the clock signal A is inputted to the exclusive OR circuit 112 exclusive OR is taken, which multiplied clock signal C having a frequency twice 2f _CLK of the frequency f _CLK of the input clock signal A by the Is output. The arrow shown in FIG. 11 will be described later.

FIG. 12 is a diagram showing a conventional clock multiplication circuit using a PLL circuit. Clock multiplier circuit 130 shown in FIG. 12 is inputted from the outside, the frequency f _CLK
The phase comparator 131 outputs a phase difference signal by comparing the phase of the reference signal C with a feedback signal D described later. The charge pump 132 outputs a signal of a voltage level corresponding to the phase difference signal. A loop filter 133 that converts the obtained signal into a control voltage signal E having a DC level, a voltage control oscillator 134 that outputs an oscillation signal F having an oscillation frequency corresponding to the control voltage signal E, and a frequency division circuit that divides the frequency of the oscillation signal F by N. And a frequency divider 135 for generating the feedback signal D. In the clock multiplication circuit 130, the reference signal C and the feedback signal D
The control voltage signal E is automatically adjusted to match the phase of the reference signal C. As a result, the oscillation signal F having a frequency Nf _CLK that is N times the frequency f _CLK of the input reference signal C is output from the voltage control oscillator 134. .

[0005]

The above-described clock multiplication circuit composed of a logic circuit requires only a small amount of circuit to operate at a high frequency and thus consumes only a small amount of power. However, a delay circuit for generating a delayed clock signal is required. Is constituted by a multi-stage gate circuit, the delayed clock signal undergoes a time variation in the direction of the arrow shown in FIG. 11 depending on the temperature, voltage, and process. Therefore, the duty ratio of the multiplied clock signal fluctuates considerably depending on operating conditions such as temperature. Further, by configuring such a clock multiplication circuit in multiple stages, if a clock signal having a higher multiplication frequency is to be obtained, the relative frequency of the clock signal with respect to the above-described operating conditions is increased by the higher frequency. There is a problem that the fluctuation is large, and thus it is difficult to design a clock multiplication circuit at a high frequency.

On the other hand, in a clock multiplying circuit using a PLL circuit, a desired multiplied clock signal can be obtained by a combination of the operating frequency of the voltage controlled oscillator and the number of multiplications. , There is a problem that power consumption increases. The present invention has been made in view of the above circumstances, and has as its object to provide a clock multiplying circuit that can generate a multiplied clock signal having low power consumption and an accurate duty ratio while suppressing fluctuations due to operating conditions such as temperature. I do.

[0007]

According to the present invention, there is provided a clock multiplying circuit comprising: (1) a delay circuit for receiving a clock signal and delaying the inputted clock signal so that the delay amount can be adjusted; A logic synthesis circuit that generates a multiplied clock signal by multiplying the input clock signal by logically synthesizing the clock signal before and after being delayed by the delay circuit. (3) Before and after the delay by the delay circuit A delay amount adjusting circuit that adjusts a delay amount of the delay circuit according to a phase difference of a clock signal later.

The clock multiplying circuit of the present invention adjusts the delay amount of the delay circuit in accordance with the phase difference between the clock signal before and after being delayed by the delay circuit to obtain a multiplied clock signal. The feedback according to the phase difference is applied to the delay clock signal compared to the conventional technique of generating a delayed clock signal by a multi-stage gate circuit to obtain a multiplied clock signal. Can be kept small. Therefore, a multiplied clock signal having an accurate duty ratio is generated. Further, compared to a conventional clock multiplying circuit using a PLL circuit, the power consumption can be reduced because a simple circuit configuration is sufficient.

Here, the delay circuit is constituted by connecting a plurality of unit delay circuits for delaying an input clock signal so as to be adjustable in delay amount in series, and the logic synthesizing circuit is composed of the unit delay circuits. May be generated by logically synthesizing a clock signal including a clock signal of a node to which the input clock signal is connected, to generate a multiplied clock signal obtained by multiplying the input clock signal.

With such a configuration, it is possible to suppress a fluctuation due to an operating condition such as a temperature and to generate a high-multiplication clock signal having an accurate duty ratio. Therefore, it is possible to obtain a clock multiplication circuit that can handle up to high frequencies.

[0011]

Embodiments of the present invention will be described below. FIG. 1 is a circuit diagram of a clock multiplying circuit according to a first embodiment of the present invention. Clock multiplication circuit 1 shown in FIG.
0, a delay adjustment delay line 11 (an example of a delay circuit according to the present invention), an exclusive OR circuit 12,
A loop filter 13 is provided.

The delay adjustment delay line 11 has a frequency f
A clock signal F of _CLK is input, and the input clock signal F is delayed to adjust the delay amount to generate a delayed clock signal G. The exclusive OR circuit 12 has a DLL
(Delay Line Loop) or PLL
(Phase Locked Loop) is a circuit used as a phase comparator of a circuit that performs phase adjustment using loop control. In the exclusive OR circuit 12, an exclusive OR of the clock signal F before being delayed by the delay adjustment delay line 11 and the delayed clock signal G after being delayed is obtained, whereby the clock signal F is output from the exclusive OR circuit 12. A multiplied clock signal H corresponding to the phase difference of the delayed clock signal G is output.

The loop filter 13 charges or discharges a charge based on the voltage level of the multiplied clock signal H from the exclusive OR circuit 12 to adjust the delay amount of the delay adjustment delay line 11. Generate I. In the present embodiment, the logic synthesizing circuit according to the present invention refers to a function of taking the exclusive OR of the clock signal F and the delayed clock signal G among the functions of the exclusive OR circuit 12, and also refers to the present invention. The delay amount adjusting circuit refers to a function of generating a multiplied clock signal H corresponding to a phase difference between the clock signal F and the delayed clock signal G among functions of the loop filter 13 and the exclusive OR circuit 12.

In the clock multiplication circuit 10 of the present embodiment,
The clock signal F and the delayed clock signal G from the delay adjustment delay line 11 are input to the exclusive OR circuit 12, and the multiplied clock signal H output from the exclusive OR circuit 12 passes through the loop filter 13 to the delay adjustment delay line 11 is fed back to the DLL. This clock multiplication circuit 10
The feedback operation is stabilized when the phase of the input clock signal F and the phase of the delayed clock signal G are shifted by π / 2. Hereinafter, a state until the feedback operation is stabilized will be described with reference to FIGS.

FIG. 2 is a timing chart of the clock multiplication circuit shown in FIG. FIG. 2A shows a timing chart when the phases of the input clock signal F and the delayed clock signal G are shifted by π / 2 or more before the feedback operation is stabilized. On the other hand, FIG.
(B) shows that the phase of the input clock signal F and the phase of the delayed clock signal G after the feedback operation is stabilized are π.
2 shows a timing chart when there is a shift of / 2. In the clock multiplication circuit 10 of the present embodiment, a feedback operation is performed as follows.

(1) The exclusive OR circuit 12 includes a clock signal F shown in FIG. 2A and a delayed clock signal delayed by the delay adjustment delay line 11 and shifted in phase from the clock signal F by π / 2 or more. G is input, and the exclusive OR circuit 12 outputs a multiplied clock signal H. In the duty ratio of the clock signal H, the width on the “L” level side is shorter than the width on the “H” level side. Therefore, in the loop filter 13, the charge time is the discharge time. Longer than Accordingly, the voltage level of the delay adjustment signal I output from the loop filter 12 gradually increases as shown in FIG.

(2) When the voltage level of the delay adjustment signal I rises, the delay time of the delay adjustment delay line 11 becomes shorter. (3) As the delay time of the delay adjustment delay line 11 becomes shorter, the phase shift between the clock signal F and the delayed clock signal G becomes smaller. The above operations (1), (2) and (3) are repeated,
The phase difference between clock signal F and delayed clock signal G is π / 2
As shown in FIG. 2B, the multiplied clock signal H output from the exclusive OR circuit 12 becomes “H” as shown in FIG.
The width of the level becomes equal to the width of the “L” level. Therefore, in the loop filter 13, the charge time and the discharge time become uniform, and the delay amount adjustment signal I, which is the control voltage in the DLL configuration, is controlled. The voltage level stabilizes. When the voltage level of the delay amount adjustment signal I is stable, the clock signal F and the delayed clock signal G
Is π / 2, the duty ratio of the multiplied clock signal H output from the exclusive OR circuit 12 is 50%, and its frequency is twice the frequency of the input clock signal F. . As described above, in the clock multiplying circuit 10 of the present embodiment, feedback is applied to the delay adjustment delay line 11 according to the phase difference between the clock signal F and the delayed clock signal G, and the delayed clock signal G is generated. Compared with the conventional technique of generating a delayed clock signal by a multi-stage gate circuit to obtain a multiplied clock signal, the time variation of the delayed clock signal G due to operating conditions such as temperature can be reduced. Therefore, a multiplied clock signal F having an accurate duty ratio is generated.
Compared with a conventional clock multiplication circuit using a PLL circuit, the only part that operates at a high speed is the exclusive OR circuit 12 that logically synthesizes the clock signal F and the delayed clock signal G, and therefore has a simple circuit configuration. Therefore, power consumption can be reduced.

FIG. 3 is a circuit diagram of the delay adjustment delay line shown in FIG. FIG. 3A shows an equivalent circuit of the delay adjustment delay line 11 shown in FIG. 1, and FIG. 3B shows a circuit diagram of the delay adjustment delay line 11. As shown in FIG. 3B, the delay adjustment delay line 11 has PMOS transistors 11a and NMO in order from the power supply _VDD side, the gates of which are connected to each other.
An inverter 11_1 composed of S transistors 11b and 11c and an NMOS transistor 11d connected in parallel with the NMOS transistor 11c is provided between the node N1 and the ground GND. In addition, the inverter 11_
The gate is connected to the first output side connected to each other, PMOS transistor 11e from the power source V _DD side in order,
An inverter 11_2 including NMOS transistors 11f and 11g and an NMOS transistor 11h connected in parallel with the NMOS transistor 11g is provided between the node N2 and the ground GND. The gates of the NMOS transistors 11d and 11h are connected to each other.

In the delay adjustment delay line 11 configured as described above, when the clock signal F becomes “H” level, the PMOS transistor 11 of the inverter 11_1
“a” is turned off, the NMOS transistors 11 b and 11 c are turned on, and the node N shifts from “H” to “L”. Then, the PMOS transistor 11e of the inverter 11_2 is turned on, and the NMOS transistor 11
f and 11g are turned off, and the “H” level is output as the delayed clock signal G. At this time, if the delay amount adjustment signal I is at “L” level, the NMOS transistor 11d
Does not contribute to the transition of the node N from 'H' to 'L', the time required for the transition becomes longer, and the delayed clock signal G
Becomes large. Also, the delay amount adjustment signal I
When the level becomes higher than the L 'level, the NMOS transistor 11
Since d contributes to the transition from “H” to “L” of the node N, the time required for the transition is shorter than when the delay amount adjustment signal I is at the “L” level, and the delay amount of the delayed clock signal G is Become smaller. Therefore, the “H” level of the delayed clock signal G is output with a delay amount corresponding to the voltage level of the delay amount adjustment signal I with respect to the input clock signal F. still,
The same applies when the "L" level of the delayed clock signal G is output. In this case, the PMOS transistor 11
a, the NMOS transistor 11h plays the above-mentioned role of the PMOS transistor 11e and the NMOS transistor 11d.

FIG. 4 is an example of a circuit diagram of the loop filter shown in FIG. The loop filter 13 has a resistor 13a having one end to which the multiplied clock signal H is input, a resistor 13b having one end connected to the other end of the resistor 13a, and a resistor 13b having one end connected to the other end of the resistor 13b. And a capacitor 13c connected to the ground GND.

Here, an “H” level voltage is input to the resistor 13 a constituting the loop filter 13 as the multiplied clock signal H. Then, charge is charged to the capacitor 13c via the resistors 13a and 13b, and a delay amount adjustment signal I corresponding to the charged charge is output. Next, an “L” level voltage is input as the multiplied clock H. Then, the charge charged in the capacitor 13c is discharged via the resistors 13b and 13a, and the delay amount adjustment signal I corresponding to the discharged charge is output.

FIG. 5 shows a second example of the clock multiplication circuit of the present invention.
It is a circuit diagram of an embodiment. The same components as those of the clock multiplying circuit 10 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The clock multiplication circuit 20 shown in FIG. 5 has a configuration in which two clock multiplication circuits 10 shown in FIG. 1 are connected in series. The clock signal F input to the clock multiplication circuit 20 is supplied to the clock multiplication circuit 1
0 is converted into a multiplied clock signal H1 having a double frequency and a duty ratio of 50%, and the multiplied clock signal H1 is further multiplied by a clock multiplying circuit 10 in a subsequent stage to a multiplied clock H2 having a double frequency and a duty ratio of 50%.
Is converted to Therefore, in the clock multiplying circuit 20 of the present embodiment, a multiplied clock signal H2 that is four times the input clock signal F and has a duty ratio of 50% is obtained.

In this embodiment, the clock multiplication circuit 1
0 has been connected in series, but the clock multiplication circuit 10 is connected in series with three, four,.
By obtaining a multiplied clock signal with a high multiplication, such as 6 times, and a duty ratio of 50%, it is possible to cope with high frequencies. FIG. 6 is a circuit diagram of a clock multiplying circuit according to a third embodiment of the present invention.

The clock multiplication circuit 30 shown in FIG. 6 includes a delay circuit 31, a logic synthesis circuit 32, and a delay amount adjustment circuit 3.
3 are provided. The delay circuit 31 includes a delay adjustment circuit 31_1 including unit delay circuits 31_1a and 31_1b.
And a delay adjustment circuit 31_2 including unit delay circuits 31_2a and 31_2b. Logic synthesis circuit 3
2 includes an exclusive NOR circuit 32a, an exclusive OR circuit 32b, and an AND gate 32c. The delay amount adjusting circuit 33 includes an exclusive OR circuit 33a and a loop filter 33b.

In the clock multiplying circuit 30 of the present embodiment,
An external clock signal J and a unit delay circuit 31_1b
And the delay clock signal L at the node where the unit delay circuits 31_2a are connected to each other is input to the exclusive OR circuit 33a. Exclusive OR circuit 33a
Now, the input clock signal J and the delayed clock signal L
And the exclusive OR circuit 33a outputs a signal corresponding to the phase difference between the clock signal J and the delayed clock signal L from the exclusive OR circuit 33a. In the loop filter 33b, charging and discharging of electric charges according to this signal are performed, and a delay amount adjustment signal is output from the loop filter 33b. The delay amount adjustment signals are input to the delay adjustment delay lines 31_1 and 31_2, and the delay adjustment delay lines 31_1 and 31_
2 is adjusted.

FIG. 7 is a circuit diagram of the clock multiplication circuit shown in FIG.
6 is a timing chart after a delay amount is adjusted. As shown in FIG. 7, delayed clock signals K and L having phases shifted by π / 4 and π / 2, respectively, from the input clock signal J are output from the unit delay circuits 31_1a and 31_1b. These delayed clock signals K and L are input to an exclusive NOR circuit 32a, and an exclusive NOR operation is performed, whereby a clock signal O is output.
Further, a delay clock signal M whose phase is shifted by 3 / 4π with respect to clock signal J is output from unit delay circuit 31_2a. The delayed clock signal M and the clock signal J are input to the exclusive OR circuit 32b to perform an exclusive OR operation, whereby the clock signal P is output. The clock signal O and the clock signal P are input to the AND gate 32c, and the AND gate 32c outputs a multiplied clock signal Q that is four times the input clock signal J and has a duty ratio of 50%. As described above, in the present embodiment, a multiplied clock signal that is multiplied by a high frequency with a simple circuit configuration is generated, so that a clock multiplying circuit that consumes low power and can handle high frequencies is obtained.

In the present embodiment, the delay circuit has been described as having a 2 × 2 stage configuration in which each of two delay adjustment delay lines is provided with two unit delay circuits. However, the present invention is not limited to this. , The delay circuit has a 2 × N stage configuration in which each of N delay adjustment delay lines is provided with two unit delay circuits, and a clock signal input from each node connected to each unit delay circuit , A delayed clock signal having a phase shifted by π / 2N may be output, and the delayed clock signal may be synthesized by a logic circuit to obtain a clock signal of a high frequency.

FIG. 8 shows a fourth embodiment of the clock multiplication circuit of the present invention.
It is a circuit diagram of an embodiment. The same components as those of the clock multiplying circuit 30 shown in FIG. 6 are denoted by the same reference numerals, and redundant description will be omitted. The clock multiplication circuit 40 shown in FIG.
Compared with the clock multiplication circuit 30 shown in FIG. 6, the delay adjustment delay line 41_1 including the unit delay circuits 41_1a and 41_1b and the unit delay circuits 41_2a and 41_
The difference is that a delay adjustment delay line 41_2 composed of 2b is added and that the exclusive OR circuit 33a is replaced with a phase comparator 42. In the clock multiplying circuit 30, the exclusive OR circuit 33a and the loop filter 33b use the delay adjusting delay lines 31_1 and 31_2 so that the phase difference between the input clock signal J and the delayed clock signal L becomes π / 2.
In the clock multiplication circuit 40 of the present embodiment, the input clock signal J and the clock signal J are transmitted to the delay adjustment delay line 31_1 by the phase comparator 42 and the loop filter 33b, which will be described in detail later. , 3
The delay adjustment delay lines 31_1, 31_2, 41_1, and 41 are adjusted so that the phase difference between the delayed clock signals N delayed via 1_2, 41_1, and 41_2 becomes zero.
_2 is adjusted. As a result, a multiplied clock signal Q having a duty ratio of 50%, which is four times the input clock signal J, is obtained. Note that each of the clock signals K, L,
The timings of M, O, P, and Q are the same as those in the timing chart shown in FIG.

FIG. 9 is an example of a circuit diagram of the phase comparator shown in FIG. The phase comparator 42 shown in FIG. 9 includes flip-flops 42a and 42b, an AND gate 42c, an inverter 42d, and an inverter 42g including a PMOS transistor 42e and an NMOS transistor 42f. The clock signal J and the delayed clock signal N are input to the flip-flops 42a and 42b. When the phase of the delayed clock signal N lags behind the phase of the clock signal J, the data of “H” level is taken into the flip-flop 42a at the rising edge of the clock signal J, and the “H” data is output from the flip-flop 42a. A level signal is output. This "H" level signal is inverted by the inverter 42d to become an "L" level signal.
As a result, the PMOS transistor 42e is turned on, and the signal R at the "H" level is output from the inverter 42g. Since the charge is charged in the loop filter 33b shown in FIG. 8 by the signal H of the "H" level, the potential of the delay amount adjustment signal output from the loop filter 33b is high, and therefore the phase of the delay clock signal N advances. It will be.

On the other hand, when the phase of the delayed clock signal N is ahead of the phase of the clock signal J, the flip-flop 42b
And the flip-flop 42b outputs an "H" level signal. This "H" level signal causes the NMOS transistor 42
f is turned on, and a signal R of an “L” level is output from the inverter 42g. This "L" level signal R
Since the charge of the loop filter 33b shown in FIG. 8 is discharged, the potential of the delay amount adjustment signal output from the loop filter 33b is low, and the phase of the delay clock signal N is delayed. Note that the clock signals J,
At the time when the flip-flops 42a and 42b both output the "H" level signals at the rising edges of the respective delayed clock signals N, the AND gate 42c outputs
An H 'level signal is output. The flip-flops 42a and 42b are reset once by this "H" level signal, and wait for the next rising edge of the clock signal J and the delayed clock signal N.

[0031]

As described above, according to the present invention,
It is possible to generate a multiplied clock signal having an accurate duty ratio with low power consumption and suppressed fluctuation due to operating conditions such as temperature. Further, it is possible to obtain a clock multiplication circuit that can handle up to high frequencies.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of a clock multiplication circuit of the present invention.

FIG. 2 is a timing chart of the clock multiplication circuit shown in FIG.

FIG. 3 is a circuit diagram example of a delay adjustment delay line shown in FIG. 1;

FIG. 4 is a circuit diagram example of the loop filter shown in FIG. 1;

FIG. 5 is a circuit diagram of a clock multiplier circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a clock multiplying circuit according to a third embodiment of the present invention.

7 is a timing chart of the clock multiplying circuit shown in FIG. 6 after a delay amount is adjusted.

FIG. 8 is a circuit diagram of a clock multiplier circuit according to a fourth embodiment of the present invention.

9 is an example of a circuit diagram of the phase comparator shown in FIG.

FIG. 10 is a diagram showing a conventional clock multiplication circuit composed of only a logic circuit.

11 is a timing chart of the clock multiplication circuit shown in FIG.

FIG. 12 is a diagram showing a conventional clock multiplying circuit using a PLL circuit.

[Explanation of symbols]

10, 20, 30, 40 clock multiplication circuit 11, 31_1, 31_2, 41_1, 41_2 delay adjustment delay lines 11_1, 11_2, 42d, 42g inverters 11a, 11e, 42e PMOS transistors 11b, 11c, 11d, 11f, 11g, 11h, 4
2f NMOS transistor 12, 32b, 33a Exclusive OR circuit 13, 33b Loop filter 13a, 13b Resistance 13c Capacitor 31 Delay circuit 31_1a, 31_1b, 31_2a, 31_2b, 4
1_1a, 41_1b, 41_2a, 41_2b Unit delay circuit 32 Logic synthesis circuit 32a Exclusive NOR circuit 32c, 42c AND gate 33 Delay amount adjustment circuit 42 Phase comparator 42a, 42b Flip-flop

Claims (2)

[Claims] A clock signal is input, and a delay circuit for delaying the input clock signal so that the amount of delay can be adjusted, and a clock signal before and after being delayed by the delay circuit are logically synthesized to be input. A logic synthesizing circuit that generates a multiplied clock signal obtained by multiplying the clock signal that has been multiplied, and a delay amount adjusting unit that adjusts a delay amount of the delay circuit according to a phase difference between the clock signal before and after being delayed by the delay circuit. And a clock multiplication circuit. 2. The delay circuit according to claim 1, wherein a plurality of unit delay circuits for delaying an input clock signal to adjust a delay amount are connected in series. 2. The clock multiplication according to claim 1, wherein a clock signal including a clock signal of a connected node is logically synthesized to generate a multiplied clock signal obtained by multiplying the input clock signal. circuit.