JPH11251876A - Pulse generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend the input pulse width, to reduce the power of SRAM, to secure the generation timing of a pulse and to prevent malfunctions by providing a pulse width extending circuit. SOLUTION: When an inverted input signal Tin, whose pulse width is T1 is inputted to a pulse width extending circuit 1, a signal delayed by delay time d1 by a delay circuit 4 and Tin are logic-operated in a logic gate 5. Then, the output signal Tout of T1 +d1 is obtained. At that time, Tout can be extended twice as much as input pulse width T1 . In such a case, T1 -d1 becomes the operation margin of the pulse width extending circuit 1. Thus, the operation margin can sufficiently be obtained by extending pulse width and newly generating pulse width. Then, the non-active periods of a word line and a sense circuit are prolonged during a write recovery period in SEAM, and the power of SRAM can be reduced. The operation margin can be secured adequately, even if the pulse width is enlarged, and malfunction due to the fluctuation of power voltage and so on can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a new pulse by using the end timing of an input pulse as a trigger, and more particularly, to increasing the pulse width of a newly generated pulse and preventing malfunction. The present invention relates to a pulse generation circuit that can prevent the pulse generation.

[0002]

FIG. 13 is a diagram showing a conventional pulse generating circuit PG.

A conventional pulse generating circuit PG is an example in which a signal of negative logic is used as an input pulse, and has a delay circuit 2 and a logic gate 3. * (IN) is
A negative logic input pulse and φ is a positive logic output pulse. “*” Means that the signal in parentheses described thereafter is inverted.

FIG. 14 is a diagram showing a specific example of a delay circuit 2 used in a conventional pulse generation circuit PG.

The delay circuit 2 is a circuit in which 2 · m (m is a natural number) inverter gates 8 are connected in cascade.
That is, the delay circuit 2 is realized by connecting the inverter gates 8 in cascade even-numbered stages.

FIG. 15A shows a conventional pulse generating circuit P.
G shows the operation and the pulse width T _{1 of the} input pulse * (IN)
There is a timing chart showing the operation when longer than the delay time d ₂ of the delay circuit 2.

An input pulse * (I
N), the delay circuit 2 outputs a pulse delayed by the delay time d _2, and the logic gate 3 outputs a pulse φ of pulse width T ₂ starting from the end timing of the input pulse * (IN). . In this case, the pulse width T of the output pulse φ is
₂ = delay time d _2. By adjusting the delay time d ₂ , the pulse width T ₂ of the output pulse φ can be set.

For example, if a write control signal in an SRAM is input to a pulse generation circuit PG, a pulse is generated during a write recovery period (time from writing of predetermined data to the SRAM to return to a state where read operation is possible). Since the circuit PG can generate a signal for controlling the word line and the sense circuit to be inactive, only the power corresponding to the time when the word line and the sense circuit become inactive can be used for the SRAM.
Power can be reduced.

[0009]

By the way, in the above conventional example, the pulse width of the pulse generated by the pulse generation circuit PG is short, and the word line and the sense circuit are not operated for a part of the write recovery period. The SRAM can be activated, so that the power consumption of the SRAM cannot be sufficiently reduced.

FIG. 15B shows a conventional pulse generating circuit P.
In G, the delay time d ₂ is equal to the pulse width T _{1 of the} input pulse.
6 is a timing chart illustrating an operation in a case where the distance is larger than the threshold.

In order to sufficiently reduce the power consumption of the SRAM, the pulse width of the pulse generated by the pulse generation circuit PG should be made longer. For this purpose, the delay time d ₂ is longer than the pulse width T ₁ of the input pulse. Can be lengthened. In this case, as shown in FIG. 15B, the generation timing of the output pulse φ is determined by the input pulse *
This is irrelevant to the end timing of (IN), so that the pulse width cannot be increased, and the power consumption of the SRAM cannot be sufficiently reduced.

On the other hand, the delay time d in the delay circuit 2_Two 
With the pulse width T of the input pulse₁ When set smaller than
In any case, the operating margin (T₁ -D_Two A) less power
At the time of actual operation due to fluctuations in voltage, etc., as shown in FIG.
As before, the delay time d _Two Is the pulse width T₁ than
Can be large. In this case, the output pulse φ is generated.
Raw timing is the end timing of input pulse * (IN)
Out of sync.

As described above, when the generation timing of the output pulse φ is not synchronized with the end timing of the input pulse * (IN), the pulse generation circuit PG is applied and the SRAM is applied.
Even if an attempt is made to control the word line or the sense circuit to be inactive during the write recovery period, the inactive period cannot be made longer than the pulse width of the write control signal.
There is a problem that the power consumption of the SRAM cannot be sufficiently reduced.

In the above conventional example, the operation margin (T
_{Since 1−} d ₂ ) is small, even when a pulse close to the pulse width of the input pulse is generated, the timing of deactivating the word line may be shifted due to power supply noise or the like during actual operation. In this case, In a low-voltage SRAM, there is a problem that data written in a memory cell is destroyed and a malfunction occurs.

According to the present invention, a pulse having a pulse width larger than that of an input pulse can be output. Even when a pulse having a pulse width close to the pulse width of the input pulse is generated, the pulse is generated due to power supply noise or the like. It is an object of the present invention to provide a pulse generation circuit that does not shift timing.

[0016]

According to the present invention, there is provided a circuit for generating a new pulse by using the end timing of an input pulse as a trigger, comprising: a pulse width extending circuit for extending the pulse width of the input pulse; And a pulse generating means for generating a new pulse using the pulse expanded by the above and the input pulse.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing a pulse generation circuit PG1 according to a first embodiment of the present invention.

The pulse generation circuit PG1 has a pulse width expansion circuit 1 for inputting a negative logic signal as an input pulse and extending the pulse width, a delay circuit 2, and a logic gate 3.
This circuit receives a negative logic input pulse * (IN) and outputs a positive logic output pulse φ. Note that “*” indicates
This means that the signal in parentheses shown after “*” is inverted.

The delay circuit 2 is a circuit similar to the circuit shown in FIG. The logic gate 3 has inversion means for inverting the output pulse of the delay circuit 2 and an AND gate. The logic gate 3 is an example of a pulse generation unit that generates a new pulse using the pulse expanded by the pulse width expansion circuit and the input pulse. The pulse generating circuit PG1 is different from the conventional example in that the pulse generating circuit PG1 has a pulse width extending circuit 1.

That is, the pulse generation circuit PG1 is a circuit for generating a new pulse with the end timing of an input pulse as a trigger. The pulse generation circuit PG1 expands the pulse width of the input pulse and the pulse width expansion circuit. 9 is an example of a pulse generation circuit including a pulse generation unit that generates a new pulse using the input pulse and the input pulse.

FIG. 2 is a circuit diagram showing a specific example of the pulse width extending circuit 1 in the pulse generating circuit PG1.

The pulse width extending circuit 1 has a delay circuit 4 and a logic gate 5, inputs a negative logic input signal * (T _IN ), and outputs a negative logic output signal * (T _OUT ). Circuit. Logic gate 5 is an AND gate.

FIG. 3 is a timing chart showing the operation of the pulse width extending circuit 1 in the above embodiment.

Input signal * (T _IN ) to pulse width extending circuit 1
Is input, the delay circuit 4 outputs a signal delayed by the delay time d ₁ of the delay circuit 4. The logic gate 5 performs a logical operation on the signal delayed by the delay circuit 4 and the input signal * (T _IN ), so that the pulse width is increased by the delay time d ₁ more than the pulse width of the input signal * (T _IN ). The output signal * (T _OUT ) can be obtained.

The pulse width extending circuit 1 outputs the output signal * (T
a pulse width _{T 1 '(= T 1 +} d 1) of the _out), can be extended up to twice the pulse width T ₁ of the input signal * (T _in). In this case, the pulse width T ₁ of the input pulse−the delay time d ₁ is the operation margin of the pulse width extending circuit 1.

As a specific example of the delay circuit 2, the same circuit as the circuit shown in FIG. 14 may be used. That is,
A circuit in which 2 · m (m is a natural number) inverter gates 8 are connected in cascade in even stages may be used as the delay circuit 2.

FIG. 4 is a timing chart showing the operation of the pulse generation circuit PG1.

An input signal * (I
When N) is input, a signal having a pulse width T ₁ ′, which is longer than the pulse width of the input signal * (IN) by the delay time d ₁ of the delay circuit 2, is output to the pulse width expansion circuit 1. .
Subsequently, the delay circuit 2 outputs a signal having a pulse width T ₁ ′ delayed by the delay time d ₂ . As a result, the input signal * (I
And the starting point the rising edge of N), the pulse φ pulse width T ₂ is outputted. At this time, the pulse width T ₂ = delay time d ₁ + delay time d ₂ , and the pulse width T ₂ of the output pulse φ can be set by adjusting the delay time d ₁ and the delay time d _2. it can.

Therefore, according to the pulse generation circuit PG2, the pulse width of the output pulse can be made larger by the delay time d ₁ than in the conventional pulse generation circuit PG. For this reason, the operation margin (= pulse width T ₁ −delay time d)
₂ ) can be sufficiently ensured, and a pulse having a sufficient pulse width (a pulse having a pulse width approximately equal to or larger than the input pulse) can be obtained.

FIG. 5 is a circuit diagram showing a pulse generation circuit PG2 according to a second embodiment of the present invention.

The pulse generating circuit PG2 includes a circuit in which n pulse width extending circuits 1 are connected in cascade (n is an integer of 2 or more), a delay circuit 2, and a logic gate 3. The difference from the generator circuit PG1 is that n pulse width extending circuits 1 are connected in cascade.

FIG. 6 is a timing chart showing the operation of the pulse generation circuit PG2.

In the pulse generation circuit PG2, the pulse width of the pulse output from the n-th pulse width expansion circuit 1 (the pulse input to the delay circuit 2) is the input pulse * (IN)
Is expanded by n times the delay time d ₁ than the pulse width of Therefore, in the pulse generating circuit PG2, the pulse width T ₂ of the output pulse φ is, n · (delay time d ₁₎ + the delay time d _2, as compared to the pulse generation circuit PG1, further the pulse width of the output pulse φ Can be bigger.

If the delay time d ₂ is reduced in the pulse generation circuit PG ₂ , a sufficient operation margin (= pulse width T ₁ -delay time d ₂ ) of the pulse width extending circuit 1 can be ensured, and the delay can be reduced. Even if the time d ₂ is reduced, by increasing the number n of stages of the pulse stretching circuit 1,
The pulse width T ₂ of the output pulse φ can be finely controlled.

Each pulse extension time (delay time) of n pulse width extension circuits 1 in the pulse generation circuit PG2.
d ₁ may be modified so that some or all of the n pulse width extending circuits 1 are set to different values. In this modification, the pulse width of the output pulse φ can be further increased similarly to the pulse generation circuit PG2, and the pulse width of the output pulse φ can be set more finely than in the case of the pulse generation circuit PG2. it can.

FIG. 7 is a circuit diagram showing a pulse generation circuit PG3 according to a third embodiment of the present invention.

The pulse generation circuit PG3 outputs a positive logic signal I
It has a pulse width extending circuit 1 ′ that receives N as an input pulse and extends the pulse width, a delay circuit 2, and a logic gate 6. Logic gate 6 has an inverter for inverting the output pulse of delay circuit 2 and an OR gate. The pulse generation circuit PG3 receives a positive logic input pulse IN and outputs a negative / positive logic output pulse * (φ). The pulse generation circuit PG3 is different from the pulse generation circuit PG1 in the logic gate 6 and the logic gate 7 used in the pulse width expansion circuit 1 ', but the other configuration is the same as the pulse generation circuit PG1.

FIG. 8 is a circuit diagram showing a specific example of the pulse width extending circuit 1 'in the pulse generating circuit PG3.

The pulse width extending circuit 1 ′ comprises a delay circuit 4,
A logic gate 7 for inputting a positive logic input signal T _IN and outputting a positive logic output signal T _OUT . Logic gate 7 is an OR gate.

FIG. 9 is a timing chart showing the operation of the pulse width extending circuit 1 'in the pulse generating circuit PG3.

FIG. 10 is a timing chart showing the operation of the pulse generation circuit PG3.

The operation of the pulse generation circuit PG3 is basically the same as that of the pulse generation circuit PG1, except that the polarity of the signal is inverted. The pulse width of the output pulse can be made larger than the pulse generation circuit PG by the delay time d ₁ , so that the operation margin (= pulse width T ₁₎
-A delay time d ₂ ) can be sufficiently ensured, and a pulse having a sufficient pulse width (a pulse having a pulse width approximately equal to or longer than the input pulse) can be obtained.

FIG. 11 is a circuit diagram showing a pulse generation circuit PG4 according to a fourth embodiment of the present invention.

The pulse generating circuit PG4 has a circuit in which n pulse width extending circuits 1 'are connected in cascade (n is an integer of 2 or more), a delay circuit 2, and a logic gate 6. The difference from the pulse generation circuit PG3 is that n pulse width extension circuits 1 'are connected in cascade.

FIG. 12 is a timing chart showing the operation of the pulse generation circuit PG4.

The operation of the pulse generating circuit PG4 is basically the same as that of the pulse generating circuit PG2, except that the polarity of the signal is inverted. The pulse width of the pulse output from the width extending circuit 1 ′ (the pulse input to the delay circuit 2) is
The pulse width of the input pulse IN is extended by n times the delay time d ₁ and the pulse width T ₂ of the output pulse φ is n ·
(Delay time d ₁ ) + Delay time d ₂ , and the pulse width of the output pulse φ can be further increased as compared with the pulse generation circuit PG 3. Therefore, the pulse generation circuit P
In G4, by reducing the delay time d _2, the operation margin of the pulse width expansion circuit - can be sufficiently secured (= pulse width T ₁ 'delay time d _2), also, the delay time d
_{Even if 2} is reduced, the pulse width T ₂ of the output pulse φ can be controlled by increasing the number n of stages of the pulse expansion circuit 1.

Further, each pulse extension time (delay time) d ₁ of the n pulse width extension circuits 1 ′ in the pulse generation circuit PG 4 is defined as a part or all of the n pulse width extension circuits 1 ′. Modifications may be made to set different values. In this modification, a pulse generation circuit PG
4, the pulse width of the output pulse φ can be further increased as compared with the pulse generation circuit PG3. According to this modification, the pulse width of the output pulse φ can be set more finely.

That is, in each of the above embodiments, a pulse width expansion circuit for expanding the pulse width of the input pulse and a pulse width expansion circuit for expanding the pulse width of the input pulse in the circuit for generating a new pulse triggered by the end timing of the input pulse. 9 is an example of a pulse generation circuit including pulse generation means for generating a new pulse by using a generated pulse and the input pulse.

According to each of the above-described embodiments, a circuit for extending the pulse width of an input pulse is provided, and a new pulse is generated using the expanded pulse and the input pulse, so that the operation margin is sufficiently increased. In addition, it is possible to generate a pulse having a pulse width approximately equal to or larger than the pulse width of the input pulse.

Therefore, when controlling the word line and the sense circuit to be inactive during the write recovery period in the SRAM, the inactive period is made longer than before by using the pulse generation circuits PG1 to PG4 of the above embodiment. Therefore, the power consumption of the SRAM can be further reduced. In particular, if the present invention is applied to an SRAM having a long cycle time, the power consumption can be further reduced.

Further, since the operation margin can be sufficiently secured even if the pulse width is widened, malfunctions due to fluctuations in the power supply voltage and the like can be prevented. , It is possible to prevent more malfunctions due to fluctuations in the power supply voltage and the like.

In the above case, the pulse generating means includes a delay circuit for delaying the pulse output from the pulse width extending circuit, and a delay circuit between the end of the input pulse and the end of the pulse output from the delay circuit. And a logic gate that outputs a pulse having a pulse width of? Further, the pulse width extending circuit is a circuit in which a plurality of the pulse width extending circuits are connected in cascade, whereby the pulse extending time can be increased. Further, each of the plurality of cascade-connected pulse width extension circuits is a circuit in which the pulse width of each output pulse is individually controlled, thereby finely controlling the pulse extension time of the entire pulse generation circuit. be able to.

[0053]

According to the present invention, it is possible to output a pulse having a pulse width larger than that of an input pulse. This has the effect that the pulse generation timing does not shift.

[Brief description of the drawings]

FIG. 1 shows a pulse generation circuit P according to a first embodiment of the present invention.
It is a circuit diagram of G1.

FIG. 2 is a circuit diagram showing a specific example of a pulse width extending circuit 1 in the pulse generating circuit PG1.

FIG. 3 is a timing chart showing an operation of the pulse width extending circuit 1 in the embodiment.

FIG. 4 is a timing chart showing an operation of the pulse generation circuit PG1.

FIG. 5 shows a pulse generation circuit P according to a second embodiment of the present invention.
It is a circuit diagram showing G2.

FIG. 6 is a timing chart showing an operation of the pulse generation circuit PG2.

FIG. 7 shows a pulse generation circuit P according to a third embodiment of the present invention.
It is a circuit diagram showing G3.

FIG. 8 is a circuit diagram showing a specific example of a pulse width extending circuit 1 'in the pulse generating circuit PG3.

FIG. 9 is a timing chart showing an operation of the pulse width extending circuit 1 'in the pulse generating circuit PG3.

FIG. 10 is a timing chart showing the operation of the pulse generation circuit PG3.

FIG. 11 is a circuit diagram showing a pulse generation circuit PG4 according to a fourth embodiment of the present invention.

FIG. 12 is a timing chart showing the operation of the pulse generation circuit PG4.

FIG. 13 is a diagram showing a conventional pulse generation circuit PG.

FIG. 14 is a diagram showing a specific example of a delay circuit 2 used in a conventional pulse generation circuit PG.

FIG. 15 is a timing chart showing an operation of a conventional pulse generation circuit PG.

[Explanation of symbols]

PG1～PG4 ... pulse generating circuit, 1,1 '... pulse width expansion circuit, 2,4 ... delay circuit, 3,5,6,7 ... logic gate, 8 ... inverter _{gate, T 1, T 1',} T 2 ... pulse width, d _1, d ₂ ... delay time.

Claims (4)

[Claims] 1. A circuit for generating a new pulse with an end timing of an input pulse as a trigger, comprising: a pulse width extending circuit for extending a pulse width of the input pulse; a pulse extended by the pulse width extending circuit; And a pulse generating means for generating a new pulse using the pulse. 2. The pulse generating means according to claim 1, wherein said pulse generating means includes: a delay circuit for delaying a pulse output from said pulse width extending circuit; and an end time of a pulse output from said delay circuit from an end time of said input pulse. And a logic gate for outputting a pulse having a pulse width of up to the above as the new pulse. 3. The pulse generation circuit according to claim 1, wherein said pulse width expansion circuit is a circuit in which a plurality of said pulse width expansion circuits are connected in cascade. 4. The pulse generation circuit according to claim 2, wherein each of the plurality of cascade-connected pulse width extension circuits is a circuit in which the pulse width of each output pulse is individually controlled. .