JPH11251546A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a stacked DRAM of high accuracy as well as high density, and its manufacturing method. SOLUTION: A plurality of gate electrodes 5 are formed in parallel with each other, by depositing an insulating film and a conductive material on a semiconductor substrate 1. An impurity diffused layer 6 is formed on an element forming region 3 of the surface part of the semiconductor substrate 1, isolated by an amount equivalent to the width of the gate electrodes 5. After an embedded electrode 16 has been formed, an interlayer insulating film 12 is deposited on the entire surface, and a plurality of bit line trenches 27 intersecting the gate electrodes 5 perpendicularly are formed in parallel with each other. A plurality of bit lines 8 having an interlayer insulating film 13 on the upper surfaces are formed by depositing a conductive material and an insulating film in order on the bit line trenches 27, the interlayer insulating film 12 is patterned by using the interlayer insulating film 13 as a mask, and capacitor apertures 28 are formed above the impurity diffused layer 6. An accumulation electrode 17 is formed by depositing a conductive material inside the capacitor apertures 28 in such a manner that the height of the upper end is made at most the height of the upper surface of the interlayer insulating film 13, and a capacitor insulating film 18 and an upper electrode 19 are formed successively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a stacked DRAM and a method of manufacturing the same.

[0002]

2. Description of the Related Art There are two types of stacked DRAMs, a conventional stacked cell having a capacitor below a bit line and a COB type cell having a capacitor above a bit line.

A conventional stacked DRAM cell will be described with reference to the drawings.

FIG. 73 is a schematic sectional view showing an example of a semiconductor memory device having a conventional stack cell according to the prior art.

In the semiconductor memory device 100 shown in FIG. 1, a lower electrode 117, a dielectric film 118 and an upper electrode 1
19 is formed below the bit line 135, the bit line contact 1 between the gate electrodes 105 is formed.
26 must be formed. Therefore, the capacitor region is limited to a region from above the element isolation insulating film 102 to above the on-gate insulating film 107 on the gate electrode 105a, and there is a problem that it is difficult to secure a sufficient area. .

In order to solve this problem, as in the semiconductor memory device 110 shown in FIG. 75, the shape of the lower electrode 137 is changed to a shape in which the width of the upper portion is changed while the area of the bottom surface is not changed. Membrane 138 and upper electrode 139
There is an example in which the area of the capacitor region is increased by forming.

However, in the case of semiconductor memory device 110, a large step is generated between the cell portion and the peripheral semiconductor region due to the change in the thickness of lower electrode 137. There was a problem that it increased.

FIG. 74 shows a conventional COB.
FIG. 2 is a schematic cross-sectional view of an example of a semiconductor memory device including a pattern cell.

In the semiconductor memory device 120 shown in FIG. 1, since the capacitor portion is formed above the bit line 135, the advantage is that the shape of the capacitor can be freely designed and the area of the capacitor can be easily increased. there were.

[0010]

However, also in the semiconductor memory device 120, the height of the cell portion from the semiconductor substrate is increased by the thickness of the capacitor, so that a step is generated from the peripheral semiconductor region. Will be
Similar to the semiconductor memory device 110 shown in FIG. 75, there is a problem that the difficulty in the subsequent manufacturing process increases.

A conventional cell and CO
In any case of the B-type cell, since a lithography process is used to form the lower electrode of the capacitor, it is necessary to provide a margin for resist pattern alignment, and shortening in the long side direction occurs. There is a problem that the area of the region is limited.

Further, a storage node (Storage No.
Since the lithography process is required to form the contact 127 (hereinafter simply referred to as SN), there is a problem that the lithography process is increased by one process as compared with the trench type DRAM, and as a result, the manufacturing cost is increased. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a high-precision and high-density stack type DR without considering a margin for resist pattern alignment.
An object of the present invention is to provide a method for manufacturing such a stacked DRAM in a simple and small number of steps, while providing an AM.

[0014]

The present invention solves the above problems by the following means.

That is, according to the present invention (claim 1), an element formation region where a semiconductor element is to be formed and an element isolation insulating film formed so as to surround the element formation region are provided on the surface. A semiconductor substrate, first and second gate insulating films formed at predetermined positions in the element formation region, parallel to one side of the element formation region, and parallel to each other; and the first gate A first gate electrode formed on the insulating film and having an upper surface and side surfaces covered with the first insulating film;
A second gate electrode formed on the second gate insulating film and having an upper surface and side surfaces covered with a second insulating film; and a surface portion of the semiconductor substrate between the first and second gate electrodes. A first impurity diffusion layer formed on the first impurity diffusion layer and a second impurity formed on a surface of a peripheral portion of the element formation region at a distance from the first impurity diffusion layer by a width of the first gate electrode. A diffusion layer, a third impurity diffusion layer formed on a surface of a peripheral portion of the element formation region at a distance from the first impurity diffusion layer by a width of the second gate electrode; A first electrode formed between the second insulating films and extending over the first impurity diffusion layer and over any one of the element isolation insulating films adjacent thereto; A portion of the first electrode extending over the element isolation insulating film and a bottom surface Connected in a partial region, above the region of the element isolation insulating film, and on the first and second insulating films, so as to be substantially perpendicular to the first and second gate electrodes. The formed bit line, the third insulating film formed on the bit line, the second and third electrodes formed on the second and third impurity diffusion layers, respectively, A fourth insulating film formed above the element forming region and having an opening reaching the upper surfaces of the second and third electrodes; and a third insulating film deposited in the opening and having an upper end having a height of the third insulating film. Semiconductor storage, comprising: a storage electrode having a height equal to or less than the height of the upper surface of the substrate, a dielectric film formed to cover the storage electrode, and a top electrode formed to cover the dielectric film. An apparatus is provided.

Preferably, the opening is formed so as to overlap at least a part of the first and second insulating film regions.

It is preferable that the opening has a bottom surface extending into the second and third electrodes.

The first and second insulating films and the third insulating film are preferably formed of the same material, for example, a nitride film.

Further, it is more preferable that the cut surface of the opening along the bit line has a width at an upper portion wider than a width at a bottom portion.

Further, it is preferable that an oxide film is formed between the bit line and the upper surfaces of the first and second insulating films.

Further, according to the present invention (claim 8), a step of forming an element isolation insulating film surrounding an element formation region where a semiconductor element is to be formed on a surface portion of the semiconductor substrate; An insulating film is deposited and selectively removed, and at a predetermined position in the element formation region, parallel to one side of the element formation region, and so as to be parallel to each other, a first and a second. Forming a gate insulating film, depositing and selectively removing a conductive material on the semiconductor substrate, and forming a first gate electrode on the first gate insulating film and the second gate insulating film Forming the upper second gate electrode and, on the surface of the element formation region of the semiconductor substrate,
A first impurity diffusion layer between the gate electrodes, a second impurity diffusion layer separated from the first impurity diffusion layer by a width of the first gate electrode, the first impurity diffusion layer and the second impurity diffusion layer; Forming a third impurity diffusion layer separated by the width of the second gate electrode; and depositing an insulating film on the entire surface, and then selectively removing the insulating film to cover the upper surface and side surfaces of the first gate electrode. Forming one insulating film and a second insulating film covering the top and side surfaces of the second gate electrode; and depositing a conductive material over the entire surface, and then selectively removing the first impurity to remove the first impurity. A first electrode extending from above the diffusion layer to any one of the element isolation insulating films adjacent thereto, a second electrode on the second impurity diffusion layer, and a third impurity diffusion layer Forming a third electrode on top, depositing an interlayer insulating film on the entire surface, After selectively removing the inter-insulating film, a conductive material is deposited, and on the device isolation insulating film, substantially orthogonal to the first and second gate electrodes, and at the first electrode and the lower surface. A step of forming a connected bit line, a step of forming a third insulating film on the bit line, and selectively removing the interlayer insulating film on the element formation region; Forming a capacitor opening on the impurity diffusion layer; and depositing a conductive material in the capacitor opening to form a storage electrode having an upper end having a height equal to or less than an upper surface of the third insulating film. A semiconductor comprising: depositing a fourth insulating film on the storage electrode to form a dielectric film; and depositing a conductive material on the dielectric film to form an upper electrode. A method for manufacturing a storage device is provided.

The step of forming the bit line is performed in a portion of the interlayer insulating film which is substantially orthogonal to the first and second gate electrodes and which extends on the element isolation insulating film of the first electrode. It is preferable to form a bit line groove having a contact opening that reaches, and bury a conductive material in the bit line groove.

In the step of forming the capacitor opening, after forming a resist pattern, the interlayer insulating film is selectively removed to a depth smaller than the bottom of the bit line by isotropic etching using the resist pattern as a mask. It is good to do after doing.

Further, an oxide film is deposited on the entire surface between the step of forming the first to third electrodes and the step of depositing the interlayer insulating film, and then the first to third impurity diffusion layers are formed. And forming a capacitor groove in parallel with the first and second gate electrodes, the capacitor groove having a lower side of the cut surface along the bit line and shorter than the upper side.

Further, the step of forming the capacitor groove includes a step of etching so that the oxide film of a predetermined thickness remains between the first and second gate electrodes. The step of forming the groove is preferably a step of performing etching so that the oxide film having a thickness equal to or less than the predetermined thickness remains.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same portions are denoted by the same reference numerals, and description thereof will not be repeated. In each cross-sectional view, (a) is a cross-sectional view taken along the line AB in the plan view described immediately before, and (b) is a cross-sectional view taken along the line CD in the plan view.

First, a first example of the semiconductor memory device according to the present invention will be described.
An embodiment will be described with reference to the drawings.

FIG. 1 is a schematic plan view of a semiconductor memory device 10 according to the present embodiment. In the figure, a dashed line indicates a pattern on the surface of the semiconductor substrate, a broken line indicates a pattern on the first layer on the semiconductor substrate, and a solid line indicates a pattern on the second layer.

As shown in FIG. 1, a rectangular element formation region 3 isolated and isolated by an element isolation insulating film 2 (see FIG. 2) is shown on the surface of a p-type semiconductor substrate 1.

A gate electrode pattern 34 on which a gate electrode 5 (see FIG. 2) is formed is formed on the first layer on the semiconductor substrate 1 so as to be parallel to the short side of the element forming region 3 and parallel to each other. Are arranged at intervals.

The second layer on the semiconductor substrate 1 has a bit line pattern 35 on which the bit line 8 (see FIG. 2) is formed.
Are arranged at predetermined intervals so as to be substantially perpendicular to the gate electrode 5. Further, in a region between the bit line patterns 35, capacitor portions 30 for storing electric charges and insulating films 32 are alternately formed.

In a region between the gate electrodes 5 and between the bit lines 8 on the surface of the semiconductor substrate 1, As which is an n-type impurity is provided.
An impurity diffusion layer 6 (see FIG. 2) serving as a source or drain doped with P or P is formed. In a predetermined region between the gate electrode patterns 34 in the first layer on the semiconductor substrate 1 (see FIG. 18), the buried electrode 16 (see FIG.
Reference) is formed. This buried electrode connects the storage electrode 17 (see FIG. 2) of the capacitor portion 30 and the impurity diffusion layer 6 thereunder, and is separated from the impurity diffusion layer 6 by the width of the gate electrode 5 to form the insulating film 32. Is connected to the impurity diffusion layer 6 formed below the bit line pattern 35 and the elliptical bit line contact region 26 indicated by a broken line in the bit line pattern 35 adjacent to the insulating film 32.

That is, the semiconductor memory device 10 shown in FIG.
A capacitor unit 30 having one end grounded and storing an electric charge;
Bit line pattern 3 with electrode material such as tungsten (W)
5, a gate electrode 5 formed of a conductive film such as polysilicon in a region of a gate electrode pattern 34, and an element formation region 3 in a surface portion of the semiconductor substrate 1.
And an n-type impurity diffusion region 6 (see FIG. 2) serving as a source or a drain formed in a region between the gate electrodes 5 and a region between the bit lines 8. And a MOS field-effect transistor (hereinafter referred to as a MOS transistor) selectively connected to the MOS transistor 8.

The specific structure of the semiconductor memory device 10 will be described with reference to the sectional view of FIG.

FIGS. 2A and 2B are schematic cross-sectional views of the semiconductor memory device 10 shown in FIG. 1. FIG. 2A is a cross-sectional view taken along the line AB of FIG. 1, and FIG. It is sectional drawing in the D cut surface.

As shown in FIG. 1, an element formation region 3 (see FIG. 1) is defined by an element isolation insulating film 2 formed on the surface of a p-type semiconductor substrate 1. In the first layer on the semiconductor substrate 1, gate electrodes 5 made of a polysilicon film are formed at predetermined intervals via a gate oxide film 4. A gate protection film 7 as a first or second insulating film is formed of a nitride film on the side and upper surfaces of the gate electrode 5 to protect the gate electrode 5 and to isolate the gate electrode 5 from other elements.

In the sectional view of FIG. 2A, a region S1 is
The cross section in the region of the bit line 8 is shown. The insulating film 11 is deposited between the gate electrodes 5, but is formed in the elliptical bit line contact region 26 shown by the broken line in FIG. An embedded electrode 16, which is a first electrode for connecting to the impurity diffusion layer 6, is formed. An interlayer insulating film 12 is formed between the bit line 8 and the gate electrode 5 and the insulating film 11 except for the bit line contact region.

On the bit line 8, an interlayer insulating layer 13, which is a third insulating film, is deposited. The interlayer insulating film 12 and the interlayer insulating layer 13 protect the bit line 8 and insulate it from other elements. Separation is taking place.

The side surface of the bit line 8 is insulated by a side wall 14 formed of a nitride film or the like.

In the sectional view of FIG. 2A, the region S2 is
The cross section in the region between the bit lines 8 is shown.

An insulating film 32 is formed on gate electrode 5, and capacitor openings 28 are formed in these insulating films 32 at predetermined intervals. As also shown in the cross-sectional view of FIG.
A storage electrode 17 made of an electrode material such as ruthenium (Ru) is formed, and a capacitor insulating film 18 which is a dielectric film made of a BST film or the like including a region on the storage electrode 17 is formed of a DRA.
An upper electrode 19 is formed on the entire surface of the M cell region, and an upper electrode 19 is formed on the capacitor insulating film 18. The feature of the present invention lies in the shape of the storage electrode 17, wherein the height of the upper end of the storage electrode 17 is equal to or less than the height of the upper surface of the interlayer insulating layer 13.

Further, as shown in FIG. 2B, this storage electrode 17 is formed in a region between the bit lines 8, and unlike the conventional semiconductor memory device shown in FIGS. It is not formed in the area above and below the line 8. By adopting such a structure, the semiconductor is provided with a DRAM cell having a larger capacitor area without forming a step with a peripheral circuit portion within a limited cell area while forming the capacitor by close packing. A storage device is provided.

Next, the second embodiment of the semiconductor memory device according to the present invention will be described.
An embodiment will be described with reference to the drawings.

FIG. 3 is a schematic plan view of the semiconductor memory device 40 according to the present embodiment, and FIG.
3B is a cross-sectional view taken along the line AB, and FIG. 3B is a cross-sectional view taken along the line CD in FIG.

As shown in FIGS. 3 and 4, the semiconductor memory device 40 of this embodiment is the same as the semiconductor memory device 10 shown in FIG. Is a feature of the present embodiment.

That is, as shown in FIG. 4, of the opposing side surfaces of the capacitor opening 29, the side surface along the gate electrode 5 forms a gentle slope that is once inclined outward from substantially half the height, and is again formed inside. This is a point that the upper surface is formed to have a shape that returns to vertical at an upper end portion. By providing such a shape, the surface area of the storage electrode 17 can be increased as shown in FIG.

If the side surface along the gate electrode 5 is formed perpendicular to the semiconductor substrate 1, the storage electrode 17
The distance between the buried electrode 16 and the storage electrode 17 adjacent to each other via the inter-gate buried electrode 16 and the gate electrode 5 to which the gate electrode 5 is connected is shortened.
There is a risk of short circuit. Therefore, by making the shape of the side surface round, the distance between the embedded electrode 16 and the adjacent embedded electrode 16 can be increased, and a short circuit can be prevented. However, since the space between the bit lines 8 is designed with the minimum processing size, if the side surface parallel to the bit line 8 is rounded, the capacitor opening 29
The area of the bottom of the buried electrode 16 becomes excessively small,
And the area of the contact portion with the contact is reduced. Therefore, FIG.
As shown in FIG. 2B, the side surface parallel to the bit line 8 is kept vertical, and the side surface parallel to the gate electrode 5 is rounded as shown in FIG. A semiconductor memory device including a DRAM cell having a large-capacity capacitor while ensuring a contact area with electrode 16 is provided.

The formation of the storage electrode 17 is facilitated by forming the capacitor opening 29 in a rounded shape rather than in a direction perpendicular to the semiconductor substrate 1.

Next, the third embodiment of the semiconductor memory device according to the present invention will be described.
An embodiment will be described with reference to the drawings.

FIG. 5 is a schematic plan view of a semiconductor memory device 60 according to the present embodiment, and FIG.
5B is a cross-sectional view taken along a line AB in FIG. 5, and FIG. 5B is a cross-sectional view taken along a line CD in FIG.

As shown in FIGS. 5 and 6A and 6B, also in the semiconductor memory device 60 of the present embodiment, there is a characteristic point in the shape of the capacitor portion 61, and the other points are shown in FIG. It is substantially the same as the semiconductor memory device 10 shown.

That is, as shown in FIG. 6, regarding the shape of the side surface of the capacitor opening 48, the side surface parallel to the bit line 8 is kept perpendicular to the surface of the semiconductor substrate 1, and the side surface parallel to the gate electrode 5 is The point is that the surface is tapered from about 75 degrees to about 85 degrees.

By forming the capacitor portion 61 in such a shape, the embedded electrode 16 adjacent to the inter-gate embedded electrode 16 to which the storage electrode 17 is connected can be formed in the same manner as in the second embodiment. , The distance to the storage electrode 17 can be lengthened to prevent a short circuit.

Further, by forming the side surface of the capacitor opening 48 at an angle rather than perpendicularly to the semiconductor substrate 1, as in the second embodiment,
The formation of the storage electrode 17 is facilitated.

Next, the fourth embodiment of the semiconductor memory device according to the present invention will be described.
An embodiment will be described with reference to the drawings.

FIG. 7 is a schematic plan view of a semiconductor memory device 80 according to the present embodiment, and FIG.
7B is a cross-sectional view taken along the line AB, and FIG. 8B is a cross-sectional view taken along the line CD in FIG.

The feature of this embodiment lies in the material of the interlayer insulating film immediately below the bit line 8, and the other points are substantially the same as those of the semiconductor memory device 60 shown in FIG.

That is, as a material of the interlayer insulating film immediately below the bit line 8, TEOS (Tetra EthOxy Silage) or BP
An oxide film 42 is used instead of SG (Boron-doped Phosphor-Silicate Glass).

As described above, by using the oxide film 42 as the insulating film immediately below the bit line 8, the parasitic capacitance of the bit line 8 can be significantly reduced. Thus, a semiconductor memory device including a DRAM cell that can operate at higher speed is provided.

Next, a first embodiment of a method of manufacturing a semiconductor memory device according to the present invention will be described with reference to the drawings.

The present embodiment is a method for manufacturing the above-described first embodiment of the semiconductor memory device according to the present invention.

FIG. 9 is a schematic plan view showing a plane pattern of gate electrode 5 of semiconductor memory device 10 shown in FIG.
In each of FIGS. 10 to 12, FIG.
FIG. 10 is a cross-sectional view taken along the line AB in FIG. 9, and FIG. 9B is a cross-sectional view taken along the line CD in FIG. 9.
The region shown by the broken line in FIG. 9 is the element formation region 3.

First, as shown in FIGS. 10A and 10B, a shallow groove-shaped opening is formed in the surface of the p-type semiconductor substrate 1 except for the element formation region 3, and an insulating film is deposited. After that, STI (Shallow
An element isolation insulating film 2 having a (trench insulator) structure is formed.

Next, after an oxide film is formed on the entire surface, a polysilicon film is deposited, and a gate oxide film 4 and a gate electrode 5 are formed at predetermined intervals in parallel with each other by patterning using a resist (FIG. 9). reference).

After that, using this gate electrode 5 as a mask, an n-type impurity, for example, As is ion-implanted at a dose of 5 × 10 ¹⁹ cm ⁻² and an acceleration voltage of 15 KeV to form an impurity diffusion layer serving as a source or a drain. 6 is formed.

Next, a nitride film is deposited on the entire surface, and a gate protective film 7 covering the side and top surfaces of the gate electrode 5 is formed by patterning using a resist.

Next, as shown in FIGS. 11A and 11B, after an interlayer insulating film 11 such as BPSG is deposited on the entire surface, as shown in FIGS. After etching back to almost the height of the upper surface of the film 7, the surface is flattened by a chemical mechanical polishing method.

Next, as shown in the plan view of FIG. 13, a resist pattern 21 is formed in the hatched region of the same figure (see FIGS. 14A and 14B), and this resist pattern 21 is used. By the patterning, the interlayer insulating film 11 is selectively removed to expose the semiconductor substrate 1 as shown in FIGS. 15A and 15B.

Next, FIGS. 16, 17 (a) and 17 (b)
19, after the resist pattern 21 is removed, as shown in FIGS. 19A and 19B, a conductive material is applied to the entire surface by LP-CVD (Low Pressure-Chemical Vapor).
Deposition) and deposited by CDE (Chemical D
The buried electrode 16 serving as a contact portion between the capacitor portion and the impurity diffusion layer 6 of the MOS transistor is formed by etch back by ry Etcing or RIE (Reactive Ion Ething) or a chemical mechanical polishing method. As the conductive material, polycrystalline silicon or amorphous silicon is desirable.

FIG. 18 is a schematic plan view showing a plane pattern of the contact portion, and the hatched portion in FIG. 18 indicates a contact portion forming region. As is apparent from comparison with FIG. 13, this contact portion is formed in a region excluding the region of resist pattern 21 and gate electrode 5.

Next, a resist pattern 22 for bit line contact is formed. FIG. 20 is a schematic plan view showing the resist pattern 22. FIG. The elliptical region shown by the broken line in FIG. 4 is the bit line contact region 26, and the resist pattern 22 is formed in all regions except the bit line contact region 26.

Referring to the sectional views of FIGS. 21A and 21B, first, an interlayer insulating film 12 such as TEOS or BPSG is deposited on the entire surface, and then a resist pattern 22 is formed on the entire surface except for the bit line contact. To form

Next, as shown in FIGS. 22A and 22B, using the resist pattern 22 as a mask, the interlayer insulating film 12 is patterned by RIE to form openings for bit line contacts. Thereafter, as shown in FIGS. 23A and 23B, the resist pattern 22 is peeled off.

Next, a bit line groove 27 is formed. First,
24, a resist pattern 23 is formed on the entire surface excluding the bit line 8 region. The cross-sectional shape is as shown in FIGS.

RIE using the resist pattern 23
26, the interlayer insulating film 12 is patterned.
As shown in (a) and (b), a bit line groove 27 is formed.

Next, as shown in FIGS. 27A and 27B, after removing the resist pattern 23, a conductive material 8 'such as tungsten (W) is deposited in the bit line groove 27. As shown in FIGS. 28A and 28B, the surface is flattened by the chemical mechanical polishing method.

Next, as shown in FIGS. 29A and 29B, the thickness of the conductive material 8 ′ is reduced by etch back to form the bit line 8. Specifically, in the case of the above-mentioned tungsten, the etch back is performed by the RIE method using SF ₆ , CF ₄ gas or the like.

Thereafter, a silicon nitride film is formed on the entire surface by LP-C
Deposited by the VD method or the plasma CVD method, the surface is flattened by a chemical mechanical polishing method as shown in FIGS. 30A and 30B, and the interlayer insulating layer 13 is formed.

Next, a capacitor opening 28 which is a capacitor formation region is formed.

First, the shaded area in the plan view of FIG.
As shown in FIGS. 33A and 33B, an SN contact resist pattern 24 is formed, and the interlayer insulating film 12 is patterned by RIE using the resist pattern.
(A) and (b), as shown in FIG.
To form At this time, since the interlayer insulating layer 13 made of a silicon nitride film is deposited on the bit line 8, etching that can obtain a selectivity with the interlayer insulating film 12 made of an oxide film, for example, C ₄ F _When patterning is performed by an etching method using ₈ + O ₂ + CO gas or the like, only the SN contact resist pattern 24 and the interlayer insulating film 12 in a region other than the region where the interlayer insulating layer 13 is present are selectively removed. The remaining capacitor openings 28 are formed between the insulating films 32.

Next, as shown in FIGS. 34 (a) and (b), after the SN contact resist pattern 24 is peeled off, a silicon nitride film is deposited on the entire surface, and the silicon nitride film is etched back as shown in FIGS. As shown in FIG. 2B, sidewalls 14 are formed on the side surfaces of the bit lines 8 and the side surfaces of the insulating film 32. This protects the side wall of the bit line 8 that has been exposed again due to the formation of the capacitor opening 28, and facilitates the adhesion of a conductive material to the side surface of the capacitor opening 28 in the formation of the storage electrode 17 described below.

Next, the storage electrode 17 is formed in the capacitor opening 28.
To form That is, a conductive material, for example, ruthenium (Ru) is deposited on the entire surface by the CVD method, and the coating type oxide film S is formed.
After burying the capacitor opening 28 with OG (Spin On Glass) or the like, the buried material and the conductive material in the flat portion are removed by a chemical mechanical polishing method. The filler material is removed by wet etching, for example, with a dilute HF solution or the like, and as shown in FIGS. The storage electrode 17 extending to the upper side of the side wall 14 of the bit line 8 is formed.

Thereafter, a capacitor insulating film 18, for example, a BST film is deposited on the entire surface, and then an upper electrode 19 is deposited. As shown in FIGS. 37 (a) and 37 (b) and FIG. Complete the formation.

According to the method of manufacturing the semiconductor memory device of the present embodiment, the capacitor openings 28 are formed between the bit lines 8,
In addition, since the upper end of the storage electrode 17 does not exceed the upper surface of the interlayer insulating layer 13 on the bit line 8, a semiconductor memory having a high-density and large-capacity capacitor does not generate a step with the peripheral portion. The device can be manufactured. Also,
Since the capacitor opening 28 is formed in a self-aligned manner using the interlayer insulating layer 13 as a mask, there is no risk of misalignment occurring in the combination of the storage electrode pattern, the lower electrode contact pattern and the bit line 8.
This dramatically increases the processing accuracy of the capacitor,
Yield can be greatly improved. Further, since no lithography step is used, the number of steps is reduced, and the manufacturing cost can be reduced.

Next, a second embodiment of the method for manufacturing a semiconductor memory device according to the present invention will be described with reference to the drawings.

The present embodiment is a method for manufacturing the above-described second embodiment of the semiconductor memory device according to the present invention.

First, in the same manner as in the first embodiment, as shown in FIGS. 39A and 39B, the element isolation insulating film 2, the gate oxide film 4, the gate electrode 5, the impurity diffusion layer 6, a gate protection film 7, an insulating film 11 between the gate electrodes 5,
Buried electrode 16 between gate electrodes 5, interlayer insulating film 12, bit line contact and bit line 8, and interlayer insulating layer 13
Is formed, a resist pattern 24 for SN contact is formed as shown in FIG.

Next, using the resist pattern 24 as a mask, the upper portion of the interlayer insulating film 12 is isotropically etched by wet etching using a dilute HF solution or the like.
The etching amount at this time is shown in FIGS.
As shown in FIG. 7, the etching is completed before the bottom of the bit line 8 is exposed.

Next, using the resist pattern 24 for SN contact as it is and using the interlayer insulating layer 13 as a mask, as shown in FIGS. 41A and 41B, the interlayer insulating layer 13 is anisotropically etched. The film 12 is patterned to form the capacitor opening 29 and expose the embedded electrode 16.

Next, as shown in FIGS. 42A and 42B, after the SN contact resist pattern 24 is peeled off, a silicon nitride film is deposited on the entire surface, and the side surfaces of the bit lines 8 are etched back. The side wall 14 is formed in a portion of the side surface of the insulating film 33 perpendicular to the semiconductor substrate. This protects the side wall of the bit line 8 that has been exposed again due to the formation of the capacitor opening 28, and facilitates the adhesion of a conductive material to the side surface of the capacitor opening 28 in the formation of the storage electrode 17 described below.

Thereafter, as shown in FIG. 43, the storage electrode 17 is formed in the capacitor opening 29 in the same manner as in the first embodiment, and then, as shown in FIG. After depositing the insulating film 18 on the entire surface, the upper electrode 19 is deposited, and the formation of the capacitor portion 31 is completed.

According to the method of manufacturing a semiconductor memory device according to the present embodiment, a large capacitor opening can be provided, so that a semiconductor memory device including a capacitor having a large storage capacity can be provided. Further, since a part of the side surface of the capacitor opening along the gate electrode is not perpendicular to the semiconductor substrate but has a rounded shape, the storage electrode can be easily formed.

Further, even when the resist pattern 24 for forming the SN contact is misaligned, the storage electrode 17 and the buried electrode 1 connected to the storage electrode 17
There is no possibility that a short circuit will occur between the buried electrode 16 and the buried electrode 16. This makes it possible to manufacture a semiconductor memory device including a capacitor having a large area while securing a contact area with the embedded electrode 16.

Next, a third embodiment of the method for manufacturing a semiconductor memory device according to the present invention will be described with reference to the drawings.

The present embodiment is a method for manufacturing the above-described third embodiment of the semiconductor memory device according to the present invention.

First, in the same manner as in the first embodiment, the element isolation insulating film 2, the gate oxide film 4, the gate electrode 5, the impurity diffusion layer 6, the gate protection film 7, and the insulating film between the gate electrodes 5 are formed. After the formation of the buried electrode 11 and the buried electrode 16, FIG.
(A) and (b), a thin silicon nitride film 41 is deposited, and an oxide film 42 is further deposited on the entire surface.
Next, as shown by the hatched portion in FIG. 44, a resist pattern 46 for the SN contact is formed with a width slightly larger than the interval between the gate electrodes 5, and is tapered at 75 to 85 degrees by using this as a mask. Oxide film 42 by RIE
Is patterned to form a capacitor groove 48 having an inverted trapezoidal cross section whose bottom is shorter than the top, as shown in FIGS. 46 (a) and 46 (b), and a silicon nitride film 41 is formed on the bottom.
To expose.

Next, as shown in FIGS. 47A and 47B, after depositing the BPSG film 12 on the entire surface, the surface is flattened by a chemical mechanical polishing method to bury the capacitor groove 48. Next, as shown in FIG.

Next, as shown in FIG. 48, a resist pattern 47 is formed over the entire region except for the bit line contact region 26 in the form of a broken line ellipse.
As shown in (a) and (b), the oxide film 42 and the silicon nitride film 41 are removed by etching by RIE.
Form bit line contacts.

Next, as shown in FIG. 50, a resist pattern 49 covering the region between the bit lines 8 is formed, and this is used as a mask by the RIE method as shown in FIGS. 51 (a) and 51 (b). , Oxide film 42 and BPSG film 12
Is patterned to form a bit line groove 27, and the silicon nitride film 41 is exposed.

Next, after the resist pattern 49 is peeled off, as shown in FIGS. 52A and 52B, an electrode material 8 ′ such as tungsten (W) is deposited in the bit line groove 27 so as to be embedded. The surface is flattened by a chemical mechanical polishing method.

Next, as shown in FIGS. 53 (a) and (b), the electrode material 8 'is etched back to form the bit line 8, and further, as shown in FIGS. 54 (a) and (b). Then, a nitride film is deposited so as to be buried in the bit line groove 27, and the surface is flattened by a chemical mechanical polishing method to form the interlayer insulating layer 13.

Next, as shown in FIGS. 55A and 55B, the BPSG film 12 is selectively removed from the oxide film 42 by using the interlayer insulating layer 13 as a mask and using a vapor such as HF. This is left as an oxide film 63, and a capacitor opening 48 is formed between the oxide films 63. Further, a silicon nitride film is deposited on the entire surface and etched back to
As shown in (a) and (b), the exposed bit line 8
Is formed on the side surface of the oxide film 63 and the side surface of the oxide film 63. This protects the side wall of the bit line 8 that has been exposed again due to the formation of the capacitor opening 48, and
In the formation of the storage electrode 17 described below, the capacitor opening 4
8 can be easily attached to the side surface of the conductive material.

Next, a conductive material such as ruthenium (Ru) is deposited on the entire surface by a CVD method, and the capacitor opening 48 is buried with a coating type oxide film such as an SOG. The buried material and the conductive material in the flat portion are removed, and then the buried material remaining in the capacitor opening 48 is removed by wet etching with a dilute HF solution or the like, and FIG. 57 (a) and FIG. As shown, the storage electrode 17 extending from the bottom surface of the capacitor opening 48 to the upper side surface of the sidewall 14 on the side surface of the oxide film 63 and further extending to the upper side surface of the sidewall 14 of the bit line 8 is formed.

Thereafter, the capacitor insulating film 18 and the upper electrode 19 are formed in the same manner as in the first embodiment, and the capacitor portion 61 is formed as shown in FIGS. 6A and 6B. Complete the formation.

According to this embodiment, since the capacitor forming opening 48 having a tapered side surface along the gate electrode 5 is formed, the formation of the storage electrode 17 becomes easy, and the resist pattern 46 for forming the SN contact is formed. Even if misalignment occurs, there is no possibility that a short circuit will occur between the storage electrode 17 and the embedded electrode 16 adjacent to the embedded electrode 16 connected to the storage electrode 17. This makes it possible to manufacture a semiconductor memory device including a capacitor having a large area while securing a contact area with the embedded electrode 16.

Next, a fourth embodiment of the method for manufacturing a semiconductor memory device according to the present invention will be described with reference to the drawings.

The present embodiment is a method for manufacturing the above-described fourth embodiment of the semiconductor memory device according to the present invention.

First, similarly to the first embodiment, the element isolation insulating film 2, the gate oxide film 4, the gate electrode 5, the impurity diffusion layer 6, the gate protection film 7, and the insulating film 11 between the gate electrodes are provided. After the formation of the embedded electrode 16, FIG.
As shown in (b), an oxide film 42 is deposited on the entire surface, and a silicon nitride film 51 is further deposited on the oxide film 42.

Next, as shown by the hatched portion in FIG.
A resist pattern 56 for N-contact is formed with a width slightly wider than the interval between the gate electrodes 5, and the nitride film 51 and the oxide film 42 are patterned by RIE using the mask as a mask with a taper of 75 to 85 degrees. , FIG.
As shown in FIGS. 0 (a) and (b), a capacitor groove 68 'having an inverted trapezoidal cross section whose bottom side is shorter than the top side is formed while the oxide film 42 remains at a predetermined thickness, and is formed on the bottom surface. The oxide film 42 is exposed.

Next, as shown in FIGS. 61 (a) and (b), after depositing a BPSG film 52 on the entire surface, the surface is flattened by a chemical mechanical polishing method, and the capacitor groove 68 'is formed.
Embed

Next, after an oxide film 43 is deposited on the entire surface, as shown in FIG. 62, a resist pattern 57 covering the entire region except for the bit line contact region 26 having a broken elliptical shape is formed, and this is used as a mask. Oxide film 43, silicon nitride film 51, and BPSG film 52 below silicon nitride film 51
And the oxide film 42 is removed by etching by RIE,
As shown in FIGS. 63A and 63B, a bit line contact is formed.

Next, as shown in FIG. 64, a resist pattern 58 covering the region between the bit lines is formed, and using this as a mask, RIE method is used to form FIGS. 65 (a) and 65 (b).
As shown in FIG. 3, the oxide film 53, the silicon nitride film 51, the BP
The SG film 52 and the oxide film 42 are patterned to form the bit line groove 27, and the oxide film 42 is exposed. At this time, the etching is performed so that the bottom of the bit line groove 27 is deeper than the bottom of the BPSG film 52.

Next, after the resist pattern 58 is peeled off, as shown in FIGS. 66A and 66B, an electrode material 8 'such as tungsten (W) is deposited in the bit line groove 27 so as to be buried. The surface is flattened by a chemical mechanical polishing method.

Next, as shown in FIGS. 67 (a) and (b), the electrode material 8 'is etched back to form the bit line 8, and further, as shown in FIGS. 68 (a) and (b). Then, a nitride film is deposited so as to be buried in the bit line groove 27 '.
The surface is flattened by a chemical mechanical polishing method to form an interlayer insulating layer 54. At this time, the nitride film 51 previously deposited on the oxide film 42 remains protected from polishing by the oxide film 53 deposited thereon.

Next, as shown in FIGS. 69A and 69B, the BPSG film 52 is selectively removed from the oxide film 42 by using the interlayer insulating layer 54 as a mask and using a vapor such as HF. Then, as shown in FIGS. 70A and 70B, oxide film 42 remaining at the bottom of capacitor groove 68 'is removed by RIE, and capacitor opening 68 is formed between remaining oxide films 83. I do.

Next, a silicon nitride film is deposited on the entire surface, and, as shown in FIGS. 71A and 71B, a sidewall 14 is formed on the exposed side surfaces of the bit lines 8 and the oxide film 83 by etching back. To protect the side wall of the bit line 8 and facilitate the attachment of a conductive material to the side surface of the capacitor opening 68 in the formation of the storage electrode 17 described below.

Next, a conductive material such as ruthenium (Ru) is deposited on the entire surface by a CVD method, and the capacitor opening 68 is buried with a coating type oxide film such as SOG. The buried material and the conductive material in the flat portion are removed, and thereafter, the buried material remaining in the capacitor opening 68 is removed by wet etching using a dilute HF solution or the like, and FIG. 72 (a) and (b). As shown, a storage electrode 17 extending from the bottom surface of the capacitor opening 68 to the upper side of the sidewall 14 on the side of the oxide film 83 and further extending to the upper side of the side wall 14 of the bit line 8 is formed.

Thereafter, the capacitor insulating film 18 and the upper electrode 19 are formed in the same manner as in the first embodiment, and the formation of the capacitor portion 81 is completed as shown in FIG.

According to the present embodiment, since the oxide film 42 is formed immediately below the bit line 8, the parasitic capacitance generated below the bit line 8 is significantly reduced as compared with the above-described first to third embodiments. can do. Thus, in addition to the effects of the above-described embodiment, a semiconductor memory device including a DRAM cell that can operate at higher speed can be provided.

[0120]

As described in detail above, the present invention has the following effects.

That is, according to the semiconductor memory device of the present invention, the storage electrode of the capacitor is formed in the region between the bit lines, and the height of the upper end is set to the height of the upper surface of the third insulating film on the bit line. Since the height is equal to or less than the height, the capacitors can be densely filled within a limited cell area. Thereby, it is possible to provide a DRAM cell having a larger capacitor area without producing a step with the peripheral portion.

When the distance between the side surfaces parallel to the gate electrode of the side surfaces of the capacitor opening is made larger than the bottom portion, the storage electrode and the embedded electrode connected to the storage electrode are adjacent to each other. A semiconductor memory device provided with a DRAM cell having a large-capacity capacitor because it can prevent a short circuit with the embedded electrode, facilitate the adhesion of the electrode material of the storage electrode, and increase the area of the storage electrode. Is provided. When an oxide film is formed between the bit line and the upper surfaces of the first and second insulating films, the parasitic capacitance of the bit line can be significantly reduced. Thus, a semiconductor memory device including a DRAM cell that can operate at higher speed is provided.

According to the method for manufacturing a semiconductor memory device of the present invention, a capacitor opening is formed between bit lines,
Further, since the upper end of the storage electrode does not exceed the upper surface of the bit line, a semiconductor memory device having a high-density and large-capacity capacitor can be manufactured without a step from the peripheral portion. Further, since the capacitor opening is formed in a self-aligned manner using the third insulating film on the bit line as a mask, there is no possibility of misalignment occurring in combination with various patterns. As a result, the processing accuracy of the capacitor is dramatically increased, and a semiconductor memory device that greatly improves the yield can be manufactured. Further, since no lithography step is used, the number of steps is reduced, and the manufacturing cost can be reduced.

When the capacitor opening is formed after the interlayer insulating film is selectively removed to a depth shallower than the bottom of the bit line by isotropic etching, the distance between the side surfaces along the gate electrode is smaller than that of the bottom. Since the capacitor opening is formed so that the upper portion is larger, the storage electrode can be easily formed, and even if the resist pattern for forming the SN contact is misaligned,
There is no risk that a short circuit will occur between the buried electrode adjacent to the buried electrode connected to the storage electrode. Thus, it is possible to manufacture a semiconductor memory device including a capacitor having a large area while securing a contact area with the embedded electrode.

In the case where a step of forming a capacitor trench after depositing an oxide film on the entire surface is provided between the step of forming the first to third electrodes and the step of depositing the interlayer insulating film, Since the oxide film is formed immediately below the bit line, the parasitic capacitance generated below the bit line can be significantly reduced. Thereby, in addition to the above effects, a semiconductor memory device that can operate at higher speed can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a schematic sectional view of the semiconductor memory device shown in FIG. 1; That is, (a) is a cross-sectional view taken along the line AB in FIG. 1, and (b) is a cross-sectional view taken along the line CD in FIG.

FIG. 3 is a schematic plan view showing a second embodiment of the semiconductor memory device according to the present invention.

FIG. 4 is a schematic sectional view of the semiconductor memory device shown in FIG. 3; That is, (a) is a cross-sectional view taken along the line AB in FIG. 3, and (b) is a cross-sectional view taken along the line CD in FIG.

FIG. 5 is a schematic plan view showing a third embodiment of the semiconductor memory device according to the present invention.

FIG. 6 is a schematic sectional view of the semiconductor memory device shown in FIG. 5; That is, (a) is a cross-sectional view taken along the line AB in FIG. 5, and (b) is a cross-sectional view taken along the line CD in FIG.

FIG. 7 is a schematic plan view showing a fourth embodiment of the semiconductor memory device according to the present invention.

8 is a schematic sectional view of the semiconductor memory device shown in FIG. 7; That is, (a) is a cross-sectional view taken along the line AB in FIG. 7, and (b) is a cross-sectional view taken along the line CD in FIG. 7.

FIG. 9 shows a first example of a method for manufacturing a semiconductor memory device according to the present invention.
It is a schematic plan view explaining embodiment of this invention.

FIG. 10 is a schematic cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 9, (b)
FIG. 10 is a cross-sectional view taken along the line CD in FIG. 9.

FIG. 11 is a schematic cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 9, (b)
FIG. 10 is a cross-sectional view taken along the line CD in FIG. 9.

FIG. 12 is a schematic cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 9, (b)
FIG. 10 is a cross-sectional view taken along the line CD in FIG. 9.

FIG. 13 is a schematic plan view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention.

FIG. 14 is a schematic sectional view illustrating a first embodiment of a method of manufacturing a semiconductor memory device according to the present invention. That is,
13A is a cross-sectional view taken along a line AB in FIG.
FIG. 14B is a cross-sectional view taken along the line CD in FIG. 13.

FIG. 15 is a schematic cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
13A is a cross-sectional view taken along a line AB in FIG.
FIG. 14B is a cross-sectional view taken along the line CD in FIG. 13.

FIG. 16 is a schematic plan view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention.

FIG. 17 is a schematic sectional view for explaining the first embodiment of a method for manufacturing a semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along a line AB in FIG.
FIG. 17B is a cross-sectional view taken along the line CD of FIG. 16.

FIG. 18 is a schematic plan view for explaining the first embodiment of the method of manufacturing the semiconductor memory device according to the present invention.

FIG. 19 is a schematic sectional view for explaining the first embodiment of a method for manufacturing a semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along a line AB in FIG. 18,
FIG. 19B is a cross-sectional view taken along the line CD in FIG. 18.

FIG. 20 is a schematic plan view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention.

FIG. 21 is a sectional view illustrating the first embodiment of the method of manufacturing the semiconductor storage device according to the present invention. That is, (a)
Is a cross-sectional view taken along the line AB in FIG. 20, and (b) is
FIG. 21 is a cross-sectional view taken along the line CD of FIG. 20.

FIG. 22 is a schematic sectional view for explaining the first embodiment of the method for manufacturing a semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB of FIG. 20,
FIG. 21B is a cross-sectional view taken along a CD line in FIG. 20.

FIG. 23 is a schematic cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB of FIG. 20,
FIG. 21B is a cross-sectional view taken along a CD line in FIG. 20.

FIG. 24 is a schematic plan view for explaining the first embodiment of the method of manufacturing the semiconductor memory device according to the present invention.

FIG. 25 is a schematic cross-sectional view for explaining the first embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 24,
FIG. 25B is a cross-sectional view taken along a CD line in FIG. 24.

FIG. 26 is a schematic cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 24,
FIG. 25B is a cross-sectional view taken along a CD line in FIG. 24.

FIG. 27 is a schematic cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 24,
FIG. 25B is a cross-sectional view taken along a CD line in FIG. 24.

FIG. 28 is a schematic cross-sectional view for explaining the first embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 24,
FIG. 25B is a cross-sectional view taken along a CD line in FIG. 24.

FIG. 29 is a schematic cross-sectional view for explaining the first embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 24,
FIG. 25B is a cross-sectional view taken along a CD line in FIG. 24.

FIG. 30 is a schematic cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 24,
FIG. 25B is a cross-sectional view taken along a CD line in FIG. 24.

FIG. 31 is a schematic plan view for explaining the first embodiment of the method of manufacturing the semiconductor memory device according to the present invention.

FIG. 32 is a schematic cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 31,
FIG. 32B is a cross-sectional view taken along a CD line in FIG. 31.

FIG. 33 is a schematic cross-sectional view for explaining the first embodiment of a method for manufacturing a semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 31,
FIG. 32B is a cross-sectional view taken along a CD line in FIG. 31.

FIG. 34 is a schematic cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 31,
FIG. 32B is a cross-sectional view taken along a CD line in FIG. 31.

FIG. 35 is a schematic cross-sectional view for explaining the first embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 31,
FIG. 32B is a cross-sectional view taken along a CD line in FIG. 31.

FIG. 36 is a schematic cross-sectional view for explaining the first embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 31,
FIG. 32B is a cross-sectional view taken along a CD line in FIG. 31.

FIG. 37 is a schematic cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 31,
FIG. 32B is a cross-sectional view taken along a CD line in FIG. 31.

FIG. 38 is a schematic plan view for explaining the second embodiment of the method of manufacturing the semiconductor memory device according to the present invention.

FIG. 39 is a cross-sectional view for explaining the second embodiment of the method for manufacturing a semiconductor memory device according to the present invention. That is, (a)
Is a cross-sectional view taken along the line AB in FIG. 38, and FIG.
FIG. 39 is a cross-sectional view taken along a CD line in FIG. 38.

FIG. 40 is a schematic cross-sectional view for explaining the second embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 38,
FIG. 39 (b) is a cross-sectional view along a CD cut surface in FIG. 38.

FIG. 41 is a schematic cross-sectional view for explaining the second embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 38,
FIG. 39 (b) is a cross-sectional view along a CD cut surface in FIG. 38.

FIG. 42 is a schematic cross-sectional view for explaining the second embodiment of the method for manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 38,
FIG. 39 (b) is a cross-sectional view along a CD cut surface in FIG. 38.

FIG. 43 is a schematic sectional view for explaining the second embodiment of the method for manufacturing a semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 38,
FIG. 39 (b) is a cross-sectional view along a CD cut surface in FIG. 38.

FIG. 44 is a schematic plan view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention.

FIG. 45 is a schematic cross-sectional view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB of FIG. 44,
FIG. 45 (b) is a cross-sectional view along a CD cut surface in FIG. 44.

FIG. 46 is a schematic cross-sectional view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB of FIG. 44,
FIG. 45 (b) is a cross-sectional view along a CD cut surface in FIG. 44.

FIG. 47 is a schematic cross-sectional view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB of FIG. 44,
FIG. 45 (b) is a cross-sectional view along a CD cut surface in FIG. 44.

FIG. 48 is a schematic plan view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention.

FIG. 49 is a schematic cross-sectional view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 48,
FIG. 49B is a cross-sectional view taken along a CD line in FIG. 48.

FIG. 50 is a schematic plan view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention.

FIG. 51 is a schematic cross-sectional view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along a line AB in FIG. 50,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 52 is a schematic cross-sectional view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along a line AB in FIG. 50,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 53 is a schematic cross-sectional view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along a line AB in FIG. 50,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 54 is a schematic cross-sectional view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along a line AB in FIG. 50,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 55 is a schematic cross-sectional view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along a line AB in FIG. 50,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 56 is a schematic cross-sectional view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along a line AB in FIG. 50,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 57 is a schematic cross-sectional view for explaining the third embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along a line AB in FIG. 50,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 58 is a schematic plan view for explaining the fourth embodiment of the method of manufacturing the semiconductor memory device according to the present invention.

FIG. 59 is a schematic sectional view for explaining the fourth embodiment of the method for manufacturing a semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 58,
FIG. 58B is a cross-sectional view taken along a CD line in FIG. 58;

FIG. 60 is a schematic sectional view for explaining the fourth embodiment of the method for manufacturing a semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 58,
FIG. 58B is a cross-sectional view taken along a CD line in FIG. 58;

FIG. 61 is a schematic sectional view for explaining the fourth embodiment of the method for manufacturing the semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 58,
FIG. 58B is a cross-sectional view taken along a CD line in FIG. 58;

FIG. 62 is a schematic plan view for explaining the fourth embodiment of the method of manufacturing the semiconductor memory device according to the present invention.

FIG. 63 is a schematic sectional view for explaining the fourth embodiment of the method for manufacturing the semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 62,
FIG. 63 (b) is a cross-sectional view taken along a CD line in FIG. 62.

FIG. 64 is a schematic plan view for explaining the fourth embodiment of the method of manufacturing the semiconductor memory device according to the present invention.

FIG. 65 is a schematic sectional view for explaining the fourth embodiment of the method for manufacturing a semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 64,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 66 is a schematic sectional view for explaining the fourth embodiment of the method for manufacturing the semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 64,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 67 is a schematic sectional view for explaining the fourth embodiment of the method for manufacturing a semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 64,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 68 is a schematic sectional view for explaining the fourth embodiment of the method for manufacturing a semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 64,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 69 is a schematic sectional view for explaining the fourth embodiment of the method of manufacturing the semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 64,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 70 is a schematic sectional view for explaining the fourth embodiment of the method for manufacturing the semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 64,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 71 is a schematic sectional view for explaining the fourth embodiment of the method for manufacturing a semiconductor memory device according to the present invention; That is,
(A) is a cross-sectional view taken along the line AB in FIG. 64,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 72 is a schematic cross-sectional view for explaining the fourth embodiment of the method of manufacturing the semiconductor memory device according to the present invention. That is,
(A) is a cross-sectional view taken along the line AB in FIG. 64,
(B) is sectional drawing in the CD cut surface of FIG.

FIG. 73 is a schematic cross-sectional view showing one example of a semiconductor memory device provided with a conventional stack cell according to the related art.

FIG. 74 is a schematic cross-sectional view of an example of a semiconductor memory device including a COB type cell according to a conventional technique.

FIG. 75 is a schematic cross-sectional view showing another example of a semiconductor memory device including a conventional stack cell according to a conventional technique.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation insulating film 3 element formation region 4, 104 gate oxide film 5 gate electrode 6, 106 impurity diffusion layer 7 gate protective film 8 bit line 8 'conductive material 10, 40, 60, 80 Semiconductor memory device 11 insulating film 12 interlayer insulating film 13, 54 interlayer insulating layer 16 buried electrode 17 storage electrode 18 capacitor insulating film 19 upper electrode 26 bit line contact region 27, 27 ′ bit line groove 28, 29, 68 capacitor opening 30 , 31, 61, 81 Capacitor part 32, 33 Insulating film between capacitors 41 Nitride film 42 Oxide film 48, 68 'Capacitor groove 63, 83 Oxide film between capacitors

Claims (12)

[Claims] A semiconductor substrate having, on a surface thereof, an element formation region where a semiconductor element is to be formed, and an element isolation insulating film formed so as to surround the element formation region; And a first and a second gate insulating film formed in parallel with one side of the element formation region and in parallel with each other, and formed on the first gate insulating film, the upper surface and the side surface. A first gate electrode covered with a first insulating film, and a second gate electrode formed on the second gate insulating film and having an upper surface and side surfaces covered with a second insulating film, A first impurity diffusion layer formed on a surface portion of the semiconductor substrate between the first and second gate electrodes, and separated from the first impurity diffusion layer by a width of the first gate electrode; The second formed on the peripheral surface of the element forming region A pure impurity diffusion layer; a third impurity diffusion layer formed on a surface of a peripheral portion of the element formation region at a distance from the first impurity diffusion layer by a width of the second gate electrode; A first electrode formed between the first and second insulating films and extending over the first impurity diffusion layer and over any one of the element isolation insulating films adjacent thereto; A portion of the first electrode extending on the element isolation insulating film and being connected in a partial area of the lower surface, and above the element isolation insulating film area, A bit line formed on the first and second insulating films so as to be substantially perpendicular to the first and second gate electrodes; a third insulating film formed on the bit lines; Second and third electrodes formed on the second and third impurity diffusion layers, respectively; A fourth insulating film formed above the element forming region and formed with an opening reaching the upper surfaces of the second and third electrodes; and a third insulating film deposited in the opening and having an upper end height of the third insulating film. A semiconductor comprising: a storage electrode having a height equal to or less than the height of the upper surface of the film; a dielectric film formed to cover the storage electrode; and a capacitor having an upper electrode formed to cover the dielectric film. Storage device. 2. The semiconductor memory device according to claim 1, wherein said opening is formed so as to overlap at least a part of a region of said first and second insulating films. 3. The semiconductor memory device according to claim 1, wherein said opening has a bottom surface extending into said second and third electrodes. 4. The semiconductor memory device according to claim 1, wherein said first and second insulating films and said third insulating film are formed of the same material. . 5. The semiconductor memory device according to claim 4, wherein said first and second insulating films and said third insulating film are nitride films. 6. The semiconductor memory device according to claim 1, wherein a cross section of said opening along said bit line has an upper portion wider than a bottom portion. 7. The semiconductor device according to claim 1, wherein an oxide film is formed between said bit line and upper surfaces of said first and second insulating films. Semiconductor storage device. 8. A step of forming an element isolation insulating film surrounding an element formation region where a semiconductor element is to be formed on a surface portion of the semiconductor substrate; and depositing an insulating film on the semiconductor substrate and selectively removing the insulating film. Forming first and second gate insulating films at predetermined positions in the element formation region so as to be parallel to one side of the element formation region and to be parallel to each other; Depositing a conductive material on the substrate, selectively removing it, a first gate electrode on the first gate insulating film,
Forming a second gate electrode on the second gate insulating film; and a first impurity diffusion layer between the gate electrodes on a surface portion of the element formation region of the semiconductor substrate; A second impurity diffusion layer separated by the width of the first gate electrode, and a third impurity diffusion layer separated by the width of the second gate electrode. Forming an insulating film over the entire surface, and then selectively removing the insulating film to cover an upper surface and a side surface of the first gate electrode; and an upper surface and a side surface of the second gate electrode. Forming a second insulating film covering the first impurity diffusion layer; and depositing a conductive material on the entire surface, and then selectively removing the conductive material from the first impurity diffusion layer. A first electrode extending over the second impurity diffusion layer A second electrode, a step of forming a third electrode on the third impurity diffusion layer, a step of depositing an interlayer insulating film over the entire surface, and selectively removing the interlayer insulating film. Depositing a material to form a bit line on the element isolation insulating film, the bit line being substantially orthogonal to the first and second gate electrodes and connected to the first electrode at a lower surface thereof; Forming a third insulating film on a line; and selectively removing the interlayer insulating film on the element forming region to form a capacitor opening on the second and third impurity diffusion layers. Depositing a conductive material in the capacitor opening to form a storage electrode having an upper end whose height is equal to or less than the height of the upper surface of the third insulating film; and a fourth insulating film on the storage electrode. Depositing and forming a dielectric film; and forming a conductive film on the dielectric film. Method of manufacturing a semiconductor memory device comprising forming an upper electrode by depositing charges. 9. The step of forming the bit line, wherein the step of forming the bit line extends substantially orthogonal to the first and second gate electrodes in the interlayer insulating film and extends on the element isolation insulating film of the first electrode. 9. The method of manufacturing a semiconductor device according to claim 8, wherein a bit line groove having a contact opening reaching the portion is formed, and the bit line groove is filled with a conductive material. 10. The step of forming the capacitor opening,
10. The method according to claim 8, wherein after the resist pattern is formed, the interlayer insulating film is selectively removed to a depth shallower than the bottom surface of the bit line by isotropic etching using the resist pattern as a mask. The manufacturing method of the semiconductor memory device described in the above. 11. An oxide film is deposited on the entire surface between the step of forming the first to third electrodes and the step of depositing the interlayer insulating film, and then the first to third impurity diffusion layers are formed. 10. A step of forming a capacitor groove passing through the top and bottom of a cut surface along the bit line shorter than the upper side in parallel with the first and second gate electrodes. 6. The method for manufacturing a semiconductor memory device according to claim 1. 12. The step of forming the capacitor trench includes the step of etching so that the oxide film of a predetermined thickness remains between the first and second gate electrodes. 12. The method according to claim 11, wherein the step of forming the groove is a step of performing etching so that the oxide film having a thickness equal to or less than the predetermined thickness remains.