JPH11250699A - Non-volatile semiconductor memory and high voltage circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory having a high voltage circuit for designating the addresses of a plurality of memory cells in a batch, increasing stress on the memory cell or the like while impressing a high voltage for a long time, and ending high voltage test in a shorter time than a conventional manner. SOLUTION: A high voltage circuit is provided with a charging and discharging circuit for charging and discharging a high voltage, level detecting circuits 30 and 40 for detecting that the charged and discharged voltage reaches a prescribed level, and outputting a level detection signal, charging and discharging control signal generating circuit 50 for generating a charging and discharging control signal for controlling the charging and discharging of the charging and discharging circuit based on the level detection signal, and high voltage switching circuit for switching the high voltage according to the charging and discharging control signal. Thus, a high voltage pulse for erasing the writing of data and a high voltage test pulse can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory capable of writing and erasing data in a memory cell by performing a charge storage operation caused by application of a high voltage, and more particularly, to finding an initial failure thereof. And a circuit for generating a high-voltage test pulse.

[0002]

2. Description of the Related Art Conventionally, there is a nonvolatile semiconductor memory (EEPROM) in which data can be electrically written and erased, in which electrons are injected / emitted using a floating gate of a tunnel oxide film. In addition, there is an MNOS type in which electrons are injected and released using a nitride film using a gate insulating film in which a nitride film and an oxide film are stacked. There is also a flash memory in which an erase gate is wired in common to all the memory transistors of a memory cell and all bits are electrically erased collectively.

To write and erase these memories, it is necessary to apply a high voltage of about 20 V to predetermined terminals. This voltage value is about four times as large as that of a DRAM, but the gate oxide film and the like are considerably thin to cause a tunnel effect, and at the time of data writing / erasing, about half of the dielectric breakdown strength. Is applied to the memory transistor. Therefore, since a high voltage applied portion of the integrated circuit is particularly susceptible to a failure such as a disconnection, it is necessary to screen for an initial failure.

Therefore, conventionally, when a high voltage test is performed on an EEPROM, a data write / erase command is repeatedly executed many times.

[0005]

However, in order to perform a high-voltage test according to the above-described conventional technique, a start command, an operation command, data transmission, etc. are performed every time a data write / erase command is executed. In addition, a high voltage must be applied to a predetermined terminal of the memory cell for a programming time for performing writing and erasing. Therefore, even if the program time is, for example, 5 msec per byte, it takes about 10 msec for one write / erase including the time required for a start command and the like. Although the time was as long as 1000 msec, the time during which the high voltage was applied to the memory cell was only 500 msec, and the time loss was large.

Even if a high voltage pulse having a short duration of 5 msec is applied 100 times and the cumulative application time is 500 msec, the stress applied to the memory cell is small as compared with a long-time high voltage application lasting 500 msec. Therefore, it takes extra time to screen for an initial failure of the nonvolatile semiconductor memory, or a special device is required.

Accordingly, the present invention provides a high voltage test for screening an initial failure of a non-volatile semiconductor memory, etc., in which addresses of a large number of memory cells are collectively specified and a high voltage is applied for a long time. It is an object of the present invention to provide a nonvolatile semiconductor memory that can apply a large stress to a memory cell to reliably find an initial failure or the like and can complete a high-voltage test in a shorter time than in the past.

Further, the present invention provides a high voltage of a nonvolatile semiconductor memory which can supply a high voltage pulse for data writing / erasing and a high voltage pulse for testing having a longer application time with the same circuit. It is an object to provide a circuit.

[0009]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory capable of writing and erasing data in a memory cell by performing a charge accumulation operation caused by application of a high voltage. In a nonvolatile semiconductor memory, a stress test mode in which a high voltage is applied to a predetermined portion of the nonvolatile semiconductor memory during a period longer than a data writing or erasing period can be set.

According to the first aspect of the present invention, after specifying a large number of addresses, a high-voltage pulse that lasts for a desired time in a desired mode such as erasing only or writing after erasing is applied to the nonvolatile semiconductor memory in a predetermined manner. Apply to the location.

According to a second aspect of the present invention, there is provided a high-voltage circuit for a nonvolatile semiconductor memory which can write and erase information in a memory cell by performing a charge storage operation caused by application of a high voltage. A circuit, a high voltage generating circuit for generating a high voltage, a charging / discharging circuit for charging / discharging the high voltage, and detecting that a voltage charged / discharged to the charging / discharging circuit has reached a predetermined level. A level detection circuit that outputs a level detection signal, and based on the level detection signal,
A charge / discharge control signal generating circuit for generating a charge / discharge control signal for controlling a charge / discharge operation of the charge / discharge circuit; and a high voltage switching circuit for switching the high voltage by the charge / discharge control signal, The voltage switching circuit generates a high voltage pulse for writing and erasing data and generates a high voltage pulse for a high voltage test of writing and / or erasing that lasts longer than the data writing or erasing period. I am trying to do it.

According to the present invention, not only a high voltage pulse for writing / erasing data but also a high voltage pulse for a high voltage test having a long duration is generated by utilizing charge / discharge of a capacitor.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 is a configuration diagram of a nonvolatile semiconductor memory according to an embodiment of the present invention. The nonvolatile semiconductor memory of the present invention includes a data decoder 80 for decoding data to be written to a memory cell, a level shifter 90 that operates at a high voltage during writing and erasing and operates at a low voltage during reading, and a memory including a selector transistor and a memory transistor. A memory cell array 100 in which cells are two-dimensionally arranged, and a column decoder 110 and a row decoder 120 for specifying an address in the memory cell array 100
A memory transistor gate voltage applying unit 130 for applying a high voltage to a gate of a memory transistor in the memory cell array 100; and a memory transistor source voltage applying unit for supplying a voltage to a source of a memory transistor in the memory cell array 100 140, a high-voltage circuit 1, and a control circuit 2 for controlling each block.

The high voltage circuit 1 includes a high voltage generation circuit 10 for generating a constant high voltage Vppr, and a high voltage Vppr.
To switch the high voltage pulse Vp for writing and erasing.
a timer circuit 20 for generating pi, and a timer circuit 20
And a low-level detection circuit 30 that receives a charge / discharge waveform TC, detects a predetermined low level of the charge / discharge voltage, and outputs a low-level detection signal, and also receives a charge / discharge waveform TC and receives a predetermined charge / discharge voltage. A high level detection circuit 40 for detecting a high level and outputting a high level detection signal; a high level detection signal TCHTB, a post-erase write signal REWR, and an external signal EXT1 (write signal W) input from the control circuit 2
An inverted signal WEB of E, an inverted signal CSB of the chip select signal CS, an erase test mode signal ERSTRN,
And outputs a charge / discharge control signal CH and its inverted signal CHB.
And a low level detection signal TCS, a charge / discharge control signal CH, and an external signal EXT2 (an inverted signal ERB of the erase signal ER) input from the control circuit 2 to instruct that writing be performed after erasing. A post-erase write signal generation circuit 60 for outputting a write signal REWRI, and a post-erase write signal REW
An external signal EXT3 (erase signal ER, write test mode signal WRSTRN,
And a latch circuit 70 that receives the inverted signal CSB of the chip select signal CS and outputs a post-erase write control signal REWR.

Here, a program signal WE for instructing data erasing and writing, an erasing signal ER for instructing data erasing, a chip select signal CS for activating the nonvolatile semiconductor memory, and a writing test are instructed. These five types of signals, a write test mode signal WRSTRN to be executed and an erase test mode signal ERSTRN instructing an erase test, are input from outside the nonvolatile semiconductor memory or input as test mode command signals from the internal control circuit 2. Then, based on the input, each is generated by a logic circuit (not shown).

Next, each circuit constituting the high voltage circuit 1 will be described. First, the high voltage generation circuit 10 of FIG. 1 is a circuit that supplies the high voltage Vppr to the timer circuit 20. This high-voltage generation circuit 10 is built in the nonvolatile semiconductor memory of the present invention, like all the other circuits.
A well-known booster circuit or the like in which the drain and the gate of the FET are connected in series from 20 to 30 stages can be used. In addition,
The high voltage generation circuit 10 is configured to operate when the programming signal WE is high.

Further, a circuit constituting the high voltage circuit 1 will be described with reference to FIGS. FIG. 2 is a circuit diagram of the timer circuit 20 having a charge / discharge circuit and a high-voltage switching circuit. The charging / discharging circuit uses the time control signal TC
And a circuit for outputting transistors T1, T2, T3, T3
4, a capacitor C and a high voltage switch A. On the other hand, the high voltage switching circuit
A circuit that outputs ppi, transistors T5, T6, T
7, T8, a high-voltage switch A, and a high-voltage switch B. Therefore, the high voltage switch A is a component common to the charge / discharge circuit and the high voltage switching circuit.

Referring to FIG. 2, the operation of the charging / discharging circuit will be described. First, the capacitor C in the figure is not charged,
The time control signal TC has a substantially ground potential. When the charge / discharge control signal CH is high, the high voltage switch A is turned on, and the high voltage Vppr is applied to the gate of the high voltage transistor T4. Therefore, the high voltage transistor T4 is turned on, and charging of the capacitor C is started. The charging time constant at this time is the product of the capacitance value of the capacitor C and the resistance value of the transistor T3 in the ON state. Here, the reference voltage V2 input to the gate of the transistor T3 determines the resistance value of the transistor T3. When the charge / discharge control signal CH is high, the inverted signal CHB is low, so that the transistor T5 is OFF, and the transistor T5 does not participate in charging at all.

On the other hand, when the charge / discharge control signal CH is low, the high voltage switch A is turned off. At this time, since the inverted signal CHB of the charge / discharge signal CH is high, the transistor T5 is turned on and the gate of the transistor T4 is turned on. Is substantially at the ground potential, but the threshold value of the high breakdown voltage transistor T4 is 0.5 (V).
Therefore, the transistor T4 is also turned off, and the high voltage Vppr is not supplied to the capacitor. at the same time,
By the reference voltage V1 input to the gate of the transistor T1, the transistor T1 is turned on with a predetermined resistance value, and the transistor T2 input to the gate with the inverted signal CHB of the charge / discharge signal CH is turned on. The capacitor C is discharged through the transistors T1 and T2. As described above, the charge / discharge circuit outputs the charge / discharge signal CH
And the inverted signal CHB switches between high and low, the voltage of the time control signal TC rises and falls.

Next, the operation of the high voltage switching circuit will be described with reference to FIG. The input of this high-voltage switching circuit also includes a charge / discharge control signal CH and its inverted signal CH.
B. First, when the charge / discharge control signal CH is high, when the high voltage switch A is turned on, the high voltage transistor T6 is turned on, and the high voltage Vppi slightly lower than the high voltage Vppr is output. At this time, the transistor T8
Is turned on to set the gate of the transistor T7 to substantially the ground potential, thereby prohibiting the transistor T7 from being turned on.

Conversely, when the charge / discharge control signal CH is low,
The high voltage switch B is turned on by the input of the inverted signal CHB.
N turns on the high breakdown voltage transistor T7, and similarly outputs the high voltage Vppi. At this time, the transistor T5
Is turned on to set the gate of the transistor T6 to a substantially ground potential, thereby prohibiting the transistor T6 from being turned on.

Thus, even if the charge / discharge control signal CH is high or its inverted signal is high, the high voltage Vp
pi is output. As described later, the charge / discharge control signal C
Since H changes later than the inverted signal CHB, when the charge / discharge control signal CH changes from high to low, both the charge / discharge control signal CH and its inverted signal CHB become high, so that the high voltage Vppi is output. Subsequently, when the charge / discharge control signal CH changes from low to high, both become low, so that the high voltage Vppi is temporarily cut off. As a result, the high voltage pulse Vppi is generated with one cycle of one charge and one cycle of the subsequent discharge. In FIG. 2,
The transistors T1, T6, and T7 are MOS transistors having a threshold value of approximately 0 V, and the transistors T2, T3,
T5 and T8 are NMOS transistors having a threshold value of 0.8V.

Next, returning to FIG.
Will be described. The low level detection circuit 30 detects a certain low level of the time control signal TC and outputs a low level detection signal TCS. As such a low-level detection circuit 30, for example, a comparator or the like can be used. Alternatively, when the low level is reached, a short pal may be output from the monostable multivibrator.

Similarly, the high level detection circuit 40 detects a constant high level of the time control signal TC and outputs a high level detection signal TCHTB. As such a high level detection circuit 40, for example, a comparator or the like can be used. Alternatively, when the low level is reached, a short pal may be output from the monostable multivibrator.

Next, the charge / discharge control signal generating circuit 50 will be described with reference to FIG. FIG. 3 is a logic circuit diagram of the charge / discharge control signal generation circuit 50, and the high level detection signal T
CHTB, post-erase write control signal REWR, and external signal EX
T1 (consisting of an inverted signal WEB of the program signal WE, an inverted signal CSB of the chip select signal CS, and an erase test mode signal ERSTRN) is input, and a charge / discharge control signal CH and its inverted signal CHB are output. Circuit.

In FIG. 3, the high level detection signal TC
The HTB, the post-erase write control signal REWR, and the inverted signal WEB of the program signal WE are input to the OR circuit 301. Also, an inverted signal CSB of the chip select signal CS,
The erase test mode signal ERSTRN is input to the NAND circuit 303. Further, the output of the OR circuit 301 and N
The output of the AND circuit 303 is input to the NOR circuit 304. Also, the erased write signal REWR is output from the inverter 302.
, And the input of the NOR circuit 305 together with the output of the NAND circuit 303. Further, the output of the NOR circuit 304 is
While the output of the NOR circuit 305 and the inverted signal WEB of the program signal WE are supplied to the NOR circuit 307.
Is input. Here, the NOR circuit 306 and the NOR circuit 307 constitute a flip-flop. And
One output of the flip-flop is connected to inverters 308 and 3
09, 310, 311 as a charge / discharge control signal CH, and the other output is connected to inverters 313, 314.
Is output as an inverted signal CHB of the charge / discharge control signal CH. Here, the capacitor 312 is an integration capacitor that delays the rise of the pulse, and the capacitor 312
15 sets CH high at power-on and CHB
In order to make the low.

The charge / discharge control signal CH and its inverted signal CHB are used for controlling the timer circuit 20 and for controlling the post-erase write signal generation circuit 60. Therefore, the charge / discharge control signal CH is input to the post-erase write signal generation circuit 60 and the timer circuit 20, and its inverted signal CHB is input to the timer circuit 20.

Next, the generation 60 of the erase / write signal will be described with reference to FIG. FIG. 4 is a logic circuit diagram of the post-erase write signal generation circuit 60, which receives a charge / discharge control signal CH, a low level detection signal TCS, and an external signal EXT2 (an inverted signal ERB of the erase signal ER), and This is a circuit that outputs a write signal REWRI.

In FIG. 4, a charge / discharge control signal CH, a low level detection signal TCS, and an external signal EXT2 (an inverted signal ERB of the erase signal ER) are input to a NOR circuit 401. The output of the NOR circuit 401 is divided into two, one of which is input to the NOR circuit 409 via the inverter 406, and the other is connected to the inverters 402, 403, 4
The signal is input to the NOR circuit 409 via the lines 04 and 405.
The inputs are integrated by the capacitors 407 and 408 to delay the rise of the pulse. NOR circuit 409
Is used to instruct that a write operation be performed following erasure.

Then, the post-erase write signal REWRI output from the NOR circuit 409 is input to the latch circuit 70. Next, the latch circuit 70 will be described with reference to FIG. FIG. 5 is a logic circuit diagram of the latch circuit 70, which comprises a post-erase write signal REWRI, an external signal EXT3 (erase signal ER, a write test mode signal WRSTRN, and an inverted signal CSB of the chip select signal CS). ) And outputs a post-erase write control signal REWR and its inverted signal REWRB.

In FIG. 5, write test mode signal W
RSTRN and inverted signal CS of chip select signal CS
B is input to the NAND circuit 501. Further, the erase signal ER and the output of the NAND circuit 501 are
2 is input. Furthermore, the write signals REWRI and N
The output of the OR circuit 502 is input to the flip-flop 503. Then, the output of the flip-flop 503 becomes the post-erase write signal REWR and its inverted signal REWRB via the inverters 504 and 505, respectively. The post-erase write control signal REWR is
The pulse width of the WRI is latched by the external signal EXT3. Note that the capacitor 506 is provided so that its node becomes low when the power is turned on.

Then, the post-erase write control signal REWR is input to the charge / discharge control signal generating circuit 50, and the timer circuit 2
It is fed back to 0. By using the high voltage circuit 1 having the above-described circuits, a high voltage pulse Vppi for writing and erasing can be easily generated. Therefore, generation of the high voltage pulse Vppi will be described with reference to FIGS.

FIG. 6 is a time chart of the high voltage circuit during a normal write operation. In the time chart of FIG. 6, first, the inverted signal CSB of the chip selector signal falls, and the write test mode signal WRSTRN and the erase test mode signal ERSTRN remain high.

Next, the erase signal ER rises, and accordingly, the inverted signal WEB of the program signal WE falls, the high voltage generating circuit 19 starts outputting the high voltage Vppr, and the time control signal Tc rises. The high-level detection circuit 40 and the low-level detection circuit 30 detect a predetermined high level and low level of the time control signal Tc, and generate a high-level detection signal TCHTB and a low-level detection signal TCH. In the charge / discharge control signal generation circuit 50, the charge / discharge control signal CH falls with the high level detection signal TCHTB. In addition, in response to the low level detection signal TCS, the erased write signal generation circuit 60 causes the erased write signal REWRI.
Falls, and the charge / discharge control signal CH is raised by the post-erase write signal REWR via the latch circuit 70. When the inverted signal WEB of the program signal WE rises, the charge / discharge control signal CH rises.

The charge / discharge control signal CH is fed back to the charge / discharge circuit in the timer circuit 20, and becomes a signal for switching between charge and discharge. Further, the high voltage pulse Vppi for erasing is temporarily turned off by the erase control signal REWR after writing from the latch circuit 70, and the capacitor of the timer circuit 20 is started to be charged by the low level detection signal TCS from the low level detection circuit 30. High voltage pulse Vp for writing
pi.

As is apparent from FIG. 6, the charge / discharge signal CH
Is high, the capacitor C of the charge / discharge circuit is charged, and when it is low, it is discharged. When the charge / discharge control signal CH is high, the high-voltage switch A is turned on. When the charge-discharge control signal CH is low, the high-voltage switch A is turned on after the high-voltage switch B is turned on.
Is turned off, the high voltage Vppi continues to be output, and when the charge / discharge control signal CH changes from low to high, the high voltage Vppi is output.
Since pi is turned off, as described above, one cycle of one charge and one subsequent discharge is defined as a high voltage pulse Vppi.
Is generated.

Next, FIG. 7 shows a mode for implementing a stress mode in which a pulse lasting a continuous period longer than the data erasing is applied. In the case of FIG. 7, in the charge / discharge control signal generation circuit 50, the erase test mode signal ERST
RN is set to low in advance, and the high-voltage erase pulse is started at the fall of the inverted signal WEB of the program signal WE. Therefore, even when the high level and the detection signal TCHTB fall, the charge / discharge control signal CH does not fall and the high voltage is maintained. Then, after a lapse of a desired time, the inversion signal CSB of the test mode signal CS rises and the charge / discharge control signal CH is switched to low, so that the timer circuit of the timer circuit 20 starts discharging. Then, when the low level detection signal TCS falls, the charge / discharge control signal CH is switched to high at the rise of the erased write control signal REWR from the charge / discharge control signal generation circuit 50, and the inverted signal WEB of the write signal WE Switches the charge / discharge control signal CH to high at the rise of the write signal W
The high voltage pulse Vppi for erasing is terminated at the fall of the inverted signal WEB of E.

Next, FIG. 8 shows an embodiment for implementing a stress mode in which a pulse that is applied for a continuous period longer than data writing is applied. The method of raising the high-voltage pulse Vppi for erasing is the same as that of FIG. 6, but by keeping the write test mode signal WRSTRN low, even if the high-level detection signal falls, the write signal after erasing is written. REWR does not fall, and the charge / discharge control signal CH
Does not fall, the high voltage Vppi is maintained. Thereafter, the inverted signal CSB of the chip select signal CS rises after a desired time has elapsed, and the erased write signal RE
The latch of WR and the charge / discharge control signal CH is released, the timer circuit starts discharging, and the inverted signal W of the program signal WE.
EB is started to end the high voltage write pulse.

In FIGS. 6 to 8, the high-voltage switch A and the high-voltage switch B are triggered by the program signal WE and correspond to the charge / discharge control signal CH and its inverted signal CHB in order to respond to the test mode start command. Switching is done.

The operation of the high voltage circuit 1 has been described above. Next, the operation of the nonvolatile semiconductor memory of the present invention will be described below. Since the nonvolatile semiconductor memory of the present invention performs a basic operation of writing, erasing, and reading data and an additional operation of performing a high-voltage test including a stress mode, first, FIG. The basic operation such as data writing will be briefly described with reference to FIG.
The additional operation of performing the high voltage test will be described with reference to FIG.

First, FIG.
FIG. 7 is an explanatory diagram of writing, erasing, and reading for the. In this figure, attention is focused on only one designated address.
In FIG. 1, a nonvolatile semiconductor memory is used for data writing / writing.
At the time of normal erasing / reading, for example, a 12-bit serial address signal is input to the column decoder 110 and the row decoder 120, and simultaneously 8 bits or 16 bits are input.
Bit data is input to a data decoder, and data is written / erased / read from / to a desired address of the memory cell array 100 using the level shifter 90, the memory transistor gate voltage applying unit 130, and the memory transistor source voltage applying unit 140. It is supposed to do. That is, to write and erase data in the nonvolatile semiconductor memory, the level shifter 90 is switched to the high voltage operation, and the high voltage pulse Vppi generated by the high voltage circuit 1 is applied to a predetermined terminal of the memory cell array 100. To read data stored in the nonvolatile memory of the present invention, the level shifter 90 is switched to a low voltage operation, and a drain voltage of the memory at a desired address is read by a sense circuit (not shown).

First, the case where writing is performed by emitting electrons from the floating gate of the memory transistor 160 will be described. In the case of writing, the column decoder 1 connected to the gate of the column transistor 150
The voltage Vx supplied from the ten address lines, the voltage Vy supplied from the address line of the row decoder 120 connected to the gate of the row select transistor 151, and the voltage Vd supplied from the bit line of the data decoder 80 are approximately two.
0 V is applied, and the voltage Vg supplied from the memory transistor gate voltage application unit 130 connected to the gate of the memory transistor 160 is set to 0 V. At this time, the two select transistors 150 and 151 are turned on, and a high voltage of about 20 V of Vd is applied to the drain of the memory transistor 160, so that electrons are emitted from the floating gate. The source voltage Vs supplied from the memory transistor source voltage applying unit 140 to the source of the memory transistor 160 is a value of 5 V or more and about 20 V or less, for example,
7V. This suppresses the source / drain current of the memory transistor 160, and the floating gate 16
This is to prevent the potential of the electron emission path 1 from lowering. Here, the source voltage Vs of 7V is equal to the high voltage Vp of about 20V.
Pi can be easily supplied from the memory transistor source voltage applying unit 140 by, for example, dividing voltage by resistance division.

Next, a case where erasing is performed by injecting electrons into the floating gate 161 of the memory transistor 160 will be described. In the case of erasing, a high voltage of about 20 V is applied to Vx, Vy, and Vg, and Vd and Vs are set to 0 V.
Vg is the memory transistor gate voltage application unit 13
Supplied from 0. At this time, the two select transistors 150 and 151 are turned ON, and the memory transistor 1
60 becomes 0V, and electrons are injected into the floating gate. In the case of a flash memory in which an erase gate is wired in common to all the memory transistors of the memory cell array 100 and all bits are electrically erased collectively, a high voltage may be applied to the erase gate.

Next, a case where data is read from the memory will be described. In the case of reading, the level shifter 90 is switched to the low voltage operation, 5 V is applied to Vx and Vy,
1.5V is applied to g and Vd, and Vs is set to 0V. At this time, if electrons have been injected into the floating gate 161, the electrons will extinguish the channel of the memory transistor 160, which is of the prescription type.
Is 1.5 V, the memory transistor 160 is not turned on. Therefore, the drain of the memory transistor is approximately V
The value of d is maintained. On the other hand, if electrons are emitted from the floating gate, since a channel is formed in the depletion-type memory transistor 160, even if Vg is zero, the memory transistor 160
Turns ON. Therefore, the drain of the memory transistor has, for example, a substantially ground potential. As described above, data can be read by changing the potential of the drain of the memory transistor depending on the presence or absence of charge in the floating gate 161.

The basic operation such as data writing of the nonvolatile semiconductor memory has been described above with reference to FIG. 9, and then, the basic operation such as data writing with reference to FIG. , And a method of instructing an additional operation for performing a high voltage test.

Incidentally, in order to screen an initial failure of the memory, it is preferable to designate a large number of addresses at once to shorten the test time. For example, the (column, row) of the address of the memory cell 100 is (all selection, all selection), (even selection, all selection), (odd selection,
It is preferable that a desired designation such as "select one line" can be made. Alternatively, it is also preferable to provide a memory transistor non-selection mode for performing a high-voltage high-voltage test by excluding only the memory transistor 160. This is because the test modes are diversified to facilitate analysis of the failure location. Furthermore, the high voltage application is terminated by erasing,
It is convenient if it is possible to specify the generation mode of the high-voltage pulse, such as whether to end with writing.

Therefore, in the present invention, not only the basic operations of data writing / erasing / reading but also various test modes can be designated by including an address code in a part of the operation mode command signal. It is.

FIG. 10 is an explanatory diagram of an example of a method of specifying an operation mode. FIG. 10 shows an example of a method of designating an operation mode in the case of serial input data, in which an operation mode command signal composed of a start bit, an operation code, a data bit, and an address code for designating the operation mode is shown. I have.

First, two start bits are a start signal, and the start is commanded by "01". Next, the operation code 2 bits and the next address A1
When the combination of 1, A10 is "0001", it indicates that the mode is the test mode. When the operation code is "01", data writing is instructed, and when the operation code is "10", data reading is instructed.

Next, the address bits A9 and A8 are set to "1".
When it is "0", it indicates that the mode is the stress mode of the present invention (# 7 to # 10). When the value is other than "10", the description is omitted because the stress mode is not the stress mode of the present invention.

Next, the address bit A7 is set to "0" when the row decoder 120 selects all the rows of the memory cell array 100, and set to "1" when it is not selected. Next, the address bit A6 is set to "0" when performing a long-time high-voltage test during the erasing period, and is set to "1" when performing the high-voltage test during the writing period.

As described above, of the address codes, A11
To A6 are used to instruct how to generate the high-voltage pulse. An external signal to the high-voltage circuit 1 is generated by the control circuit 2 from these bits indicating the generation mode of the high-voltage pulse, and is used as an external signal to be input to the high-voltage circuit 1.

These external signals correspond to the program signal W
E, an erase signal ER instructing data erasure, a chip select signal CS instructing start of a test mode, a write test mode signal WRSTRN instructing a write test, an erase test mode signal ERSTRN instructing an erase test,
There are five types.

As described above, these external signals are
It is input to each circuit of the high voltage circuit 1 of FIG. The charge / discharge control signal generation circuit 50 receives the inverted signal WEB of the program signal WE, the inverted signal CSB of the test mode signal CS, and the erase test mode signal ERSTRN as EXT1. Further, an inverted signal ERB of the erase signal ER is input to the post-erase write signal generation circuit 60 as EXT2.
Further, the erase signal ER, the write test mode signal WRSTRN, and the inverted signal CSB of the chip select signal CS are input to the latch circuit 70 as EXT3. That is, the high-voltage circuit 1 of FIG. 1 is a circuit that outputs a high-voltage pulse Vppi while controlling charging and discharging with the above five types of external signals and the like.

In the normal mode for writing data, not in the test mode, for example, the control circuit 2 to which the data write command signal has been input receives a write test mode signal WRSTRN for instructing a write test, and With the erase test mode signal ERSTRN instructing the erase test kept high, the erase test mode signal ERSTRN is input to the charge / discharge control signal generation circuit 50 of the high voltage circuit 1 to generate a high voltage pulse.

As described in detail above, according to the present invention, in addition to writing, erasing, and reading data, a large number of addresses are designated for screening of initial failures, and then various tests are performed. It is configured so that a high voltage / high voltage test can be performed in the mode. That is, when a test mode command signal is input to the nonvolatile semiconductor memory of the present invention, a high voltage pulse corresponding to the high voltage test mode is automatically generated and applied to the memory cell. I have.

[0057]

As described above, according to the present invention, in a high voltage test for screening for an initial failure of a nonvolatile semiconductor memory, a high voltage is applied to a memory cell or the like while a high voltage is applied for a long time. By increasing the stress, it is possible to reliably screen for initial failures,
In addition, the high voltage test can be completed in a shorter time than before.

In particular, according to the first aspect of the present invention, only erasing is performed.
In a desired mode such as writing after erasing, a stress mode in which a high voltage is applied to a predetermined portion of the nonvolatile semiconductor memory can be set in a continuous period longer than a data writing or erasing period. It is possible to screen the initial failure of the memory easily and quickly in a mode not available.

According to the second aspect of the present invention, a high voltage pulse for data writing / erasing and a high voltage pulse for testing having a longer application time can be supplied by the same circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a nonvolatile semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a timer circuit having a charge / discharge circuit and a high-voltage switching circuit.

FIG. 3 is a logic circuit diagram of a charge / discharge control signal generation circuit.

FIG. 4 is a logic circuit diagram of a post-erase write signal generation circuit.

FIG. 5 is a logic circuit diagram of a latch circuit.

FIG. 6 is a time chart of the high voltage circuit during a normal write operation.

FIG. 7 is a time chart of a stress mode in which a high voltage pulse is applied for a longer continuous time in an erasing period.

FIG. 8 is a time chart of a stress mode in which a high voltage pulse is applied for a longer continuous time in a writing period.

FIG. 9 is an explanatory diagram of writing / erasing / reading for a memory transistor.

FIG. 10 is an explanatory diagram of an example of a method for specifying an operation mode.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 high voltage generation circuit 20 timer circuit having charge / discharge circuit and high voltage switching circuit 30 low level detection circuit 40 high level detection circuit 50 charge / discharge control signal generation circuit 60 post-erase write signal generation circuit 70 latch circuit 80 data decoder 90 Level shifter 100 Memory cell array 110 Column decoder 120 Row decoder 130 Memory transistor gate voltage application unit 140 Memory transistor source voltage application unit

Claims (2)

[Claims] 1. A non-volatile semiconductor memory capable of writing and erasing data in a memory cell by performing a charge accumulation operation caused by application of a high voltage, wherein said non-volatile semiconductor memory is longer than a data writing or erasing period. A nonvolatile semiconductor memory characterized in that a stress test mode for applying a high voltage to a predetermined portion of the nonvolatile semiconductor memory can be set. 2. A high-voltage circuit provided in a nonvolatile semiconductor memory capable of writing and erasing information in a memory cell by performing a charge accumulation operation caused by application of a high voltage, wherein the high-voltage generation circuit generates a high voltage. A charge / discharge circuit that charges / discharges the high voltage; a level detection circuit that detects that a voltage charged / discharged in the charge / discharge circuit has reached a predetermined level and outputs a level detection signal; A charge / discharge control signal generation circuit that generates a charge / discharge control signal for controlling the charge / discharge of the charge / discharge circuit, and a high voltage switching circuit that switches the high voltage with the charge / discharge control signal. Generating a high-voltage pulse for writing and erasing data and generating a high-voltage pulse for a high-voltage test that is longer than a data writing or erasing period. High-voltage circuit of the nonvolatile semiconductor memory which is characterized by being composed urchin.