JPH11249969A - Address conversion circuit and address conversion system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an address conversion circuit and an address conversion system which shorten the access time for a memory while securing the overall capacity of the memory even when a defective cell exists in the memory. SOLUTION: The address conversion circuit is provided with an address conversion part 101 which converts a logical address to a first physical address corresponding to a normal address and outputs the first physical address, a defective address storage circuit 4 where a defective address corresponding to a defective memory cell in a memory 2 is stored, and a redundancy discrimination circuit 1 which substitutes the first physical address with a second physical address corresponding to a redundant address to send it to the memory 2 in response to coincidence between the first physical address and the defective address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation circuit and an address translation system, and more particularly to an address translation circuit and an address translation system for a memory provided with a redundant memory for guaranteeing the total memory capacity of defective memory cells. Regarding the conversion system.

[0002]

2. Description of the Related Art FIG. 6 shows a configuration of a conventional address translation system. The address translation system includes the CPU 3 and the CP
A memory control circuit 110 connected to U3 and a plurality of memories 102 connected to the memory control circuit 110 are provided.

[0003] The memory is sold so that a predetermined total capacity (for example, 40 megabytes) can be used. The total amount of memory must be guaranteed. That is,
Even when a defective memory cell is present in a part of the memory, the memory must be able to use a predetermined total capacity.

[0006] The memory 102 is provided with a normal memory (not shown) having a capacity corresponding to the total capacity of the memory 102.

In the conventional address conversion system, when a defective memory cell (not shown) exists in the normal memory of the memory 102, the total capacity of the memory 102 is guaranteed.
Inside the memory 102, in addition to the normal memory, a redundant memory (not shown) and a redundant memory for replacing a physical address corresponding to the defective memory cell with a physical address corresponding to the redundant memory when an access is made to the defective memory cell. A judgment circuit 103 is provided.

FIG. 7 shows an internal configuration of the memory 102 and the memory control circuit 110 in the conventional address translation system. Note that only one memory 102 is shown for the sake of simplicity. The memory control circuit 110 includes an address conversion unit 101. The redundancy judgment circuit 103 provided in the memory 102 includes a comparison circuit 102A and a defective address storage unit 102B.

The address conversion unit 101 converts a logical address from the CPU 3 into a physical address corresponding to the memory 102. The comparison circuit 102A includes an address conversion unit 101
Address received from the server and the defective address storage unit 1
02B is compared with the defective address stored in 02B. When the comparison result between the physical address from the address conversion unit 101 and the defective address matches, it means that the access destination is a defective memory cell, and the redundancy judgment circuit 103 determines the physical address from the address conversion unit 101. The memory cell in the redundant memory is accessed by replacing it with a redundant address corresponding to the memory cell in the redundant memory. If the comparison result between the physical address from the address conversion unit 101 and the defective address does not match, it means that the access destination is a normal memory cell. Is accessed to the memory cell in the normal memory corresponding to.

[0008]

However, by providing the redundancy judgment circuit 103 inside the memory 102 and performing redundancy judgment inside the memory 102, the total capacity of the memory 102 is guaranteed when a defective memory exists. In the conventional address conversion system, there is a problem that the access speed to the memory is reduced. This will be specifically described below.

FIG. 8A shows a first processing method in a memory access operation of a conventional address translation system. FIG. 8B shows a second processing method in the memory access operation of the conventional address translation system.

The first processing method will be described with reference to FIG. In the first processing method, first, the address conversion unit 1
01 is the defective address storage unit 102B
The redundancy determining circuit 103 provided in the memory 102 determines whether or not the address matches the defective address stored in the memory 102. If the address matches, a process P1 (time T1) of replacing the address with the redundant address is executed. After the process P1 is executed, a process P2 (time T2) of accessing based on the physical address (normal address) from the address conversion unit 101 or the redundant address obtained by replacing the physical address from the address conversion unit 101 is executed.

The second processing method will be described with reference to FIG. In the second processing method, of the circuit relating to the access path corresponding to the normal address and the circuit relating to the access path corresponding to the redundant address, processing P3 (time T3) for accessing halfway in the circuit relating to the access path corresponding to the normal address. Is executed, and the process P1 (time T1) is executed in parallel with the process P3.

When the redundancy judgment circuit 103 provided in the memory 102 judges that the physical address from the address conversion unit 101 matches the defective address, the redundancy judgment circuit provided in the memory 102 after the processing P1. 1
03, a process P4 (time T2) for accessing based on the redundant address replaced from the physical address is executed. Redundancy determination circuit 103 provided in memory 102
If it is determined that the physical address from the address conversion unit 101 does not match the defective address,
02 does not need to be replaced with a redundant address by the redundancy determination circuit 103 provided in the standby time T5 (= T1
After -T3), the remaining access process P6 of process P3 (time T6 = T2-T3) is executed based on the normal address.

In either of the first processing method and the second processing method, the time from when the memory 102 receives the physical address to when it outputs the data of the access destination and ends the access, That is, in the access time, the redundancy judgment circuit 103 provided in the memory 102 judges whether or not the physical address from the address conversion unit 101 matches the defective address. Time T1 is required.

In order to complete the guarantee of the total capacity of the memory 102 on the memory side from the request of the system side, a redundancy judgment circuit 103 is provided in the memory 102 and the redundancy judgment circuit 10
3 is a processing time in the memory 102 and a processing of determining whether or not a physical address matches a defective address, and a processing of replacing the physical address with a redundant address when the processing is performed, requires a time T1 for determination and replacement. This is disadvantageous in that the access time of the memory 102 in the address translation system is reduced.

The present invention has been made in view of such problems of the prior art.

An object of the present invention is to provide an address conversion circuit and an address conversion system which can shorten the access time to a memory while guaranteeing the total capacity of the memory even when a defective memory cell exists in the memory. To provide.

[0017]

An address translation circuit according to the present invention is an address translation circuit which translates a logical address into a physical address and sends the physical address to a memory. A redundant address for guaranteeing the capacity of the memory by replacing a defective address corresponding to a defective memory cell in the memory array, and converting the logical address to a first physical address in the normal memory array. An address conversion unit that outputs the first physical address; a defective address storage unit that stores the defective address corresponding to the defective memory cell of the memory; and a comparison result between the first physical address and the defective address. In response to the match, the first physical address is replaced with a second physical address corresponding to the redundant address, and And a redundancy determination circuit to be transmitted to the memory, thereby the objective described above being achieved.

The redundancy judging circuit compares the first physical address output from the address conversion unit with a defective address stored in the defective address storage unit, and outputs a comparison result; A replacement unit that replaces the first physical address corresponding to a normal address with a second physical address corresponding to the redundant address and outputs the first physical address and the second physical address based on the comparison result And a selector for selecting one of them and sending it to the memory.

A mode signal output unit for sending a mode signal to the memory based on the comparison result may be further provided.

An address translation system according to the present invention includes a CPU that outputs a logical address, an address translation circuit that receives the logical address, translates the physical address into a physical address, and sends the physical address, and receives the physical address and corresponds to the physical address. And a memory for accessing the memory cell,
The memory has a normal address and a redundant address for guaranteeing a capacity of the memory by replacing a defective address corresponding to a defective memory cell in a normal memory array, and the address conversion circuit includes: Converting a logical address into a first physical address in the memory array;
An address conversion unit that outputs a physical address; a defective address storage unit that stores the defective address corresponding to the defective memory cell of the memory; and a comparison result between the first physical address and the defective address that matches. A redundancy determining circuit that responds and replaces the first physical address with a second physical address corresponding to the redundant address and sends it to the memory, thereby achieving the above object.

The redundancy judging circuit compares the first physical address output from the address conversion unit with a defective address stored in the defective address storage unit, and outputs a comparison result; A replacement unit that replaces the first physical address corresponding to a normal address with a second physical address corresponding to the redundant address and outputs the replacement result, and compares the first physical address and the second physical address based on the comparison result. And a selector for selecting one of them and sending it to the memory.

[0022] The address conversion circuit may further include a mode signal output section for sending a mode signal to the memory based on the comparison result.

[0023] The memory may include a plurality of memory chips.

An address conversion circuit according to the present invention replaces a physical address corresponding to a defective memory cell with a physical address corresponding to a redundant memory and sends it to the memory when the defective memory cell is accessed.

Therefore, during the time from when the memory receives the physical address to when the access is completed, that is, during the access time, the redundancy judgment circuit provided in the memory determines whether the physical address matches the defective address. No time is required for the determination and replacement of the physical address with the redundant address.

As a result, even when a defective memory cell exists in the memory, the access time to the memory can be reduced while guaranteeing the total capacity of the memory.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the address translation system according to the present invention will be described below.

FIG. 1 shows a configuration of an address translation system according to an embodiment of the present invention. The address conversion system includes a CPU 3 and a memory control circuit 1 connected to the CPU 3.
0 and a plurality of memories 2 connected to the memory control circuit 10. The memory control circuit 10 replaces a physical address corresponding to a defective memory cell with a physical address corresponding to a redundant memory (not shown) when an access is made to a defective memory cell (not shown).
It has.

FIG. 2 shows an internal configuration of the memory control circuit 10 and the memory 2 according to the embodiment of the present invention. FIG.
Shows an address translation algorithm in the address translation system according to the embodiment of the present invention.

Referring to FIG. 2, memory control circuit 10 includes:
It includes a redundancy judgment circuit 1, an address conversion unit 101 ', a defective address storage circuit 4, and a control circuit 12. The redundancy judgment circuit 1 includes a comparison circuit 1B, a replacement circuit 1C, and a selector 1D.
And The memory 2 is a normal memory array 2
A, redundant memory array 2B, defective address storage unit 2
C. The CPU 3, the memory control circuit 10, and the memory 2 are all connected to a clock line CLK.

The normal memory array 2A has normal memory cells having a capacity corresponding to the total capacity specification of the memory 2. The redundant memory array 2B has a redundant memory cell for replacing a defective memory cell in order to guarantee the total capacity of the memory 2 when a defective memory cell exists in the normal memory array 2A.

When receiving the logical address from the CPU 3, the address converter 101 'converts the logical address received from the CPU 3 into a physical address corresponding to the normal memory array 2A and outputs the physical address. This address conversion is executed based on the address conversion algorithm shown in FIG.

The comparison circuit 1B includes an address conversion unit 101 '
Is compared with the defective address stored in the defective address storage circuit 4 to output a comparison result. The replacement circuit 1C replaces the physical address output from the address conversion unit 101 'with a physical address representing a redundant address corresponding to the redundant memory array 2B.

When the comparison result output from the comparison circuit 1B matches, the selector 1D selects a physical address representing the redundant address corresponding to the redundant memory array 2B output from the replacement circuit 1C and sends the selected physical address to the memory 2. Send out. When the comparison result output from the comparison circuit 1B does not match, the selector 1D selects a physical address corresponding to the normal memory array 2A output from the address conversion unit 101 'and sends it to the memory 2.

The memory 2 accesses the normal memory array 2A or the redundant memory array 2B based on the physical address sent from the selector 1D.

FIG. 4 is a timing chart of memory access in the address translation system according to the present embodiment.

The CPU 3 and the memory control circuit 10 operate in synchronization with the clock on the clock line CLK. Recently, the memory 2 also performs an access operation in synchronization with the clock of the clock line CLK. In such a clock-synchronous address translation system, it is important how much time margin the access result data is determined with respect to the rising edge of the clock. This time margin is shown as a setup time in FIG.
Within the margin of the setup time in the processing in each of the CPU 3, the memory control circuit 10, and the memory 2,
The margin of the setup time in the processing in the memory 2 is the smallest. Therefore, it is important how to lengthen the setup time in the processing in the memory 2.

In the conventional address conversion system, as shown in the conventional example 1 of FIG. 4, it is determined whether or not a physical address matches a defective address, and if the physical address is a defective address, it is replaced with a redundant address. Process P1 (time T
1) is allocated to the memory 2 side.

In a process P2 (time T2) for accessing based on a normal address or a redundant address, a process of fetching an address sent from the address conversion unit 101, a subsequent predecode process, and selection of a word line or a column line Operation and the like are performed.

In addition to the process P2, the process in the memory 2
If the process P1 for determining whether the physical address matches the defective address and replacing it with the redundant address is further assigned, the setup time TSU2 becomes shorter as shown in FIG. That is, in the processing in the memory 2, there is no time margin for the access processing.

For this reason, as shown in the conventional example 2 of FIG.
In order to take a sufficient setup time TSU3, the end of the access processing must be further delayed by one clock. As a result, the processing to be executed with latency = 4 (conventional example 1) becomes the processing requiring latency = 5 (conventional example 2). As described above, in order to complete the guarantee of the memory capacity on the memory 2 side, if the process P1 is assigned to the process in the memory 2, the access speed of the memory 2 is reduced.

On the other hand, when considering the entire address translation system, it is found that the processing in the memory control circuit 10 has sufficient time for access processing. In the process in the memory control circuit 10, one clock time TAD is allocated. There is sufficient time to execute the process P1 of comparing the physical address with the defective address using the time TAD of one clock and replacing it with the redundant address in the process of the memory control circuit 10.

In the address translation system according to the present invention,
The process P1 is assigned to a part of the time TAD having a sufficient time. The time T1 in the first processing method and the second processing method described with reference to FIGS. 8A and 8B is allocated within the time TAD that is the processing time in the memory control circuit 10. As a result, sufficient time for the access processing is given to the memory 2, and the total access time is reduced as compared with the conventional system.

FIG. 5 shows an internal configuration of the memory control circuit 10A and the memory 2 in a modification of the address translation system according to the embodiment of the present invention. The same elements as those of the address translation system described in FIG. 2 are denoted by the same reference numerals. A detailed description of these will be omitted.

The difference from the address conversion system described with reference to FIG. 2 is that the mode signal output circuit 1E is
It is a point provided in. The memory control circuit 10A includes:
It includes a redundancy judgment circuit 11, an address conversion unit 101 ', a defective address storage circuit 4, and a control circuit 12. The redundancy judgment circuit 11 includes a comparison circuit 1B, a replacement circuit 1C, a selector 1D, and a mode signal output circuit 1E.

The mode signal output circuit 1E includes a comparison circuit 1B
If the comparison result output from the memory 2 matches, the mode signal indicating access to the redundant memory array 2B is sent to the memory 2
Send to The mode signal output circuit 1E includes a comparison circuit 1B
If the comparison result output from the memory array 2 does not match, a mode signal indicating access to the normal memory array 2A is sent to the memory 2.

The normal memory array 2A and the redundant memory array 2B have different memory configurations, and therefore have different address designation methods. Generally, since the redundant memory array 2B has a small capacity, for example, in the case of 16 redundant memory cells, a method of designating 4 bits as an address bit length is adopted. The address bit length when specifying the address of the redundant memory array 2B is smaller than the address bit length when specifying the address of the normal memory array 2A. As described above, the address designation method differs between the normal memory array 2A and the redundant memory array 2B.

When the memory 2 receives the mode signal indicating access to the redundant memory array 2B, the memory 2 uses the method of designating the address of the redundant memory array 2B.
Access B. When the memory 2 receives the mode signal indicating access to the normal memory array 2A, the memory 2 accesses the normal memory array 2A by a method of specifying an address of the normal memory array 2A. The memory 2 uses the mode signal as information for identifying whether the physical address sent from the selector 1D is an address for accessing the normal memory array 2A or an address for accessing the redundant memory array.

In order to store the defective address in the defective address storage circuit 4, the defective address of the memory is stored in a defective address storage section 2C which is a nonvolatile memory means provided in the memory 2, and FIG. The redundancy determination circuit 1 may read out the defective address stored in the defective address storage section 2C and store the defective address in the defective address storage circuit 4 as indicated by an arrow AR shown in FIG. The storage in the defective address storage unit 2C may be performed when the memory 2 is shipped, and the defective address may be read from the defective address storage unit 2C after the shipped memory 2 is mounted on the address conversion system.

The defect corresponding to the defective address includes not only a point bit defect but also a number of consecutive addresses defects such as a word line defect and a bit line defect. As for the defective addresses corresponding to the consecutive defective addresses, the individual defective addresses are not stored in the defective address storage circuit 4 or the defective address storage unit 2C, but the upper several bits are common to the row address and the column address. It is also possible to use a method of storing all addresses collectively as defective addresses.

When a test circuit for testing whether an address in the memory 2 is a defective address and storing the address determined as a defective address in the defective address storage circuit 4 is provided in the redundancy judgment circuit 1, the memory 2 It is possible to relieve not only the defective addresses stored at the time of shipment but also newly generated defective addresses after the shipped memory 2 is mounted on the address translation system.

As described above, according to the address translation system according to the present embodiment, even if a defective memory cell exists in the memory, the access time to the memory can be reduced while guaranteeing the total capacity of the memory. can do.

According to the address conversion system according to the present embodiment, only one redundancy judgment circuit is provided in the memory control circuit. Therefore, a conventional address conversion system in which a redundancy judgment circuit is provided in each of a plurality of memories. Compared with the conversion system, the area and the cost of the memory 2 can be reduced.

According to the address translation system according to the present embodiment, before the access request is sent to the memory 2, the redundancy judgment circuit judges whether the physical address related to the access request is a normal address or a redundant address. I do. The memory 2 does not need to operate both circuits related to the access path corresponding to the normal address and circuits related to the access path corresponding to the redundant address. When the physical address related to the access request is a normal address, the memory 2 only needs to operate the circuit related to the access path corresponding to the normal address. When the physical address related to the access request is the redundant address, the memory 2 Needs to operate only the circuit related to the access path corresponding to the redundant address. As a result, power consumption is reduced as compared with the conventional address translation system in which both the circuit relating to the access path corresponding to the normal address and the circuit relating to the access path corresponding to the redundant address need to operate. Can be.

Although the synchronous type in which the memory 2 operates in synchronization with the clock has been described as an example, the present invention is not limited to this. The memory 2 may be of an asynchronous type.

Although an example has been described in which the redundancy judgment circuit is provided in the memory control circuit, the present invention is not limited to this. The redundancy judgment circuit may be a circuit different from the memory control circuit.

[0057]

As described above, the address conversion circuit according to the present invention replaces the physical address corresponding to the defective memory cell with the physical address corresponding to the redundant memory when the defective memory cell is accessed. Send out.

Therefore, in the memory, no time is required for determining whether the physical address matches the defective address and replacing the physical address with the redundant address.

As a result, even when a defective memory cell exists in the memory, the access time to the memory can be reduced while guaranteeing the total capacity of the memory.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an address translation system according to an embodiment.

FIG. 2 is a configuration diagram of the inside of a memory control circuit 10 and a memory 2 according to the embodiment.

FIG. 3 is an address translation algorithm in the address translation system according to the embodiment;

FIG. 4 is a timing chart of memory access in the address translation system according to the embodiment.

FIG. 5 is a diagram showing the internal configuration of a memory control circuit 10A and a memory 2 in a modification of the address translation system according to the embodiment.

FIG. 6 is a configuration diagram of a conventional address translation system.

FIG. 7 shows a memory 1 in a conventional address translation system.
2 is a diagram showing the internal configuration of a memory control circuit 110 and a memory control circuit 110. FIG.

FIG. 8A is a diagram illustrating a first processing method in a memory access operation of a conventional address translation system. (B) is an explanatory diagram of a second processing method in a memory access operation of the conventional address translation system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 11 Redundancy determination circuit 1B Comparison circuit 1C Replacement circuit 1D selector 2 Memory 2A Normal memory array 2B Redundant memory array 2C Defective address storage unit 3 CPU 4 Defective address storage circuit 10 Memory control circuit

Claims (7)

[Claims] 1. An address conversion circuit for converting a logical address into a physical address and sending the physical address to a memory, wherein the memory stores a normal address and a defective address corresponding to a defective memory cell in a normal memory array. An address conversion unit for converting the logical address into a first physical address in the normal memory array and outputting the first physical address; A defective address storage unit for storing the defective address corresponding to the defective memory cell of the memory; and a first physical address in response to a result of comparison between the first physical address and the defective address being matched. With a second physical address corresponding to the redundant address and sending it to the memory. Less conversion circuit. 2. The redundancy judging circuit compares a first physical address output from the address conversion unit with a defective address stored in the defective address storage unit, and outputs a comparison result. A replacement unit that replaces the first physical address corresponding to the normal address with a second physical address corresponding to the redundant address and outputs the first physical address; and the first physical address and the second physical address based on the comparison result. 2. The address conversion circuit according to claim 1, further comprising: a selector for selecting any one of the following and sending the selected data to the memory. 3. The address conversion circuit according to claim 1, wherein the redundancy judgment circuit includes a mode signal output unit that sends a mode signal to the memory based on the comparison result. 4. A CPU that outputs a logical address, an address conversion circuit that receives the logical address, converts the logical address into a physical address, and transmits the physical address; and a memory that receives the physical address and accesses a memory cell corresponding to the physical address. Wherein the memory has a normal address and a redundant address for guaranteeing the capacity of the memory by substituting a defective address corresponding to a defective memory cell in a normal memory array; An address conversion unit that converts the logical address into a first physical address in the normal memory array and outputs the first physical address; and a defective address that stores the defective address corresponding to the defective memory cell of the memory. A storage unit, wherein the comparison result between the first physical address and the defective address matches A redundancy judging circuit which responds and replaces the first physical address with a second physical address corresponding to the redundant address and sends it to the memory. 5. A comparing unit that compares the first physical address output from the address conversion unit with a defective address stored in the defective address storage unit and outputs a comparison result. A replacement unit that replaces the first physical address corresponding to the normal address with a second physical address corresponding to the redundant address and outputs the first physical address; and the first physical address and the second physical address based on the comparison result. 5. The address translation system according to claim 4, further comprising: a selector that selects any one of the following and sends the selected data to the memory. 6. The address translation system according to claim 4, wherein said address translation circuit further comprises a mode signal output unit for transmitting a mode signal to said memory based on said comparison result. 7. The address translation system according to claim 4, wherein said memory includes a plurality of memory chips.