JPH1124990A - Processing module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change an access cycle and to load a memory different in the access cycle. SOLUTION: A processing module 10 is connected to the processing module of another system through a common bus 15. When a read/write control part 13 writes data into a memory 11 in accordance with a write request from a processing part 12, the same writing is executed into the memory in the processing module of the other system through the common bus 15. Thus, the memory 11 always holds the same content as a memory at the processing module of the other system. An access cycle storage part 16 to which the access cycle of the memory 11 is set and an access cycle control part 17 generating the access cycle of the memory, which is set in the access cycle storage part 16, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

(Table of Contents) Technical Field to which the Invention pertains Prior Art (FIGS. 8 and 9) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 and 2) Embodiment of the Invention (FIG. 3) 7) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing module which is connected to a processing module of another system via a shared bus, and is shared when a read / write control section writes data to a memory in response to a write request from a processing section. The present invention relates to a processing module configured to perform the same writing to a memory in a processing module of another system via a bus, so that the memory always holds the same contents as the memory in the processing module of another system.

[0003]

2. Description of the Related Art Generally, a host computer (CPU)
And a plurality of DASDs (Direct Access Storage Devices) between the CPU and each DAS.
A system for controlling access to D is provided. This system is generally composed of two systems of processing modules having the same configuration (hereinafter, may be simply referred to as modules).

[0004] The memories provided for these processing modules are connected via a shared bus, and the MPU (MicroProcessing) of each processing module is connected to these memories.
or Unit). In this system, when writing to each memory, the same contents are also written to other memories, and these memories always hold the same data.

A conventional configuration of a processing module used in such a system will be described with reference to FIG. FIG. 8 is a block diagram showing the configuration of a system having a conventional processing module. As shown in FIG.
The two processing modules 50-1 and 50-2 have the same configuration, and are connected to each other via an inter-module shared bus 60.

The processing module (# 0) 50-1 includes a memory 51-1, an MPU 52-1 and a read / write control unit 5.
3-1, comprises an arbitration unit 54-1 and an OR gate 55-1. Similarly, the processing module (# 1) 50-2
Are a memory 51-2, an MPU 52-2, a read / write control unit 53-2, an arbitration unit 54-2, and an OR gate 55.
-2.

The memories 51-1 and 51-2 store various data, and these memories always hold the same data. MPU (processing unit) 5
2-1 and 52-2 are stored in the memories 51-1 and 51, respectively.
The processing is performed based on the data held in -2. The read / write control units 53-1 and 53-2 control access to the memories 51-1 and 51-2 according to read / write requests from the MPUs 52-1 and 52-2, respectively.

When arbitration units 54-1 and 54-2 compete for read / write requests (bus requests) from read / write control units 53-1 and 53-2, respectively,
This is for arbitrating the right to use the shared bus 60 between the processing modules 50-2 and 50-1 of the other system, and a specific operation example thereof will be described later with reference to FIG. O
The R gates 55-1 and 55-2 take the logical sum of the write control signals from the read / write control units 53-1 and 53-2 and output them to the memories 51-1 and 51-2, respectively. , These OR gates 55-1, 55-2
With this operation, write access is simultaneously performed to the memories 51-1 and 51-2 of both modules 50-1 and 50-2.

With the above configuration, the read / write control units 53-1 and 53-2 control the MPUs 52-1 and 52-5, respectively.
2-2, the read / write control signal is sent to the memories 51-1 and 51-2 and the arbitration unit 5
4-1 and 54-2. If these read / write control signals do not conflict, the read access is executed independently in each of the modules 50-1 and 50-2. The write control signal from the read / write control unit 53-1 or 53-2 is supplied to the OR gate 55-1.
Or, through 55-2, both modules 50-1, 5
Since the data is input to both the memories 51-1 and 51-2, the write access is made to both the modules 50-1 and 50-2.
0-2 are performed simultaneously.

Therefore, when writing (data updating) to the memory of one module, the same writing (data updating) is performed to the memory of another system module via the shared bus 60. Done at the same time. Thus, the memory 51-1 (51-2) in one system always holds the same contents as the memory 51-2 (51-1) in the processing module 50-2 (50-1) of the other system. become.

On the other hand, when the read / write control units 53-1 and 53-2 read / write control signals are simultaneously output (when the read / write control signals conflict),
The arbitration unit 54- in each of the modules 50-1 and 50-2
After the arbitration operation (arbitration operation) is performed by the read / write control units 54-1 and 54-2, the read / write control units 53-1 and 53-2 receive the bus use permission from the arbitration unit 54-1 or 54-2, so that the memory is read. -Access is performed in order.

In the arbitration operation by the arbitration units 54-1 and 54-2, conventionally, one of the modules [for example, the module (# 0) is always used regardless of read / write.
50-1] is prioritized. When read access conflicts, each memory 51-
1 and 51-2 have the same data and do not collide with each other on the shared bus 60 during read access.
0-2 are executed simultaneously. When the write access conflicts, the arbitration units 54-1 and 54-2 preferentially perform the write access in the module (# 0) 50-1.

The case where a write request occurs in the module 50-1 and a read request occurs in the module 50-2 will be described with reference to FIG. Module 5
When a write request is generated at 0-1 and a read request is generated at the module 50-2, as shown in FIG. 9, the read / write control units 53-1 and 53-2 change the arbitration units 54-1 and 54.
The bus request signals # 0 and # 1 for -2 simultaneously rise (timing t1).

Each of the arbitration units 54-1 and 54-2 performs an arbitration operation in a contention cycle, and in order to give priority to write access in the module (# 0) 50-1, first, the module (# 0) 50- 1, the arbitration unit 54-1 outputs a bus use permission to the read / write control unit 53-1 and the bus start signal # 0 rises (timing t2).

When the write cycle in the module (# 0) 50-1 ends, the module (# 1) 5
Since the bus request signal # 1 from the read / write control unit 53-2 at 0-2 is still rising, in response to this, the module (# 1) 50-2 executes the module 50-2 to execute read access. (# 1) 5
The arbitration unit 54-2 at 0-2 outputs a bus use permission to the read / write control unit 53-2, and the bus start signal # 1 rises (timing t3).

[0016]

By the way, the memory 51
Since the access cycles of -1 and 51-2 vary depending on the memory element, the read / write control unit 53-
Reference numerals 1 and 53-2 are configured to output a read / write control signal in a predetermined access cycle.

However, depending on the device, when an access cycle is long (access speed is slow) but a cheaper memory is desired, or when the current memory is replaced with a memory having a short access cycle (fast access speed). However, since the access cycle cannot be changed in the conventional processing module shown in FIG.
It can only handle cycles of memory.

Conventionally, in arbitration operation, memory access of one module is always prioritized irrespective of read / write. However, when a system as shown in FIG. Is rarely performed at the same frequency, and the frequency of either operation is generally higher. Therefore, if an arbitration operation that gives priority to only one module's memory access is performed irrespective of the frequency, the processing speed is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and enables a change in an access cycle so that a memory having a different access cycle can be mounted. It is an object of the present invention to provide a processing module that achieves high processing speed by improving the performance of the processing module, thereby improving the performance of the apparatus.

[0020]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, a processing module 10 of the present invention includes a shared bus 15 for a processing module of another system (not shown). A processing unit 12 that performs processing based on data held in the memory 11, and a read / write control unit that controls access to the memory 11 in response to a read / write request from the processing unit 12. It has a write control unit 13 and an arbitration unit 14 for arbitrating the right to use the shared bus 15 between the processing modules of the other system and a read / write control unit 13 in response to a write request from the processing unit 12. When writing to the memory 11 is performed, the same writing is performed to the memory in the processing module of another system via the shared bus 15 so that the memory 11 is always Process is configured to retain the memory of the same contents of the module.

In the present invention, the access cycle storage unit 1 in which the access cycle of the memory 11 is set is set.
6 and an access cycle control unit 17 for generating an access cycle of the memory 11 set in the access cycle storage unit 16 (claim 1). When the access cycle of the memory 11 is different from that of the memory of the other processing module, the register for setting the memory access cycle of the other processing module for the write access operation is:
It may be provided as an access cycle storage unit 16 (claim 2).

When the access cycle differs between the memory 11 and the memory of the processing module of another system, the access of the memory 11 for the read access operation is performed.
A register in which a cycle is set may be provided as the access cycle storage unit 16 (claim 3). With the above-described configuration, the access cycle according to the set value can be generated by the access cycle control unit 17 only by changing the set value of the access cycle in the access cycle storage unit 16.
The cycle can be changed (claim 1).

At this time, when the access cycle differs between the memory 11 and the memory in the processing module of the other system, if the access cycle of the other system is slower than the own system,
The access cycle of the other system can be set in a register as an access cycle for a write access operation (claim 2), and if the access cycle of the other system is slower than the own system, An access cycle can be set in a register as an access cycle for a read access operation.

FIG. 2 is a block diagram showing the principle of the present invention. As shown in FIG. 2, the processing module 10A of the present invention basically has the same memory 11 and processing function as the processing module 10 shown in FIG. Although it is configured to include a unit 12, a read / write control unit 13, and an arbitration unit 14, in the present invention,
A read / write priority register 18 in which an access type to be preferentially executed is set in advance is provided, and a bus use request accompanying a write request from the read / write control unit 13 and a read / write control unit in a processing module of another system is provided. When the bus request and the bus request accompanying the read request occur at the same time, the access of the type set in the read / write priority register 18 is preferentially executed (claim 4).

For the access of the type set in the read / write priority register 18, the arbitration unit 14 unconditionally and preferentially issues a bus use permission to the read / write control unit 13. A circuit may be provided (claim 5), and the arbitration unit 14 may be provided with a priority invalidation register in which information for invalidating the operation of the bus use permission issuing circuit is set (claim 6).

When the access by the other processing module is preferentially executed, the time until the execution of the access by the other processing module is completed after the contention cycle at the time of the normal arbitration operation of the arbitration unit 14 is completed. And a guaranteed cycle control unit that generates the guaranteed cycle calculated by the guaranteed cycle calculating unit after the completion of the contention cycle.

Further, a comparison circuit for comparing the value of the read / write priority register with the value of the read / write priority register in the processing module of another system and notifying an error to the firmware when the values are different may be provided. (Claim 8). With the above-described configuration, if a frequently accessed type (read / write) is set in the read / write priority register in advance, a bus use request accompanying a write request and a bus use request accompanying a read request occur simultaneously. The access of the type having a high frequency is preferentially executed (claim 4).

At this time, the bus use permission issuing circuit in the arbitration unit 14 unconditionally preferentially issues the bus use permission to the read / write control unit 13 for the access of the setting type, thereby enabling read / write. An access signal to the memory 11 is immediately output from the control unit 13,
The access is executed preferentially (claim 5). However, if the invalidation information is set in the priority invalidation register, the operation of the bus use permission issuing circuit is invalidated, and the arbitration unit 14 performs a normal arbitration operation (claim 6).

When the access by the processing module of the other system is executed with priority, the guaranteed cycle is calculated by the guaranteed cycle calculation unit of the own system, and the guaranteed cycle is calculated by the guaranteed cycle control unit of the own system after the completion of the contention cycle. Since it is generated, the access by the processing module of the own system can be executed after waiting for the total time of the contention cycle and the guarantee cycle (claim 7).

Further, when the value of the read / write priority register of the own system is different from the value of the read / write priority register of the processing module of the other system, the difference is detected by the comparison circuit and the firmware is notified. Since the error notification is performed, it is possible to prevent a malfunction due to such a difference in the values (claim 8).

[0031]

Embodiments of the present invention will be described below with reference to the drawings. The system of the present embodiment is also provided, for example, between a host computer (CPU) and a plurality of DASDs, and controls access from the CPU to each DASD.

FIG. 3 is a block diagram showing the configuration of a system having a processing module according to an embodiment of the present invention. As shown in FIG.
Memory systems 21-1 and 21 provided with two processing modules (hereinafter, sometimes simply referred to as modules) 20-1 and 20-2 having the same configuration and provided in these modules 20-1 and 20-2, respectively. -2 is shared bus 26
Connected through. In the following, the reference numerals to which "-1" is added indicate the elements constituting the processing module (# 0) 20-1, and the reference numbers to which "-2" is added indicate the processing module (# 1) 20-. 2 shall be shown.

The processing module (# 0) 20-1 includes a memory 21-1, an MPU 22-1, and a read / write control unit 2.
3-1, arbitration unit 24-1, OR gate 25-1, access cycle register for write 31-1, access cycle register for read 32-1, switching unit (MU)
X) 33-1, access cycle control counter 34-
1, read / write priority register 35-1, wait cycle operation unit 36-1, wait cycle control counter 37-
1, comparison circuit 38-1 and error register 39-1
It is composed of

Similarly, the processing module (# 1) 20-2
Are a memory 21-2, an MPU 22-2, a read / write control unit 23-2, an arbitration unit 24-2, and an OR gate 25-
2, write access cycle register 31-2,
Read access cycle register 32-2, switching unit (MUX) 33-2, access cycle control counter 34-2, read / write priority register 35-2, wait cycle operation unit 36-2, wait cycle control counter 37-2, comparison circuit 38-2 and error register 3
9-2.

The memories 21-1 and 21-2 store various data, and these memories always hold the same data. MPU (processing unit) 2
2-1 and 22-2 are memories 21-1 and 21 respectively.
The processing is performed based on the data held in -2. The read / write control units 23-1 and 23-2 control access to the memories 21-1 and 21-2 in response to read / write requests from the MPUs 22-1 and 22-2, respectively. The embodiment is configured as described later with reference to FIG.

When the read / write requests (bus requests) from the read / write control units 23-1 and 23-2 compete with each other, the arbitration units 24-1 and 24-2 normally use the other systems. The right to use the shared bus 60 is arbitrated between the processing modules 20-2 and 20-1. In this embodiment, the right is used as described later with reference to FIG.

The OR gates 25-1 and 25-2 take the logical sum of the write control signals from the read / write control units 23-1 and 23-2, respectively, and store them in the memories 21-1 and 21-2, respectively.
1-2, and these OR gates 25
Due to the operations of -1, 25-2, the memory 21 of both modules 20-1 and 20-2 is used for write access.
1, 21-2.

The write access cycle registers (cycle register storage units) 31-1 and 31-2 and the read access cycle registers (cycle registers)
In each of the register storage units 32-1 and 32-2, an access cycle of the memories 21-1 and 21-2 is set. Here, if the memories 21-1 and 21-2 are the same, the same access cycle value is set in the write access cycle registers 31-1 and 31-2. If the access cycle is different between the access cycle and 21-2, the value of the later access cycle is set for both. As a result, even if different memories are installed between the own system and the other system, the memory 2
Write operations for 1-1 and 21-2 can be performed simultaneously.

The read access cycle registers 32-1 and 32-2 have memories 21-1 and 21-
2 is set to the same value, the same access cycle value (same as the value set in the registers 31-1 and 31-2) is set. If the cycle is different, the memory 21-1,
The value of the access cycle of 21-2 is set. Thus, when the access cycle of the own system is faster than that of the other system, it is possible to perform a read operation at a high speed using the access cycle.

The switching unit (MUX) 33-1 selects and outputs the value of the write access cycle register 31-1 during a write operation, and outputs the value of the read access cycle register 32-1 during a read operation. The switching unit (MUX) 33-2 selects and outputs the value of the write access cycle register 31-2 during the write operation. On the other hand, a switching operation is performed so as to select and output the value of the read access cycle register 32-2 during the read operation.

The access cycle control counters (access cycle control units) 34-1 and 34-2 are set with the values of the access cycles output from the switching units 33-1 and 33-2 as initial values, respectively. , Is counted down in synchronization with the clock to generate an access cycle for the memories 21-1 and 21-2. The operation will be described later with reference to FIG.

Read / write priority registers 35-1, 3
In 5-2, an access type (read / write) to be preferentially executed is set in advance. If the access status is normal, these registers 35-1 and 35-2 have the same value. The access type is set. Specifically, “1” is set when writing is prioritized, and “0” is set when reading is prioritized.

Then, each processing module 2 of the present embodiment
0-1 and 20-2 are bus use requests (bus use request / write) accompanying write requests from the read / write control units 23-1 and 23-2 and bus use requests (bus use request / read) accompanying read requests. ) Occur simultaneously, the access of the type set in the read / write priority registers 35-1 and 35-2 is preferentially executed.

In order to realize such a function, the processing module 20-1 (20-2) of the present embodiment includes a waiting cycle operation unit 36-1 (36-2) and a waiting cycle control counter as described later. 37-1 (37-2) and a read / write control unit 23-1
(23-2) and the arbitration unit 24-1 (24-2) are shown in FIG.
It is configured as shown in FIG. In the following description,
The configuration of the processing module (# 0) 20-1 will be described, but the configuration of the processing module (# 1) 20-2 is the same.

When the access by the processing module 20-2 of the other system is preferentially executed, the waiting cycle operation unit 36-1 performs the processing of the other system after the completion of the contention cycle in the normal arbitration operation of the arbitration unit 24-1. The time until the execution of the access by the module 20-2 is completed is calculated as a wait cycle (guaranteed cycle). For example, as shown in FIG.
8 and an arithmetic circuit 29.

The comparison circuit 27 compares the write access cycle set in the register 31-1 with the write access cycle set in the register 31-1.
The value is compared with the read access cycle set to 1, and if it is equal, the value is output as it is, while if not equal, the larger value is output. The contention cycle register 28 is used to preset a contention cycle during the normal arbitration operation of the arbitration unit 24-1.

The arithmetic circuit 29 calculates the value A from the comparison circuit 27.
And the value B set in the contention cycle register 28, the waiting cycle (guaranteed cycle) C is calculated as C = A
This is calculated and output as −B. After the contention cycle of the arbitration unit 24-1, the wait cycle control counter 37-1 is set with the value of the wait cycle calculated by the wait cycle calculation unit 36-1 as an initial value, and synchronizes the value with the clock. Then, a wait cycle is generated by counting down.
Note that the above-described waiting cycle calculation unit 36-1 (36-
2) and the wait cycle control counter 37-1 (37-
The operation 2) will be described later with reference to FIG.

Next, the read / write control section 23-1 (23-2) and the arbitration section 24-1 (2
The detailed configuration of 4-2) will be described with reference to FIG. The read / write control unit 23-1 includes a bus use request generation circuit 40, an OR gate 41, an AND gate 42,
It comprises a latch circuit 43 and an underflow detection circuit 44.

The bus use request generation circuit 40 has been provided conventionally, and either a “bus use request / read” signal or a “bus use request / write” signal in response to a read / write request from the MPU 22-1. One to launch. The OR gate 41 outputs the logical sum of the “bus use request / read” signal from the bus use request generation circuit 40 and the “bus use request / write” signal, and the AND gate 42 outputs the counter 34-1. And outputs the logical product of the set signal of the access cycle to the register, the output from the OR gate 41, and the bus use permission signal from the arbitration unit 24-1 to the set terminal (SET) of the latch circuit 43.

The latch circuit 43 is set at the rising edge of the output of the AND gate 42 and outputs a memory access signal to the memory 21-1. The underflow detection circuit 44 includes the access cycle control counter 3
The value of 4-1 changes from “1” to “0” by the countdown operation (underflow; predetermined access
When the end of the cycle is detected, a signal which rises is output to the reset terminal (RESET) of the latch circuit 43.

That is, either the “bus use request / read” signal or the “bus use request / write” signal from the bus use request generation circuit 40 rises, and the arbitration unit 2
When the bus use permission signal is output from 4-1 and the value of the access cycle is set in the counter 34-1 and the set signal rises, the latch circuit 43 is set to the state where the memory access signal has risen. .

The output state of the memory access signal is reset by the rise of a signal from the underflow detection circuit 44 at the end of a predetermined access cycle. Therefore, the latch circuit 4
3 is supplied from the register 31-1 or 32-1 to the access cycle control counter 3
4-1 rises by the value of the access cycle set, that is, the access cycle control counter 34-1
Will be generated for the access cycle set to.

On the other hand, the arbitration unit 24-1 is provided with the synchronization circuit 4
5, an arbitration circuit 46, a bus use permission issuing circuit 47, a priority invalidation register 48, and an OR gate 49. The synchronization circuit 45 is provided conventionally, and synchronizes the arbitration operation of the own system with the arbitration operation of the other system in response to bus use request information from the other system.

The arbitration circuit 46 is also provided conventionally, and performs an arbitration operation so as to always give priority to the memory access of one module (for example, the module (# 0) 20-1). It is. When the read accesses conflict with each other, the memories 21-1 and 21-2 have the same data and the data does not collide on the shared bus 26 in the read access. 1, 20-2 are executed simultaneously. When there is a conflict between write accesses, the arbitration unit 24-
The write access in the module (# 0) 50-1 is preferentially performed by 1, 24-2. Further, when a read access and a write access conflict, in the present embodiment, basically, the operation of the bus use permission issuing circuit 47 to be described later has priority over the operation of the arbitration circuit 46, but the priority to be described later When the invalid register 48 is set, the arbitration circuit 46 operates to give priority to the memory access of one module (for example, the module (# 0) 20-1) as in the related art.

However, the arbitration circuit 46 of the present embodiment receives the output from the above-described waiting cycle control counter 36-1 or 36-2 when the access of the other system is preferentially executed and receives the output shown in FIG. As described above, the access of the own system is executed after waiting for the total time of the contention cycle and the wait cycle calculated by the wait cycle calculation unit 35-1 or 35-2 of the own system.

The bus use permission issuing circuit 47 gives unconditional priority to the read / write control unit 23-1 for the use of the type set in the read / write priority register 37-1. Issued to
In the present embodiment, the OR gate 47a, the switching unit (MUX)
47b and an AND gate 47c.

The OR gate 47a outputs the logical sum of the "bus use request / write" signal and the "bus use request / read" signal from the bus use request generation circuit 40 of the read / write control section 23-1 to the arbitration circuit 46. The arbitration circuit 46 outputs an OR gate 47
When the signal from a rises, a normal arbitration operation is started.

The switching unit (MUX) 47b sends the “bus use” from the bus use request generation circuit 40 according to the type (1: write priority / 0: read priority) set in the read / write priority register 37-1. Selectively outputs either the "request / write" signal or the "bus use request / read" signal, and outputs the "bus use request / write" signal in the case of write priority and the "bus use request / read" signal in the case of read priority. Outputs a "bus use request / read" signal.

The AND gate 47c outputs the logical product of the signal from the switching section 47b and the value of the priority invalidation register 48. When "1" is set in the priority invalidation register 48, the switching section 47c outputs the logical product. The signal ("bus use request / write" signal or "bus use request / read" signal) from 47b is output as it is as a bus use permission signal. The priority invalidation register 48 is set with information for invalidating the operation of the bus use permission issuing circuit 47. When "1" is set as described above, the bus use permission issue circuit 4
7 is valid, and if "0" is set, AND
The output from the gate 47c is always "0", and the operation of the bus use permission issuing circuit 47 is invalidated.

The OR gate 49 outputs a logical sum of an output from the arbitration circuit 46 and an output from the bus use permission issuing circuit 47 as a bus use permission signal. Therefore, in the present embodiment, the priority invalid register 48
When a conflict between read access and write access occurs while "1" is set to "1", regardless of the operation of the arbitration circuit 46, the bus use permission issuing circuit 4
7 is unconditionally sent from the OR gate 49 to the read / write controller 23-1 (AND gate 42).
Output to When "0" is set in the priority invalid register 48, or when a conflict occurs between read accesses or write accesses, the bus use permission signal from the arbitration circuit 46 is read from the OR gate 49. / Write control section 23-1 (AND gate 42).

In FIG. 3, the comparison circuits 38-1 and 38-1
38-2 is a read / write priority register 3
The value of 7-1 is compared with the value of read / write priority register 37-2.
Error information is set in the firmware 1 and 39-2, respectively, and an error is notified to the firmware. The processing module 20-of the present embodiment configured as described above
Operations 1 and 20-2 will be described.

For example, the MPU 22 of the module 20-1
In response to a read request from -1, a "bus use request / read" signal is output from the bus use request generation circuit 40 of the read / write control unit 23-1, and a bus use permission signal is output from the arbitration unit 24-1. In this case, the bus start signal rises as shown in FIG. 6 with the rise of the bus use permission signal (timing T0). With the rise of the bus start signal, the access cycle value (for example, 3) set in the read access cycle register 32-1 is set as an initial value in the access cycle control counter 34-1. Set (timing T1).

Thus, the bus use request generation circuit 40
The "bus use request / read" signal from
The three conditions that the bus use permission signal is output from the arbitration unit 24-1 and the set signal from the counter 34-1 rises are satisfied, and the read / write control unit 2
The output of the AND gate 42 at 3-1 rises, and the latch circuit 43 is set to a state where the memory access signal has risen (timing T2).

Then, by counting down the value set in the control counter 34-1 in synchronization with the clock, an access cycle of the memory 21-1 is generated, and the under cycle accompanying the end of the predetermined access cycle is generated. In response to the rise of the signal from the flow detection circuit 44, the latch circuit 43 is reset, and the memory access signal falls (timing T3).

That is, the memory access signal from the latch circuit 43 rises by the value of the access cycle set in the access cycle control counter 34-1 from the register 32-1 and is supplied to the access cycle control counter 34-1. The signal of the set access cycle will be generated. Here, the case of the read operation has been described, but the write operation is similarly performed.
A similar operation is performed in module 20-2.

Therefore, the registers 31-1 (31-2),
Only by changing the set value of the access cycle in 32-1 (32-2), the access cycle according to the set value is changed.
Access cycle control counter 34-1
Since the access cycle can be generated by (34-2), the access cycle can be changed, and a memory having a different access cycle can be mounted.

Thus, when the user wants to use a cheaper memory with a long access cycle (slow access speed) or replaces the current memory with a memory with a short access cycle (fast access speed), the user can use it. Can be easily responded to, and greatly contributes to improving serviceability. At this time, if the access cycle between the memory 21-1 and the memory 21-2 is different, the access
If the cycle is slower than the own system, the access cycle of the other system is set in the register 31-1 (31-2) as an access cycle for the write access operation, so that the access cycle is adjusted to the slower access cycle. Write operations to the two memories 21-1 and 21-2 can be performed simultaneously.

If the access cycle of the other system is slower than that of the own system (if the access cycle of the own system is faster than the other system), the access cycle of the own system is changed to the access for the read access operation. By setting a cycle in the register 32-1 (32-2), a high-speed read operation can be performed. On the other hand, if a frequently used access type (read / write) is set in advance in the read / write priority registers 37-1 and 37-2, a bus use request accompanying a write request and a bus use request accompanying a read request are determined. When they occur at the same time, it is possible to preferentially execute a type of access that is frequently performed.

At this time, in the present embodiment, the access preferentially executed is immediately executed regardless of the arbitration operation (contention cycle) by the arbitration circuit 46. For example, in the state where the read priority (“0”) is set in the read / write priority registers 37-1 and 37-2, as shown in FIG. 7, a write request is issued by the processing module (# 0) 20-1. Processing module (#
1) When a read request occurs simultaneously in 20-2, the bus request signal # 0 rises, and the processing module (# 1) 20-2 simultaneously outputs the bus request signal # 0.
1, the bus start signal # 1 rises, and the read operation is immediately and preferentially executed (timing T10).

In this case, in the processing module 20-2,
In the read / write control unit 23-2, the "bus use request / read" signal from the bus use request generation circuit 40 rises, and the "bus use request / read" signal is directly sent to the arbitration unit 24-2. The signal is output from the bus use permission issuing circuit 47 as a bus use permission signal, passes through an OR gate 49, and passes through an AND gate 42 of the read / write control unit 23-2.
Is input to

With the rise of the bus use permission signal, a read access cycle is set in the access cycle control counter 34-1 as described above with reference to FIG. 6, and the set signal rises. This allows
The three conditions are that the "bus use request / read" signal from the bus use request generation circuit 40 rises, the bus use permission signal is output from the arbitration unit 24-1, and the set signal from the counter 34-1 rises. Satisfied
The output of the AND gate 42 of the read / write control unit 23-1 rises, and the latch circuit 43 is set to a state where the memory access signal has risen. Thereafter, the read operation in the processing module 20-2 is executed in the same manner as in FIG. 6, and the memory access signal in the processing module (# 1) 20-2 has a read access cycle as shown in FIG. Stand up for a while.

At this time, in the processing module 20-1,
The waiting cycle calculation unit 36-1 calculates, as the waiting cycle, the time from the end of the contention cycle during the normal arbitration operation of the arbitration unit 24-1 until the execution of the read access by the processing module 20-2 is completed. . That is,
In the waiting cycle calculation unit 36-1, the write access / write access set in the register 31-1 is performed by the comparison circuit 27.
The cycle is compared with the read access cycle set in the register 32-1. If they are equal, the value is output as it is, while if they are not equal, the larger value is output. Thereafter, in the arithmetic circuit 29, the contention cycle register 28
The waiting cycle C is calculated by subtracting the value B corresponding to the contention cycle set in (1).

Then, the value of the waiting cycle calculated by the waiting cycle calculation unit 36-1 is set as an initial value in the waiting cycle control counter 37-1. After the contention cycle B in the arbitration circuit 46 is completed, the counter 37 By counting down the value of -1 in synchronization with the clock, the wait cycle C for detecting the read end is read.
Is generated.

As a result, the arbitration circuit 46 in the arbitration unit 24-1 determines the time obtained by adding the contention cycle B and the waiting cycle C (in this embodiment, the time corresponding to the read access cycle A in the processing module 20-2). After waiting for the time, the bus use permission signal is output to raise the bus start signal # 0, and the write access by the processing module 20-1 of the own system is executed (timing T11).

As described above, according to the present embodiment, if the frequent access type (read / write) is set in the read / write priority registers 37-1 and 37-2 in advance, the bus associated with the write request is set. When a use request and a bus use request accompanying a read request occur simultaneously, a bus use permission signal is issued unconditionally by the bus use permission issuing circuit 47 for the access of the set type, and the access of the type with high frequency is given priority. Since the processing is executed immediately and immediately, the processing speed is increased and the performance of the apparatus is greatly improved.

At this time, on the module 20-1 side waiting for the priority memory access to end, the waiting cycle (guaranteed cycle) calculated by the waiting cycle operation unit 35-1 is replaced by the waiting cycle. The module 2 of the other system is generated by the control counter 36-1.
The time point at which the memory access ends at 0-2 is reliably estimated, and the next memory access (the previous conflicted access) can be immediately executed almost simultaneously with the end of the memory access, thereby increasing the processing speed and the device performance. Contribute to the improvement of

However, if invalidation information “0” is set in the priority invalidation register 48 in the arbitration units 24-1 and 24-2, the operation of the bus use permission issuing circuit 47 is invalidated, and the normal operation of the arbitration circuit 46 is performed. An arbitration operation can be performed. If the value of the read / write priority register 37-1 is different from the value of the read / write priority register 37-2, the comparison circuits 38-1 and 38-3
-2 detects the difference and notifies the firmware of an error, so that a malfunction due to such a difference in values can be reliably prevented.

In the above embodiment, the case where the read operation is prioritized has been described. However, by setting "1" to the read / write priority registers 37-1 and 37-2, the write operation is performed in the same manner as described above. Operations can be prioritized. Further, the present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the present invention and its gist.

[0079]

As described above in detail, according to the processing module of the present invention (claims 1 to 3), only by changing the set value of the access cycle in the access cycle storage unit, the set value can be changed. A corresponding access cycle can be generated by the access cycle control unit, and the access cycle can be changed, so that memories with different access cycles can be mounted. Therefore, access
The user can easily respond to the demands of the user, such as when the user wants to use a cheaper memory with a long cycle (slow access speed) but wants to replace the current memory with a memory with a short access cycle (fast access speed). Contributes to improved serviceability.

The processing module of the present invention (claim 4)
According to 8), if a frequently accessed type (read / write) is set in the read / write priority register in advance, a bus use request accompanying a write request and a bus use request accompanying a read request occur simultaneously. In this case, the access of the type that is frequently performed is preferentially executed, so that the processing speed is increased and the performance of the apparatus is greatly improved.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a principle block diagram of the present invention.

FIG. 3 is a block diagram showing a configuration of a system having a processing module as one embodiment of the present invention.

FIG. 4 is a block diagram illustrating a detailed configuration of a read / write control unit and an arbitration unit according to the embodiment.

FIG. 5 is a block diagram illustrating a detailed configuration of an arithmetic circuit according to the present embodiment.

FIG. 6 is a time chart for explaining a memory access operation in the embodiment.

FIG. 7 is a time chart for explaining an arbitration operation (arbitration operation) in the embodiment.

FIG. 8 is a block diagram showing a configuration of a system having a conventional processing module.

FIG. 9 is a time chart for explaining an arbitration operation (arbitration operation) in a conventional processing module.

[Explanation of symbols]

10, 10A processing module 11 memory 12 processing unit 13 read / write control unit 14 arbitration unit 15 shared bus 16 access cycle storage unit 17 access cycle control unit 18 read / write priority register 20-1, 20-2 processing module 21 -1, 21-2 memory 22-1, 22-2 processing unit 23-1, 23-2 read / write control unit 24-1, 24-2 arbitration unit 25-1, 25-2 OR gate 26 shared bus 27 Comparison circuit 28 Competing cycle register 29 Arithmetic circuit 31-1, 31-2 Write access cycle register (access cycle storage unit) 32-1, 32-2 Read access cycle register (access cycle storage) Unit) 33-1 and 33-2 Switching unit (MUX) 34-1 and 34-2 Access Cycle control counter (access cycle control unit) 35-1, 35-2 read / write priority register 36-1, 36-2 wait cycle operation unit 37-1, 37-2 wait cycle control counter (guaranteed cycle control unit) 38-1, 38-2 Comparison circuit 39-1, 39-2 Error register 40 Bus use request generation circuit 41 OR gate 42 AND gate 43 Latch circuit 44 Underflow detection circuit 45 Synchronization circuit 46 Arbitration circuit 47 Bus use permission Issue circuit 47a OR gate 47b Switching unit (MUX) 47c AND gate 48 Priority invalid register 49 OR gate

Claims (8)

[Claims] 1. A memory connected to a processing module of another system via a shared bus, a processing unit for performing processing based on data held in the memory, and a read / write request from the processing unit A read / write control unit for controlling access to the memory, and an arbitration unit for arbitrating the right to use the shared bus between the other processing module, and a write request from the processing unit. Depending on the lead /
When writing to the memory by the write control unit, the same writing is performed to the memory in the processing module of the other system via the shared bus, so that the memory always performs the processing of the other system. In a processing module configured to hold the same contents as a memory in a module, an access cycle in which an access cycle of the memory is set
A processing module, comprising: a cycle information storage unit; and an access cycle control unit that generates an access cycle of the memory set in the access cycle storage unit. 2. A register for setting an access cycle of a memory in a processing module of another system for a write access operation when an access cycle of the memory and a memory of the processing module of another system are different. 2. The processing module according to claim 1, wherein the processing module is provided as the access cycle storage unit. 3. A register for setting an access cycle of the memory for a read access operation when an access cycle of the memory differs from that of the memory of the processing module of the other system, the register storing the access cycle. 2. The device as claimed in claim 1, wherein
Alternatively, the processing module according to claim 2. 4. A memory connected to a processing module of another system via a shared bus, a processing unit for performing processing based on data held in the memory, and responding to a read / write request from the processing unit. A read / write control unit for controlling access to the memory, and an arbitration unit for arbitrating the right to use the shared bus between the other processing module, and a write request from the processing unit. Depending on the lead /
When writing to the memory by the write control unit, the same writing is performed to the memory in the processing module of the other system via the shared bus, so that the memory always performs the processing of the other system. In a processing module configured to hold the same contents as a memory in a module, a read / write priority register in which an access type to be preferentially executed is preset is provided, and the read / write control unit and the other system are provided. When a bus use request accompanying a write request and a bus use request accompanying a read request are simultaneously generated from the read / write control unit in the processing module of, the access of the type set in the read / write priority register is preferentially performed. A processing module characterized by being configured to execute. 5. The arbitration unit receives the read / write request for the type of access set in the read / write priority register.
5. The processing module according to claim 4, further comprising a bus use permission issuing circuit that unconditionally preferentially issues a bus use permission to the write control unit. 6. The processing module according to claim 5, wherein said arbitration unit is provided with a priority invalidation register in which information for invalidating an operation of said bus use permission issuing circuit is set. 7. When the access by the other processing module is preferentially executed, after the contention cycle in the normal arbitration operation of the arbitration unit is completed, the execution of the access by the other processing module is completed. A guaranteed cycle calculation unit that calculates a guaranteed cycle according to the time required to perform the operation, and a guaranteed cycle control unit that generates the guaranteed cycle calculated by the guaranteed cycle calculation unit after the completion of the contention cycle. Claim 4
The processing module according to claim 6. 8. A comparing circuit for comparing the value of the read / write priority register with the value of the read / write priority register in the processing module of the other system, and notifying an error to the firmware if the values are different. The processing module according to claim 4, wherein: