JPH11248803A - Timing generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timing generation circuit by which a timing signal in a short cycle is generated without using a memory whose access time is small. SOLUTION: In an address generation circuit 1, an m-stage leading address signal An+m is outputted to an m-1-stage shift register 5 by the input of a timing signal DTn. The m-1-stage shift register 5 inputs an m-stage leading address signal An+m by a shift timing signal ST, and it outputs an address signal An+1 to a memory 3. The memory 3 outputs cycle data Dn+1 stored in an address for the address signal An+1 by using the address signal An+1. However, the memory 3 requires the access time until the cycle data Dn+1 is outputted. When the timing of the timing single ST is set at a proper value, cycle data Dn is inputted to a counter circuit 4 by the timing signal DTn in an AND gate 7. The counter circuit 4 performs a counting operation one by one at every prescribed interval up to the value of the input cycle data Dn, it generates a timing signal DTn+1 when the counting operation is finished, and it outputs the shift timing signal ST to the m-1-stage shift register 5 before the finish tie of the counting operation on the basis of the cycle data Dn.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generation circuit which is applied to an IC (integrated circuit) tester or the like and generates a variable timing signal serving as a reference for an operation test of an IC.

[0002]

2. Description of the Related Art A signal path of a conventional timing generation circuit will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of a conventional timing generation circuit. In this figure, an m-stage preceding address signal An + m, which precedes a timing signal DTn (n is a natural number) output by the counter circuit 4 by “m (m is a natural number)”, is applied to the address generator 1. Output from

The m-stage shift register 2 outputs an address signal An to the memory 3 in which the cycle data of the timing signal Dn is stored in synchronization with the shift timing signal ST in accordance with the input m-stage preceding address signal An + m. . This shift timing signal ST is a signal output from the counter circuit 4 and adjusted in timing by the delay circuit 8. The memory 3 outputs the period data Dn to the AND circuit 7 based on the input address signal An.

The AND circuit 7 outputs the period data Dn to the counter circuit 4 at the timing when the timing signal DTn becomes "1". The counter circuit 4 counts the time based on the input period data Dn, and outputs a timing signal DTn + 1 to the delay circuit 6 when the counting is completed.
Further, the address generation circuit 1 generates a next m-stage preceding address signal An + m + 1 according to the timing signal DTn + 1 input via the delay circuit 6.

Next, the operation of the conventional timing generation circuit will be described with reference to FIGS. FIG. 5 is a timing chart showing the operation timing of the timing generation circuit. At time t1, the m-stage shift register 2
Receives a shift timing signal ST. Thus, at time t2, the memory 3
To output the cycle data Dn. Here, the time from time t1 to time t2 is defined as T3.

The access time from the input of the address signal An of the memory 3 to the output of the periodic data signal Dn occupies most of the time T3. Therefore, the time T
3 is simply the access time of the memory 3.

At time t3, the AND circuit 7
Outputs the cycle data Dn to the counter circuit 4. Here, the time T3a is a time from time t2 when the periodic data signal Dn is input to the AND gate 7 to time t3 when the periodic data signal Dn is input to the counter circuit 4.
Therefore, the shift timing signal ST of the m-stage shift register 2 needs to be input to the m-stage shift register 2 at a time that is at least a time obtained by adding the time T3 and the time T3a to the rise of the timing signal DTn. .

As a result, if the time from the shift timing signal ST to the timing signal DTn is T2, the relationship of T2> T3 + T3a must be satisfied.

Further, the period T1 of the timing signal DTn
Must be set longer than the time T2,
The condition for setting the cycle T1 is T1>T2> T3 + T3a. The cycle T1 indicates, for example, the time from time t3 to time t4. That is, the cycle T1 indicates the cycle at which the timing signal DTn is output.

[0010]

As the operating frequency of an IC increases, the operating frequency of a timing generator of an IC test apparatus such as an IC tester needs to be increased. However, in the conventional timing generation circuit, the condition of T1>T2> T3 + T3a must be satisfied.

Therefore, the period T1 of the timing signal DTn
Is to shorten the access time T3 of the memory 3. However, memories with short access times are expensive and difficult to obtain. The present invention has been made in view of such a background, and an object of the present invention is to provide a timing generation circuit that generates a timing signal having a short cycle without using a memory having a fast access time.

[0012]

According to the first aspect of the present invention,
An address generating means for generating, when a timing signal is inputted, an m-stage preceding address signal corresponding to a timing signal preceding the timing signal by m (m is a natural number) in the timing generating circuit; When a signal is input, the first-in first-out
An m-1 stage shift register for sequentially inputting and holding the stage preceding address signal and sequentially outputting the held address signal simultaneously, and storing the address signal corresponding to the address signal when the address signal is input. A memory for outputting the cycle data that has been output, counts the time, and when the count value of the count result matches the cycle data, compares the count value of the count result with the cycle data. And a timing generating means for outputting a shift timing signal and a timing signal of a predetermined cycle as a result of the above. With this configuration, the data signal can be read from the memory in parallel with the process of outputting the timing signal, so that it is not necessary to consider the access time of the memory.

According to a second aspect of the present invention, in the timing generating circuit according to the first aspect, the timing generating means is constituted by a counter, and counts "1" at predetermined time intervals until the numerical value of the periodic data is obtained. A timing signal is output when the count value of the counting result matches the periodic data.

According to a third aspect of the present invention, in the timing generation circuit of the first or second aspect, the shift register and the timing generation circuit, wherein the shift timing signal is delayed by a predetermined time and input to the timing generation means. And a delay circuit interposed between the first and second means.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a timing generation circuit according to one embodiment of the present invention. In this figure, 1 is an address generation circuit, and m
M-stage preceding address signal An + m indicating the stage ahead address
Are output when the timing signal DTn is input to the m-1 stage shift register 2. This timing signal DTn
Are output from the counter circuit 4 and the timing is adjusted by a delay circuit 6 interposed between the counter circuit 4 and the address generation circuit 1.

The shift register 5 receives the m-stage preceding address signal An + m when the shift timing signal ST is input. Further, the m-1 stage shift register 5 outputs the address signal An + 1 to the memory 3 because the address signal Am + n is shifted by m-1 stages when the shift timing signal ST is input. The shift timing signal ST is output from the counter circuit 4 and its timing is adjusted by the delay circuit 8 inserted between the counter circuit 4 and the (m-1) -th stage shift register 5.

The memory 3 stores the address signal An +
Due to 1, the cycle data Dn + 1 stored at the address indicated by the address signal An + 1 is output. However, although the periodic data Dn + 1 starts to be output from the memory 3, the memory 3
Because of having the access time T3, the periodic data Dn + 1 is actually
It takes time T3 to output. Therefore, by selecting the timing of the timing signal ST to an appropriate value, the periodic data Dn is passed by the timing signal DTn by the AND gate 7 and input to the counter circuit 4.

The counter circuit 4 counts "1" at predetermined intervals until the value of the periodic data Dn input from the AND gate 7 is reached, and generates a timing signal DTn + 1 when the counting is completed. The timing signal DTn + 1 is adjusted in timing by being delayed by a predetermined time by the delay circuit 6, and is input to the address generation circuit 1. Further, the counter circuit 4 generates a shift timing signal ST before the time T2 of counting based on the value of the periodic data Dn, and
Output to the one-stage shift register 5.

Next, the operation of the timing generation circuit according to one embodiment will be described with reference to FIGS. FIG.
4 is a timing chart showing the operation of the timing generation circuit according to one embodiment of the present invention. At time t1, the counter circuit 4 outputs the shift timing signal ST.

The m-1 stage shift register 5 receives the m-stage preceding address signal Am + n output from the address generation circuit 1 in response to the shift timing signal ST delayed and input by the delay circuit 8. At the same time, m
The -1 stage shift register 5 outputs the address signal An + 1 to the memory 3.

Then, at time t2, the counter circuit 4 outputs the timing signal DTn to the address generation circuit 1 via the delay circuit 6. When the timing signal DTn is input, the address generation circuit 1 converts the m-stage preceding address An + m into the (m−1) -stage shift register 5.
Output to

At time t2, the memory 3 outputs the periodic data Dn. Accordingly, the period data Dn is output from the AND gate 7 because the timing signal DTn is at the “H” level. For this reason,
The cycle data Dn is input to the counter circuit 4.

Therefore, in order to stabilize the input of the cycle data Dn to the counter circuit 4, the time t1 is set to a predetermined value so that a hold time T4 of the cycle data Dn from time t2 to time t3 can be secured. Need to be Then, the counter circuit 4 calculates the input period data D
Start counting time based on n.

Next, at time t4, the output data of the memory 3 transitions from the cycle data Dn to the cycle data Dn + 1. At this time, if the access time T3 of the memory 3 is too short, or if it is desired to correct the error of the access time T3, the delay time of the delay circuit 8 is changed and the m-1 stage shift register of the shift timing signal ST is changed. 5 will be adjusted.

Next, at time t5, the counter circuit 4
Outputs the shift timing signal ST to the (m-1) -th stage shift register 5 via the delay circuit 8 assuming that the count value becomes the value of the period data Dn and the time T2 is before the time t6 when the counting operation is completed. . The m-stage preceding address output from the address generation circuit 1 is input to the (m-1) -th stage shift register 5 when the shift timing signal ST is input. As described above, the timing generation process is repeatedly performed.

The condition for establishing the cycle T1 of the timing signal DTn in the above-described timing generation circuit is that the time from the rise of the shift timing signal ST to the rise of the timing signal DTn is T2, and the access time of the memory 3 is time T3. T2 <T3T1 + T2>T3T1> T2.

The cycle T1 of the timing signal DTn does not depend on the access time T3 of the memory 3 if the shift timing signal is set so that the condition of T2 <T3T1 + T2> T3 is satisfied.

FIG. 3 is a timing chart of an application example of the timing generation circuit according to one embodiment. When the access time T3 of the memory 3 is set to "20 ns", and the time T2 "10 ns" from the rise of the shift timing signal ST to the output of the timing signal DTn has a margin of "5 ns" and "15 ns", The cycle T1 of DTn is changed from “T1 + T2 = 25 ns” to “15”.
ns ”.

As described above, according to the timing generation circuit of one embodiment, the m-stage preceding address An + m supplied from the address generation circuit 1 is, for example, m-1 stages of m-
The data is shifted by the one-stage shift register 5 and input to the memory 3 in which the cycle data Dn of the timing signal DTn is stored. The memory 3 starts outputting the cycle data Dn + 1 one stage ahead, but the shift timing signal is selected so that the cycle data Dn one stage ahead can be input.

That is, the access time T3 of the memory 3 is made smaller than the sum of the period T1 of the timing signal DTn and the time T2 when the shift timing signal ST is output from the counter circuit 4 earlier than the timing signal DTn. As a result, since the period T1 is not affected by the access time of the memory 3, the timing signal DTn can be provided in the timing generation circuit of one embodiment without using an expensive high-speed memory.
Has the effect of shortening the cycle of

[0031]

According to the first aspect of the present invention, when a timing signal is input, an m-stage preceding address signal corresponding to a timing signal preceding the timing signal by m (m is a natural number) stages And an m-1 stage shifter for sequentially inputting and holding the m-stage preceding address signals in a first-in first-out manner when a shift timing signal is input, and sequentially outputting the simultaneously held address signals. A register, when the address signal is input, a memory for outputting cycle data stored at an address corresponding to the address signal, and a time count, and counts the count result and the cycle data. And a timing generating means for outputting a shift timing signal and a timing signal of a predetermined cycle as a result of the comparison. Therefore, the order period of the timing signal is not affected by the access time of the memory, there is an effect capable of shortening the period of the timing signal without using a memory having an expensive high-speed access time

According to the second aspect of the present invention, the timing generating means is constituted by a counter, and counts "1" at predetermined time intervals until the value of the periodic data is obtained.
Since the timing signal is output when the count value of the counting result matches the cycle data, there is an effect that the cycle of the timing signal can be accurately adjusted to a predetermined time.

According to the third aspect of the present invention, there is provided a delay circuit interposed between the shift register and the timing generating means for delaying the shift timing signal by a predetermined time and inputting the signal to the timing generating means. In order to provide, the time when the shift timing signal is input to the shift register is changed by delaying by a predetermined value,
There is an effect that the cycle of the timing signal can be adjusted to a predetermined time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a timing generation circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation of the timing generation circuit of FIG. 1;

FIG. 3 is a timing chart when the timing generation circuit of FIG. 1 is actually applied.

FIG. 4 is a block diagram showing a configuration of a timing generation circuit according to a conventional example.

FIG. 5 is a timing chart showing an operation of the timing generation circuit of FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address generation circuit 3 Memory 4 Counter circuit 5 m-1 stage shift register 6, 8 Delay circuit 7 AND circuit

Claims (3)

[Claims] 1. An address generating means for generating an m-stage preceding address signal corresponding to a timing signal preceding by m (m is a natural number) stages when a timing signal is inputted, and a shift timing When the signal is input, the first-in first-out order, the m-stage preceding address signal is sequentially inputted and held,
M- which sequentially outputs simultaneously held address signals
A one-stage shift register; a memory for outputting periodic data stored at an address corresponding to the address signal when the address signal is input; and a time counting unit. A timing generating circuit for comparing the periodic data with the timing data and outputting a shift timing signal and a timing signal having a predetermined period as a result of the comparison. 2. The timing generating means is constituted by a counter, and counts “1” at predetermined time intervals until the numerical value of the periodic data is reached, and the counted value of the counting result matches the periodic data. 2. The timing generation circuit according to claim 1, wherein a timing signal is output at a time. 3. A delay circuit interposed between said shift register and said timing generating means for inputting said shift timing signal to said timing generating means with a predetermined time delay. 3. The timing generation circuit according to claim 1 or 2.