JPH11242892A - Nonvolatile semiconductor storage device and its data writing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely make a semiconductor storage perform a self-boosting operation and also to attain the quick access in the device by applying the voltage set high on a boost while controlling timings and applying the voltage set low on a drain side selection gate. SOLUTION: In a control circuit 12, after a bit line BL1 is charged to a power source voltage Vcc by making transistors NT1, NT2 to be respectively conductive and nonconductive with signals PGM1, 2 and by making a transistor PT1 conductive with a Vref, the PGM2 is made a high level and when latched data of a latch circuit Q1 is '0', the data is written by bringing up all word lines of a selection siring to the Vcc while applying a prescribed voltage on the gate SG1A of a drain side selection transistor. When a drain side selection transistor is cut off in the case the data is '1', and non-selection word lines are brought up to a prescribed voltage in the case the data is '0', a channel is sepctrated from the BL by the drain side transistor and a channel voltage is boosted to a non-write volt age.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device such as a NAND flash memory and a data writing method thereof.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor nonvolatile memory device such as an EPROM or a flash memory, data is written by injecting electrons into a floating gate by channel hot electron injection (hereinafter, CHE).
R-type semiconductor nonvolatile memory devices have been the mainstream. However, in the above-described NOR type semiconductor nonvolatile memory device, since one bit contact and one source line are shared by two memory transistors, it is difficult to achieve high integration and a large capacity cannot be achieved. is there.

In view of the above, a NAND string is formed by connecting a plurality of memory transistors in series to form two NAND transistors.
There has been proposed a NAND flash memory that achieves high integration by sharing one bit contact and one source line in the D column.

In a general NAND flash memory, an erasing operation is performed by applying 0 V to all word lines of a selected NAND column block and applying a high voltage (for example, 20 V) to all word lines of a non-selected NAND column block and a substrate of a memory array. I do. As a result, electrons are extracted from the floating gate to the substrate only in the memory transistor of the selected NAND string block, and the threshold voltage of the memory transistor shifts in the negative direction to about -3 V, for example.

On the other hand, a data write operation is performed in a so-called page unit for the memory transistors connected to the selected word line at a time, and a high voltage (for example, 18 V) should be written to the selected word line (0 data). 0) Apply 0 V to the bit line to which the memory transistor is connected, and apply an intermediate voltage (for example, 8 V) to the bit line to which the write-inhibited (1 data) memory transistor is connected. As a result, electrons are injected into the floating gate of only the selected memory transistor to be written, and the threshold voltage of the selected memory transistor shifts in the positive direction to, for example, about 2V.

In such a NAND flash memory, both writing and erasing of data are performed by FN (Fowler No.
rdheim) Since the operation is performed by the tunnel current, it is relatively easy to supply the operation current from the booster circuit in the chip, and there is an advantage that the operation can be easily performed by a single power supply. Furthermore, since data is written in units of pages, that is, collectively for the memory transistors connected to the selected word line,
As a corollary, it is advantageous in terms of writing speed.

[0007]

The above-mentioned N
AND flash memory has the following disadvantages.
That is, since the data write operation of the NAND flash memory is performed in page units, it is necessary to apply an intermediate voltage (for example, 8 V) to all the bit lines to which the memory transistors whose writing is to be inhibited are connected. . Since the number of bit lines per page is usually 512 bytes, that is, about 4000, the load of the booster circuit for generating the intermediate voltage is large. In the above-described data write operation, since it is necessary to control the threshold voltage of the write memory transistor, a plurality of write / write operations are performed.
Since the verify operation is performed repeatedly,
It is necessary to charge the write inhibit bit line to an intermediate voltage.

For this reason, when the number of write / verify times increases, the time required for switching the bit line voltage in the write / verify operation becomes dominant rather than the substantial write time, and the write speed is limited, making high-speed write difficult. Becomes Further, the data latch circuit provided for each bit line and for latching page data needs to have a high withstand voltage specification in order to handle an intermediate voltage, so that the size is inevitably large, and therefore, the data latch circuit for each bit line is required. The layout of the data latch circuit becomes difficult.

The above-mentioned problems have been solved, and a NA suitable for a single power supply operation at a low voltage, capable of high-speed writing, and having a simple layout of a data latch circuit for each bit line.
A new writing method of the ND type flash memory is disclosed in the following literature. Reference: IEEE JOURN
AL OF SOLID- STATE CIRCUIT
S, VOL. 30, NO. 11, NOVEMBER 1
995 p1152-p1153, and FIGS.

In the data write operation disclosed in the above-mentioned document, a NAND string connected to a memory transistor to be inhibited from writing is placed in a floating state, and a channel voltage of the NAND string is mainly applied to an unselected word line. The voltage is automatically boosted by capacitive coupling with a pass voltage (for example, 10 V). This automatic boosting operation is called a self-boost operation.

FIG. 3 is a diagram for explaining an operation when data is written to the NAND flash memory by the above-described self-boost operation.

The NAND type flash memory shown in FIG. 3 has four NAND strings connected to two bit lines for convenience.
FIG. 4 is a diagram showing a memory array in which memory transistors are connected in series. In an actual memory array, the number of memory transistors connected in series to one NAND string is generally about 16 . In FIG. 3, BLa and BLb indicate bit lines, and bit lines BLa
Is connected to a NAND string in which two select transistors ST1a to ST2a and four memory transistors MT1a to MT4a are connected in series. In addition, bit line B
Lb includes two select transistors ST1b to ST2b,
And a NAND string in which four memory transistors MT1b to MT4b are connected in series. The selection transistors ST1a and ST1b are controlled by a first NAND column selection line SL1, and the selection transistors ST2a and ST2b are controlled by a second NAND column selection line SL2. Also, the memory transistors MT1a to MT4a
And MT1b to MT4b are connected to word lines WL1 to WL1 respectively.
Controlled by WL4.

Next, in the NAND flash memory shown in FIG. 3, when page writing is performed by selecting the word line WL2, MT2a is a memory transistor to be inhibited from writing, and MT2b is a memory transistor to be written. The operation in this case will be described.

First, the power supply voltage V _cc (3.3 V) is applied to the NAND column selection line SL1, and the ground voltage GND (0 V) is applied to the selection line SL2.
V), and the power supply voltage V is applied to the bit line BLa to which the memory transistor MT2a for which writing is to be inhibited is connected.
_CC (3.3 V), memory transistor M to be written
Ground voltage GND is applied to bit line BLb to which T2b is connected.
(0 V) is applied. Next, a write voltage Vpgm (for example, 18 V) is applied to the selected word line WL2, and a pass voltage Vpass (for example, 10 V) is applied to the non-selected word lines WL1, WL3 to WL4.

As a result, the channel portion of the NAND string to which the memory transistor MT2a to be prohibited from writing is connected is in a floating state, and the potential of the channel portion is mainly a non-selected word line (three in FIG. 3, (Generally 15 lines).
Due to the capacitor coupling with pass, the voltage is boosted and rises to the write inhibit voltage, and the data write to the memory transistor MT2a is inhibited. On the other hand, the channel portion of the NAND string to which the memory transistor MT2b to be written is connected is set to the ground voltage GND (0 V), and the write voltage Vpg applied to the selected word line is set.
Due to the potential difference from m, data is written to the memory transistor MT2b, and the threshold voltage shifts in the positive direction, for example, from -3V in the erased state to about 2V.

FIGS. 4 (a) and 4 (b) show the self-
FIG. 4A is a diagram for explaining a boost operation. FIG. 4A shows a write-inhibited NAND in a self-boost operation.
FIG. 4B shows one memory transistor in a column, and FIG. 4B is an equivalent circuit diagram thereof.

In FIG. 4A, VC is a word line WL.
(Control gate CG), VF is the potential of the floating gate FG, Vch is the boosted NAND column channel potential, C-ono is the interlayer capacitance composed of a three-layer insulating film between the control gate and the floating gate, C-tox is the capacitance of the tunnel oxide film, C
-ch is the channel capacitance of the memory transistor including the source / drain diffusion layer region. L-dep is a depletion layer spreading length in the source / drain diffusion layers. In FIG. 4B, C-ins is a combined capacitance obtained by connecting the interlayer capacitance C-ono and the tunnel oxide film capacitance C-tox in series.

According to the equivalent circuit of FIG. 4B, the NAND column channel potential Vch during the self-boost operation is (1)
It is expressed by an equation.

[0019]

Vch = Br · VC (1) Here, Br is a self-boost efficiency represented by the following equation (2), which is usually determined by an optimum design of the device structure.
Set to about 0.8.

[0020]

## EQU2 ## Br = C-ins / (C-ins + C-ch) (2)

By the way, in the self-boost operation at the time of writing, VC in equation (1) is a weighted average of all word line applied voltages, but in a general NAND type flash memory, a word forming a NAND string is used. Since the number of lines is about 16, the pass voltage Vpass applied to the non-selected word lines becomes dominant. Therefore, equation (1) is represented as equation (3).

[0022]

Vch = Br · Vpass (3)

Therefore, Br ≒ 0.8, Vpass =
If it is 10 V, Vch ≒ 8 V, which can be a sufficient write inhibit voltage.

NA by the self-boost operation described above
In the data write operation of the ND type flash memory, it is not necessary to apply a high intermediate voltage to the non-selected bit lines, so that it is suitable for a single power supply operation at a low voltage, high-speed write is possible, and each bit line has The layout of the data latch circuit is easy.

However, in order to realize the self-boost operation, it is necessary to increase the self-boost efficiency Br to at least 0.6 to 0.8. If the self-boost efficiency Br cannot be sufficiently obtained, the NAND column channel potential Vch does not sufficiently increase, and therefore, in the example of FIG. 3, erroneous writing may be performed on the non-selected memory transistor MT2a. Also, the pass voltage Vpas
If an attempt is made to raise the channel potential Vch by increasing s, in the example of FIG. 3, erroneous writing may be performed on the non-selected memory transistors MT1b, MT3b to MT4b. Also, the self-boost efficiency B
Since r cannot be 1 in principle, even if no erroneous writing is performed on the non-selected memory transistor, the disturb is inevitably deteriorated.

Considering this problem, the self-
To achieve the boost, the write data must be “1”.
If (bit line voltage: V _CC -Vth), the memory string channel voltage by the transistor cut-off selection gate needs to be boosted to the non-writing voltage. For this reason, the gate voltage of the select gate transistor at the time of writing is set to be lower than the power supply voltage V _CC, and the threshold voltage Vth of the select gate transistor is set to be higher and cut off immediately when the word line rises. It is necessary to make it. Therefore, the boost voltage is boosted only to a voltage obtained by multiplying the pass voltage Vpass by the capacitance ratio (self-boost efficiency). If the boost voltage is low, for example, if the pass voltage Vpass is 9 V or less, when the write data is "1", a high electric field is generated between the floating gate and the channel in the write cell, and writing occurs. Writing occurs even if the boost voltage decreases due to leakage during the writing period.
Password line voltage Vpas to increase boost voltage
When s is increased to, for example, 11 V or more, when write data is "0" (channel voltage is 0 V), disturb-based writing occurs in unselected cells on the same string.

Therefore, the pass voltage Vpa at the time of writing is
ss becomes 9V ≦ Vpass ≦ 11V, and 7.2V ≦ V
ch ≦ 8.8V. One write time is 10-2
However, if the channel voltage drops to a certain value or more due to leakage in the cell where the write data is "1" during this period, an electric field sufficient to generate an FN tunnel between the floating gate and the channel is generated. ,
Writing happens.

In the conventional circuit, the threshold voltage of the NMOS transistor forming the drain side select gate is set so that the drain side select gate SG1a (SG1b) is reliably cut off and the boost operation is started. It is set higher. For this reason, in the conventional self-boost method, the initial charge initially supplied from the bit line does not significantly contribute to the boost voltage.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of surely causing self-boost and improving disturb resistance.

[0030]

In order to achieve the above object, the present invention is directed to a memory transistor in which a plurality of memory transistors for electrically writing and erasing data are connected, and one end and the other end thereof are connected in accordance with a gate voltage. Memory strings connected to a bit line and a ground line via a selection transistor whose conduction state is controlled are arranged in a matrix,
A semiconductor non-volatile memory device in which control gates of memory cell transistors in the same row are connected to a common word line and data is written using self-boost. A second voltage higher than the first voltage is applied to the gate of the transistor, and the first voltage is applied to the word line to make the channel potential of the memory string the same as the bit line potential. A first voltage is applied to the gate of the connected selection transistor, a third voltage higher than the second voltage is applied to a selected word line, and the third voltage and the first voltage are applied to an unselected word line. And control means for applying a voltage intermediate to the voltage of.

In the present invention, the first voltage is substantially the same as the higher voltage applied to the bit line, and the intermediate voltage is the second voltage.

In the present invention, the selection transistor on the bit line side is an insulated gate field effect transistor, and the threshold voltage is set to a standard value.

Also, in the present invention, the memory string is a NAN in which a plurality of memory transistors are connected in series.
It has a D-row configuration.

The present invention also provides a memory transistor for electrically writing and erasing data, a plurality of memory transistors connected to each other, and one end and the other end of which are connected via a selection transistor whose conduction state is controlled in accordance with a gate voltage. Memory strings connected to a bit line and a ground line are arranged in a matrix, control gates of memory cell transistors in the same row are connected to a common word line, and a semiconductor nonvolatile memory for writing data using self-boost. A data writing method for a storage device, wherein during a data writing operation, a second voltage higher than a first voltage is applied to a gate of a selection transistor connected to a bit line and a first voltage is applied to a word line. After setting the channel potential of the memory string to the same potential as the bit line potential, A first voltage is applied to the gate of the transistor, the third higher than the second voltage to the selected word line
And an intermediate voltage between the third voltage and the first voltage is applied to the non-selected word lines.

According to the present invention, after charging the bit line, the second voltage is supplied to the gate of the drain-side selection transistor, and all word lines of the selected string are raised to the first voltage. At this time, in the memory cell in which the write data is “1”, the channel between the drain-side selection transistor and the cell to be written is substantially charged to the first voltage. In the memory cell where the write data is “0”, the channel from the drain side select transistor to the cell to be written is set to 0V. Thereafter, the gate voltage of the drain-side selection transistor is reduced from the second voltage to the first voltage. At this time, when the write data is “1”, since the drain / source / gate of the drain-side selection transistor is all at the first voltage, the drain-side selection transistor is cut off and the channel is disconnected from the bit line. When the write data is “0”, the drain-side selection transistor is in a conductive state (on state). Here, when the unselected word line of the selected string is raised to the intermediate voltage of the third voltage and the selected word line is raised to the third voltage, the channel is separated from the bit line by the drain-side selection transistor, and the channel voltage is not written. Boosted to voltage.

[0036]

FIG. 1 is a circuit diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention. This nonvolatile semiconductor memory device 10 includes a memory cell array 11,
It is composed of a write / read control circuit 12. In an actual device, the bit lines are arranged in an array,
The nonvolatile semiconductor memory devices shown in FIG. 1 corresponding to this are arranged in a matrix.

The memory cell array 11 has a word line WL0
To WL15. The memory string A1 is connected to the bit line BL1. The memory string A1 is
Memory cell transistors MT0A to MT15A comprising a nonvolatile semiconductor memory device having a floating gate
Has a NAND string connected in series.
The drain of the memory cell transistor MT0A in the ND column is connected to the bit line BL1 via the selection gate SG1A, and the source of the memory cell transistor MT15A is connected to the reference potential line VGL via the selection gate SG2A. The threshold voltage of the NMOS transistor forming the selection gate SG1A is set to about 0.7V.

Then, the gate electrode of the selection gate SG1A is connected to the selection signal supply line SSL, and the selection gate SG2
The gate electrode of A is connected to the selection signal supply line GSL.

The write / read control circuit 12 has an n-channel M
It is composed of OS (NMOS) transistors NT1 to NT5, a p-channel MOS (PMOS) transistor PT1, and a latch circuit Q1 formed by coupling inputs and outputs of an inverter.

The NMOS transistor NT is provided between the bit line BL1 and the first storage node N1a of the latch circuit Q1.
1, NT2 are connected in series. The connection point between the NMOS transistors NT1 and NT2 is the PMOS transistor P
It is connected to the supply line of the power supply voltage V _CC via a T1, N
Grounded via MOS transistor NT3 and NM
It is connected to the gate electrode of OS transistor NT4. The NMOS transistors NT4 and NT4 are connected between the second storage node N1b of the latch circuit Q1 and the ground line.
5 are connected in series.

The signal PGM1 is supplied to the gate electrode of the NMOS transistor NT1, and the signal PGM2 is supplied to the gate electrode of the NMOS transistor NT2.
The signal RST is supplied to the gate electrode of the MOS transistor NT3, the signal RD is supplied to the gate electrode of the NMOS transistor NT5, and the signal Vref supply line is connected to the gate electrode of the PMOS transistor PT1.

[0042] In the non-volatile semiconductor memory device 10, not shown, to earn a cell current during read, the power supply voltage V _CC = 3. In 3V 4. 5~6. 0V (hereinafter, P5
V) is provided with a P5V booster circuit for performing word line boosting.

Next, the write operation of the above configuration will be described with reference to the timing chart of FIG.

First, while the signal PGM1 is set to the high level and the NMOS transistor NT1 is kept conductive, the signal PGM2 is set to the low level, and the bit line BL1 and the first storage node N1a of the latch circuit Q1 are set.
Is maintained in a non-conductive state. In this state, the signal Vref is set to the low level, and the PMOS transistor PT1 is held in the conductive state. As a result, the bit line is charged to the power supply voltage V _CC level.

After the bit line is charged, the signal PGM2 is set to the high level, and the NMOS transistor NT2 is kept conductive. At this time, when the latch data of the latch circuit Q1 is "1", the bit line potential does not change, but when the latch data is "0", the bit line charge is
The bit line potential is pulled down to 1 and becomes 0V.

In this state, the drain-side selection gate SG1
The selection signal supply line SSL to which the gate electrode of A is connected is P
5V, all word lines in the selected string are raised to power supply voltage V _CC . At this time, the drain-side selection gate SG1
Assuming that the threshold voltage of the NMOS transistor constituting A is set to about 0.7 V, the memory cell in which the write data is "1" has a channel between the drain-side select gate SG1A on the drain side and the cell to be written. Is almost charged to the power supply voltage V _CC (since SG1A to the selected cell is depleted (Vth = −2 to −3 V)). In the memory cell where the write data is “0”, the channel from the drain-side select gate SG1A on the drain side to the write target cell is set to 0V.

Thereafter, the selection signal supply line SSL to which the gate electrode of the drain-side selection gate SG1A is connected is set at P5V.
To the power supply voltage V _CC . At this time, when the write data is “1”, since the drain / source / gate of the drain side select gate SG1A is all at the power supply voltage V _CC , the drain side select gate SG1A is cut off,
The channel is disconnected from the bit line BL1. When the write data is “0”, the drain side select gate SG1A
Is in a conductive state (ON state).

Here, when the unselected word line of the selected string is raised to Vpass and the selected word line is raised to Vpgm, the channel is separated from the bit line by the drain-side selection gate SG1A, and the channel voltage is boosted to the non-write voltage. .

The charge Q0 charged in the channel is
If the capacitance between the channel and the p-well at this time is Cch0, it is given by the following equation.

[0050]

Q0 = Cch0 · Vcc (4)

For the sake of simplicity, all word line voltages are set to Vp
ass. At this time, in the selected string, if the capacitance between the channel and the p-well is Cch, the charge charged in the capacitance Cch is Qch, and the charge charged in Cins is Qins, the following equation is established.

[0052]

−Qins + Qch = Q0 (−Cins · Vins + Cch · Vch = Cch0 · Vcc) (5)

[0053]

(6) Vins + Vch = Vpass (6)

The following equation is obtained from these two equations.

[0055]

Vch = {Cins / (Cins + Cch)} · Vpass + {Cch0 / (Cins + Cch) · Vcc} (7)

In equation (7), the first term is equivalent to equation (1), but the channel voltage is increased by the amount of the second term. And
Since Cch operates in the same manner as the varicap diode, when the channel voltage Vch increases, Cc in the equation (7) is obtained.
h becomes smaller than Cch of the equation (2), and as a result, (7)
The first term of the equation is also larger than the equation (1).

As described above, according to the present embodiment, a higher boost voltage than before can be obtained by the timing control, and the threshold voltage Vth of the drain-side selection gate can be set low. Is reduced, and as a result, the speed of the first access can be increased.

[0058]

As described above, according to the present invention,
There is an advantage that the self-boost can be reliably generated, the boost voltage becomes higher than before, and the disturbance resistance can be improved. Further, the threshold voltage of the drain-side selection gate can be set low, and the speed of the first access can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a timing chart for explaining a write operation according to the present invention.

FIG. 3 is a diagram for explaining an operation when data is written to a NAND flash memory by a self-boost operation.

FIG. 4A illustrates one memory transistor during a self-boost operation, and FIG. 4B is an equivalent circuit diagram thereof.

[Explanation of symbols]

10: nonvolatile semiconductor memory device, 11: memory array,
12 Write / read control circuit, NT1 to NT5 NMOS
Transistor, PT1 ... PMOS transistor, Q1 ...
Latch circuit.

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (10)

[Claims] A plurality of memory transistors for electrically writing and erasing data are connected, and one end and the other end are connected to a bit line and a ground via a selection transistor whose conduction state is controlled according to a gate voltage. The memory strings connected to the lines are arranged in a matrix,
A semiconductor non-volatile memory device in which control gates of memory cell transistors in the same row are connected to a common word line and data is written using self-boost. A second voltage higher than the first voltage is applied to the gate of the transistor, and the first voltage is applied to the word line to make the channel potential of the memory string the same as the bit line potential. A first voltage is applied to the gate of the connected selection transistor, and a second voltage is applied to the selected word line.
A non-volatile semiconductor memory device having control means for applying a third voltage higher than the voltage of the first voltage and applying an intermediate voltage between the third voltage and the first voltage to a non-selected word line. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said first voltage is substantially the same as a higher voltage applied to a bit line, and said intermediate voltage is a second voltage. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said first voltage is a power supply voltage, and said intermediate voltage is a second voltage. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said select transistor on the bit line side comprises an insulated gate field effect transistor, and a threshold voltage is set to a standard value. 5. The nonvolatile semiconductor memory device according to claim 2, wherein said selection transistor on the bit line side is an insulated gate field effect transistor, and a threshold voltage is set to a standard value. 6. The nonvolatile semiconductor memory device according to claim 1, wherein said memory string has a NAND string configuration in which a plurality of memory transistors are connected in series. 7. The nonvolatile semiconductor memory device according to claim 2, wherein said memory string has a NAND string configuration in which a plurality of memory transistors are connected in series. 8. The nonvolatile semiconductor memory device according to claim 4, wherein said memory string has a NAND string configuration in which a plurality of memory transistors are connected in series. 9. A plurality of memory transistors for electrically writing and erasing data are connected, and one end and the other end thereof are connected to a bit line and a ground via a selection transistor whose conduction state is controlled according to a gate voltage. The memory strings connected to the lines are arranged in a matrix,
A data write method for a semiconductor non-volatile memory device in which control gates of memory cell transistors in the same row are connected to a common word line and data is written using self-boost. After applying a second voltage higher than the first voltage to the gate of the connected selection transistor and applying the first voltage to the word line to make the channel potential of the memory string the same as the bit line potential, A first voltage is applied to the gate of a selection transistor connected to each bit line, a third voltage higher than the second voltage is applied to a selected word line, and a third voltage is applied to a non-selected word line. A data writing method for a nonvolatile semiconductor memory device, wherein a voltage intermediate between the first voltage and the first voltage is applied. 10. The first voltage is substantially the same as a higher voltage applied to a bit line, and the intermediate voltage is a second voltage.
The data writing method for a nonvolatile semiconductor memory device according to claim 9, wherein