JPH11242890A - Non-volatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device capable of simultaneously carrying out a write/erase operation and a read operation without increasing the chip area. SOLUTION: The device is provided with plural sets of sense amplifiers 33, 34; when a write/erase operation is not being performed, a read operation is carried out using all sense amplifiers; when the write/erase operation is being performed, the read operation is carried out using one set of sense amplifiers 33 or 34 in the plural sense amplifiers; and a verification operation at the time of write/erase is carried out using the sense amplifiers 34 or 33 that is not used for the read operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device such as a flash memory.

[0002]

2. Description of the Related Art As a conventional example of a nonvolatile semiconductor memory device, there is a nonvolatile semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. Hei 6-180999. FIG. 4 is a block diagram showing a configuration of the nonvolatile semiconductor memory device. This nonvolatile semiconductor memory device includes a flash array 41 and a flash array 42, and control / address / data (Control / Address / Da) for controlling these.
ta) a bus 43 and an input / output (I / O) bus 44.

A flash array 41 and a flash array 42 are respectively a flash EEPROM memory cell array (Memory-Cell Array) 45.
1 and 452, and each of the flash arrays 41 and 42 has its own row decoder (X-DEC) 461, 462 and column decoder (Y-D).
EC) 471, 472, sense amplifier (SENSE-A)
MP) 481, 482 and an output buffer (OUT-BU).
F) 491 and 492 are provided. Each of the flash arrays 41 and 42 shares another common peripheral circuit (not shown) in the flash EEPROM.

Each of the flash arrays 41 and 42 has a control / address / data (Control / Add).
An operation command of each array is input from a CPU (not shown) via a bus (res / Data) 43, and each array is independently controlled according to the operation command. That is, each of the flash arrays 41, 4
2, the read / write / erase operations are performed independently. Therefore, the CPU operates the flash array 41
During the write operation, the task that needs to access the information stored in the flash array 42 can be performed.

[0005]

However, in the conventional nonvolatile semiconductor memory device having the above configuration, a write / erase verify operation (when data in a flash cell is normally performed) required when writing or erasing a flash array is performed. Operation to confirm that writing / erasing has been performed),
Since it is possible to simultaneously perform the data read operation to the outside independently and simultaneously in each flash array, a separate sense amplifier is required in each of the flash arrays 41 and 42, and the chip area is disadvantageously increased. there were.

As a nonvolatile semiconductor memory device that can solve this problem, a nonvolatile semiconductor memory device having a configuration shown in FIG. 5 is generally known. This nonvolatile semiconductor memory device includes a flash array 51 and a flash array 52.
, A sense amplifier (SENSE-AMP) 55, an output buffer (OUT-BUF) 56, and control / address / data (Control / Address).
s / Data) bus 53 and input / output (I / O) bus 5
4. Each flash array 51 and 52
Are respectively configured to include flash EEPROM memory cell arrays (Memory-Cell Array) 571 and 572, and each of the flash arrays 51 and 52 has its own row decoder (X).
-DEC) 581, 582 and a column decoder (Y-D)
EC) 591 and 592 are provided. The read operation from the flash arrays 51 and 52 and the write / erase verify operation are performed by the sense amplifier (SENSE-AMP) 55 that is shared by each. In this nonvolatile semiconductor memory device, a sense amplifier (SENSE-
Since the two flash arrays 51 and 52 share the AMP 55, for example, when reading the contents of the flash array 52 during the writing / erasing operation of the flash array 51, the writing / erasing operation of the flash array 51 is temporarily performed. It is necessary to interrupt the read operation of the flash array 52.

In the nonvolatile semiconductor memory device having this configuration,
Although the chip area does not increase because the sense amplifiers are shared, when the read operation from the other flash array is performed during the write / erase operation of one flash array, the former write / erase operation is temporarily performed. There is a drawback that it is necessary to interrupt the operation and it takes time until the read operation can be executed.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and a nonvolatile semiconductor memory device capable of simultaneously executing a write / erase operation and a read operation without increasing the chip area. The purpose is to provide.

[0009]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device having a plurality of sense amplifiers, wherein a write / erase operation is not performed. A read operation is performed using all sense amplifiers, and when a write / erase operation is being performed, a read operation is performed using an arbitrary number of sense amplifiers of the plurality of sense amplifiers, and a read operation is performed. Write / read using unused sense amplifiers
A verify operation at the time of erasing is performed.

According to the nonvolatile semiconductor memory device of the present invention having the above configuration, the nonvolatile semiconductor memory device has a plurality of sense amplifiers, and uses all the sense amplifiers when the write / erase operation is not performed. When a write / erase operation is being performed, a read operation is performed using an arbitrary number of sense amplifiers of the plurality of sense amplifiers, and a sense amplifier not used for the read operation is used. , The write / erase verify operation is performed, so that even when the write / erase verify operation is being performed, the read operation can be performed at the same time. Further, since the sense amplifier can be shared by a plurality of flash arrays, an increase in chip size can be prevented.

As described above, according to the nonvolatile semiconductor memory device of the present invention, it is possible to execute the read operation at the same time as the write / erase operation without increasing the chip size.

According to a second aspect of the present invention, there is provided a non-volatile semiconductor memory device according to the present invention, wherein a first memory array, a second memory array, a plurality of sense amplifiers, and a first data array connected to the first memory array are provided. A second data line connected to the second memory array; a first selection circuit for decoding the first data line to transfer data to the plurality of sense amplifiers; and decoding the second data line. A second selection circuit for transferring data to the plurality of sense amplifiers, a data multiplexer, a plurality of data latch circuits, an address latch circuit for latching an externally input address, and an output signal from the address latch circuit. Address multiplexer for multiplexing an address inputted from the outside and an address inputted from the outside, and a data rewriting circuit. It is intended to.

Further, according to a third aspect of the present invention, in the nonvolatile semiconductor memory device according to the second aspect, the data rewriting operation of the first memory array is performed by the address latch circuit. The verification is performed using the stored address, and the first operation is performed using an arbitrary number of sense amplifiers of the plurality of sense amplifiers during the verify operation.
The data of the memory array is verified, and the data read operation of the second memory array during the data rewrite operation of the first memory array is performed using an externally input address. Data is read from the second memory cell using a sense amplifier not used for the verify operation of the first memory array, and the data rewrite operation of the second memory array uses the address stored in the address latch circuit. And verifying data in the second memory array using an arbitrary number of sense amplifiers of the plurality of sense amplifiers during a verify operation, and verifying the first memory during a data rewrite operation of the second memory array. The data read operation of the array is performed using an address input from the outside, and Among amplifier, it is characterized in that the reading data of the first memory array using a sense amplifier that is not used to verify operation of the second memory array.

Further, in the nonvolatile semiconductor memory device according to a fourth aspect, in the nonvolatile semiconductor memory device according to the second aspect, a read operation is performed when rewriting data in the first memory array or rewriting data in the second memory array. The read operation of the other memory array is performed by using an arbitrary number of sense amplifiers among the plurality of sense amplifiers, and data to be read at one time is time-divisionally divided into a plurality of times and sense-amplified. Data is transferred to the plurality of data latch circuits via the data multiplexer.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

This nonvolatile semiconductor memory device has a first flash array and a decoder (Array & dec).
order1) 11, a second flash array and decoder (Array & decoder2) 12, an address latch circuit (address-latch) 13, an address multiplexer (Mux.) 14, 15, and 1.
6, and a write / read circuit (sense & p
(program path) 17. The address latch circuit (address-latch) 13 latches a write / erase address (out-address) input from the outside in response to an address latch control signal AL. Address multiplexer (Mux.) 1
4, 15 and 16 are a first flash array and decoder (Array & decoder 1) 11 and a second flash array and decoder (Array & decoder 1).
decoder2) controls 12 addresses. Specifically, during the read operation, the latch address use signal (A
ASEL) goes low, and the externally input address (out-address) is replaced with the internal address (i).
ntadda, intaddb, and intaddc), and during a write / erase operation, the latch address use signal (AASEL) goes high, and the write / erase address (out-latch) latched by the address latch circuit (address-latch) 13. addres
s) to the internal address (intadda, intadd)
b, intaddc). Further, a block for executing a write / erase operation is selected by intaddc which is a block selection address. In the case of the embodiment of FIG. 1, if intaddc is at a high level, the first flash array and decoder (Array & de)
If the codec1) 11 is selected and intaddc is at the low level, the second flash array and decoder (Array & decoder2) 12 are selected. Addresses (o) input from the outside are supplied to the flash array and the decoder not selected at the time of the write / erase operation by the address multiplexer (Mux.).
out-address) is transferred. FIG. 6 shows a specific example of the address multiplexer (Mux.) Circuit.

FIG. 2 shows a write / read circuit (sen
A specific configuration example of “se & program path” 17 is shown. In the description of the nonvolatile semiconductor memory device of the present embodiment, the case of 8 bits is described for simplification, but it is needless to say that the present invention is not limited to 8 bits. This write / read circuit (s
ense & program path) 17 is a data writing circuit (program circuit)
21, data sense circuit (sense circuit)
t) 22, a data multiplexer (DMux.) 23,
And two data latch circuits 24 and 25 (lat
ch1 and latch2). In the figure, the first flash array and the decoder (Array) are shown.
& Decoder1) 11 and second flash array and decoder (Array & decoder2)
12 is also shown. The bit lines (not shown) of the memory cell array are connected via a decoder (not shown)
First flash array and decoder (Array &
decoder1) 11, the data line BLA
The second flash array and decoder (Array)
& Decoder2) 12 for the data line BL
B. Data writing circuit (progr
am circuit) 21 is the data line BLA or B depending on the state of the block selection address intaddc.
A write voltage is supplied to one of the LBs. The data sense circuit (sense circuit) 22 includes a first
Flash Array and Decoder (Array & d
The data of the memory cell in the second flash array and decoder (Array & decoder 2) 12 is read out via the data line BLA or BLB. The read data is output after being divided into a plurality of sense output lines (SENA, SENB).
In the description of the nonvolatile semiconductor memory device of the present embodiment, the case where the data is divided into two sets of 4 bits is described for simplicity, but the present invention is limited to the case of dividing the data into two sets of 4 bits. Needless to say, it is not a thing.
At the time of a read operation that is not during a write / erase operation, the sense output lines SENA and SENB output 4-bit low-side data and 4-bit high-side data, respectively, and the data is output to the outside. During a read operation during a write / erase operation, the sense output line SENA outputs four low-side bits when the high / low-side data selection signal (HLK) is low, and the first data latch circuit (latch).
1) 24 latches the low-side 4-bit data. Yes/
When the low-side data selection signal (HLK) is high, the sense output line SENA outputs four high-side bits. When the high / low side data selection signal (HLK) is high, the data multiplexer (DMux.) 23 outputs the sense output line SE.
The data of NA is stored in a second data latch circuit (latch).
2) Transfer to 25. During the write / erase operation, the sense output line SENB outputs verify data for the write / erase operation to a CPU (not shown).

FIG. 3 shows a data sense circuit (sense).
(Circuit) 22 is shown. This data sense circuit (sense circuit) 22
Two data line selection circuits 31 and 32 (selecto
r circuit), two sets of sense amplifiers 33 and 3
4 (SA1, SA2) and a sense amplifier / reference voltage generation circuit (reference circuit)
it) 35. Data line selection circuits 31 and 3
2 (selector circuit) includes four data transfer gates and a control circuit (control circuit) for controlling the transfer gates.
it) 36. A control circuit for controlling the transfer gate
Table 1 shows 36 truth tables.

[0020]

[Table 1]

The data sense circuit 22 based on the truth values shown in Table 1 will be described. At the time of a read operation not during writing / erasing, the first flash array and the decoder (Array & de)
When the data of (coder1) 11 is read, the block selection address intaddc goes high (E in the table is "1"). Since writing / erasing is not being performed, the latch address use signal (AASEL) goes low (F in the table is "0"). In this case, the bit line of the selected memory cell of the first flash array and decoder (Array & decoder 1) 11 is connected to the data line BLA. Control circuit for controlling the transfer gate (c
A control circuit (control ci) for controlling the transfer gate is provided by the control circuit (control circuit) 36.
The transfer gate connected to the output A and the transfer gate connected to the output D of the Rcuit 36 are opened.
A1) The high-side 4 bits of the data line BLA are
It is connected to a pair of sense amplifiers (SA2). At this time, the second flash array and decoder (Array)
& Decoder2) Data line BLB connected to 12
On the side, the block selection address intaddc goes low (E in the table is "0"). Since writing / erasing is not in progress, the latch address use signal (AASEL) also goes low (F in the table is "0"). In this case, a control circuit (control circuit) for controlling the transfer gate
The output A, B, C, and D of the control circuit 36 for controlling the transfer gate are all "0" by the control circuit 36, so that the data line BLB is connected to the sense amplifiers 33 and 34 (SA1 and SA).
Not connected to 2).

At the time of a read operation during writing / erasing,
First flash array and decoder (Array &
When the writing to the decoder 1) 11 is executed, the block selection address intaddc becomes high level (E in the table is “1”). Since writing / erasing is being performed, the latch address use signal (AASEL) becomes high level (F in the table is "1"). In this case, the first flash array and the decoder (Array & decode)
r1) The bit line of the selected memory cell 11 is connected to the data line BLA. A control circuit (control circuit) 36 for controlling the transfer gate controls the transfer gate (control circuit).
The transfer gate connected to the output B of the transfer circuit 36 or the transfer gate connected to the output D is opened. Control circuit for controlling the transfer gate (con
Whether the transfer gate connected to the output B of the control circuit 36 is opened or the transfer gate connected to the output D is opened is determined by the high / low side data selection signal (HL).
KA). High / low side data select signal (HL
KA) is controlled by a write control circuit (not shown) in a block where writing / erasing is performed. As for the data of the data line BLA, the low-side 4 bits and the high-side 4 bits are separately time-division-divided into the second set of sense amplifiers 34 (SA
Connected to 2). At this time, the second flash array and decoder (Array & decoder 2) 12
On the side of the data line BLB connected to, the block selection address intaddc goes low (E in the table indicates “
0 "). Since writing / erasing is in progress, the latch address use signal (AASEL) goes high (F in the table is"").
1 ″). In this case, a control circuit (control circuit) 36 that controls the transfer gate causes
A control circuit for controlling the transfer gate (contro
The transfer gate connected to the output A or C of (l circuit) 36 is opened. Whether the transfer gate connected to the output A of the control circuit 36 for controlling the transfer gate is opened or the transfer gate connected to the output C is opened depends on the high / low side data selection signal (HLKB). The high / low side data selection signal (HLKB) is controlled in synchronization with the high / low side data selection signal (HLK) unless it is a block where writing / erasing is performed. Data line BLB
In this data, four low-side bits and four high-side bits are separately and time-divisionally connected to the first set of sense amplifiers 33 (SA1). The high / low side data selection signals HLKA and H
LKB is a latch address use signal (AASEL),
This signal is generated by a logic circuit (not shown) using the high / low side data selection signal (HLK).

[0023]

According to the nonvolatile semiconductor memory device of the present invention described in detail above, in a nonvolatile semiconductor memory device having a plurality of sense amplifiers, when a write / erase operation is not executed, all sense signals are not sensed. A read operation is performed using an amplifier, and when a write / erase operation is performed, a read operation is performed using an arbitrary number of sense amplifiers of the plurality of sense amplifiers, and the read operation is performed. By performing a write / erase verify operation using a sense amplifier that does not have a chip area, a read operation can be performed at the same time even when a write / erase verify operation is being performed without increasing the chip area. .

Incidentally, Japanese Patent Application Laid-Open No. 5-54682 discloses that
A nonvolatile semiconductor memory having a configuration in which an erasing operation and a reading operation can be simultaneously performed on different blocks of a memory cell array is disclosed. ,
When an erase operation and an erase verify operation are performed consecutively to secure a sense amplifier for a read operation for a block that is not a target of the erase operation, a series of erase operations (especially, an erase verify operation) are temporarily stopped to perform data It is necessary to perform a read operation and then restart a series of erase operations. According to the nonvolatile semiconductor memory device of the present invention, such control is not required at all.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration example of a write / read circuit shown in FIG.

FIG. 3 is a block diagram showing a specific configuration example of a data sense circuit shown in FIG. 2;

FIG. 4 is a block diagram illustrating a configuration example of a conventional nonvolatile semiconductor memory device.

FIG. 5 is a block diagram showing a configuration example of another conventional nonvolatile semiconductor memory device.

FIG. 6 is a circuit diagram showing a specific configuration example of the address multiplexer shown in FIG. 1;

[Explanation of symbols]

11 First Flash Array and Decoder 12 Second Flash Array and Decoder 13 Address Latch Circuit 14, 15, 16 Address Multiplexer 17 Write / Read Circuit 21 Data Write Circuit 22 Data Sense Circuit 23 Data Multiplexer 24 First Data Latch Circuit 25 Second data latch circuit 31 First data line selection circuit 32 Second data line selection circuit 33 First set of sense amplifiers 34 Second set of sense amplifiers 35 Sense amplifier / reference voltage generation circuit 36 Transfer gate control circuit

Claims (4)

[Claims] 1. A nonvolatile semiconductor memory device having a plurality of sense amplifiers, wherein when a write / erase operation is not performed, a read operation is performed using all sense amplifiers, and the write / erase operation is performed. When the read operation is performed, a read operation is performed using an arbitrary number of the sense amplifiers, and a verify operation at the time of writing / erasing is performed using a sense amplifier not used for the read operation. A nonvolatile semiconductor memory device characterized by the above-mentioned. 2. A first memory array, a second memory array, a plurality of sense amplifiers, a first data line connected to the first memory array, and a second data line connected to the second memory array. Line, a first selection circuit for decoding the first data line and transferring data to the plurality of sense amplifiers, and a second selection circuit for decoding the second data line and transferring data to the plurality of sense amplifiers Circuit, a data multiplexer, a plurality of data latch circuits, an address latch circuit for latching an externally input address, and a plurality of multiplexes for multiplexing an address output from the address latch circuit and an externally input address. A nonvolatile semiconductor memory device comprising an address multiplexer and a data rewriting circuit. 3. The nonvolatile semiconductor memory device according to claim 2, wherein the data rewriting operation of said first memory array is performed using an address stored in said address latch circuit, and said plurality of data is written during a verify operation. The data of the first memory array is verified using an arbitrary number of sense amplifiers among the sense amplifiers, and the data read operation of the second memory array during the data rewrite operation of the first memory array is input from outside. Performing data read from the second memory cell using a sense amplifier that is not used for the verify operation of the first memory array among the plurality of sense amplifiers,
The data rewriting operation of the second memory array is performed using an address stored in the address latch circuit, and the verify operation uses an arbitrary number of sense amplifiers of the plurality of sense amplifiers. And the data read operation of the first memory array during the data rewrite operation of the second memory array is performed by using an externally input address. A non-volatile semiconductor storage device, wherein data is read from the first memory array using a sense amplifier not used for a verify operation of the memory array. 4. The non-volatile semiconductor memory device according to claim 2, wherein a read operation is performed at the time of rewriting data of said first memory array or at the time of rewriting data of said second memory array. , Using a given number of sense amplifiers out of the plurality of sense amplifiers, amplifying the data to be read at a time by dividing the data to be read in a plurality of times by time division, and transmitting the data to the plurality of data latch circuits. A nonvolatile semiconductor memory device, wherein the data is transferred via a multiplexer.