JPH11238727A - Plasma cvd system - Google Patents

Plasma cvd system

Info

Publication number
JPH11238727A
JPH11238727A JP3845198A JP3845198A JPH11238727A JP H11238727 A JPH11238727 A JP H11238727A JP 3845198 A JP3845198 A JP 3845198A JP 3845198 A JP3845198 A JP 3845198A JP H11238727 A JPH11238727 A JP H11238727A
Authority
JP
Japan
Prior art keywords
susceptor
plasma cvd
semiconductor wafer
substrate
cvd apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3845198A
Other languages
Japanese (ja)
Inventor
Hiroshi Iwata
博志 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP3845198A priority Critical patent/JPH11238727A/en
Publication of JPH11238727A publication Critical patent/JPH11238727A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To enhance the rate of operation, and reduce the man-hours required for maintenance work by providing a section for reinforcing the field of high frequency voltage discharge action on the surface of an electrode substrate for mounting a substrate to be processed contiguously on the outer fringe thereof. SOLUTION: This plasma CVD system comprises an electrode substrate (susceptor) for mounting a substrate to be processed, while serving as one electrode for generating plasma through capacity coupling. A disc-like susceptor 30 is provided with a central fixing hole 21. A plurality of small hole groups, each comprising a set of three small holes 23a, 23b and 23c, are provided on the periphery of the susceptor 30 in the region 22 for mounting a semiconductor wafer, for example. A section for enhancing the field of high frequency voltage discharge action, e.g. a groove 31 in the surface of the susceptor 30, is provided in a region which is contiguous to the outer fringe of the mounting region 22.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はプラズマCVD装置
に関し、さらに詳しくは、被処理基板を載置し、容量結
合型でプラズマを発生させる一方の電極ともなる電極基
板の構造に特徴を有するプラズマCVD装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma CVD apparatus, and more particularly, to a plasma CVD apparatus having a structure of an electrode substrate on which a substrate to be processed is mounted and which is one electrode for generating plasma in a capacitive coupling type. Related to the device.

【0002】[0002]

【従来の技術】近年、半導体装置の製造工程における導
電体膜、絶縁膜、ポリシリコン膜等の成膜装置として、
プラズマCVD装置が多用されている。このプラズマC
VD装置には、反応ガスのプラズマを発生させるための
電力供給方法の違い等による、容量結合型プラズマCV
D装置、誘導結合型プラズマCVD装置、マイクロ波プ
ラズマCVD装置、ECRプラズマCVD装置等があ
り、半導体ウェハ面内の成膜の膜質や膜厚の均一性、成
膜速度向上等を目指したプラズマCVD装置の検討がな
されている。
2. Description of the Related Art In recent years, as a film forming apparatus for forming a conductor film, an insulating film, a polysilicon film, etc. in a semiconductor device manufacturing process,
A plasma CVD apparatus is frequently used. This plasma C
The VD apparatus has a capacitively coupled plasma CV due to a difference in power supply method for generating a plasma of a reaction gas.
There are D equipment, inductively coupled plasma CVD equipment, microwave plasma CVD equipment, ECR plasma CVD equipment, etc., and plasma CVD aimed at improving film quality and film thickness uniformity, film formation speed, etc. on the surface of a semiconductor wafer. The device is being studied.

【0003】ここでは、従来の容量結合型プラズマCV
D装置の一つである平行平板型プラズマCVD装置の例
を、図5〜図7を参照して説明する。まず、平行平板型
プラズマCVD装置1は、図5に示すように、処理容器
である反応チャンバ2と、反応チャンバ2内の半導体ウ
ェハ10を載置するウェハ基板(サセプタ)3と、反応
チャンバ2内のサセプタ3に対向した状態に配置され、
反応ガスをプラズマ化するための高周波電極5が接続さ
れた上部電極4と、反応チャンバ2内に反応ガスを送り
込むガス配管6と、反応チャンバ2内の反応ガス等を排
気する排気管7等で概略構成されている。
Here, a conventional capacitively coupled plasma CV
An example of a parallel plate type plasma CVD apparatus which is one of apparatuses D will be described with reference to FIGS. First, as shown in FIG. 5, a parallel plate type plasma CVD apparatus 1 includes a reaction chamber 2 which is a processing container, a wafer substrate (susceptor) 3 on which a semiconductor wafer 10 in the reaction chamber 2 is mounted, and a reaction chamber 2. Is disposed facing the susceptor 3 in the
An upper electrode 4 to which a high-frequency electrode 5 for converting the reaction gas into plasma is connected, a gas pipe 6 for feeding the reaction gas into the reaction chamber 2, an exhaust pipe 7 for exhausting the reaction gas and the like in the reaction chamber 2, and the like. It is schematically configured.

【0004】サセプタ3は、円板状となっていて、円板
状の周辺部に複数枚の半導体ウェハ10を載置し、モー
タ等の駆動部と接続した回転軸8によりサセプタ3が回
転するようになっている。またサセプタ3は、接地され
ていて、上部電極4に対応する下部電極ともなってい
る。上部電極4の内部には、半導体ウェハ10を輻射熱
により加熱するための加熱ヒータ9が設けられている。
反応チャンバ2内のガス配管6の側壁には、反応チャン
バ2内に反応ガスを噴出させる小孔6aが複数個設けら
れていて、反応ガスがサセプタ3の中央に向け、サセプ
タ3に平行に噴出するようになっている。
The susceptor 3 has a disk shape. A plurality of semiconductor wafers 10 are mounted on a peripheral portion of the disk shape, and the susceptor 3 is rotated by a rotating shaft 8 connected to a driving unit such as a motor. It has become. The susceptor 3 is grounded and serves as a lower electrode corresponding to the upper electrode 4. A heater 9 for heating the semiconductor wafer 10 by radiant heat is provided inside the upper electrode 4.
On the side wall of the gas pipe 6 in the reaction chamber 2, a plurality of small holes 6 a for ejecting the reaction gas into the reaction chamber 2 are provided, and the reaction gas is ejected toward the center of the susceptor 3 in parallel with the susceptor 3. It is supposed to.

【0005】次に、円板状のサセプタ3の詳細構造を、
図6および図7を参照して説明する。ここで、図6
(a)はサセプタ3の概略平面図、図6(b)は図6
(a)のA−A部の概略断面図、図7は、図6(b)の
P部の拡大図で、サセプタ3に半導体ウェハ10を載置
した状態での図である。サセプタ3は、図6に示すよう
に、円板状となっており、この円板状のサセプタ3中央
には、回転軸8にサセプタ3を取り付けるための孔21
が設けられいて、サセプタ3周辺部には、複数の半導体
ウェハ10を載置する載置領域22に設けられた、3個
の小孔23a、23b、23cを一組とする複数の小孔
群が設けられている。
Next, the detailed structure of the disc-shaped susceptor 3 will be described.
This will be described with reference to FIGS. Here, FIG.
FIG. 6A is a schematic plan view of the susceptor 3, and FIG.
FIG. 7A is a schematic cross-sectional view of the AA part, and FIG. 7 is an enlarged view of the P part of FIG. 6B, in which the semiconductor wafer 10 is mounted on the susceptor 3. As shown in FIG. 6, the susceptor 3 has a disk shape, and a hole 21 for attaching the susceptor 3 to the rotating shaft 8 is formed in the center of the disk-shaped susceptor 3.
Is provided around the susceptor 3, and a plurality of small hole groups provided as a set of three small holes 23 a, 23 b, and 23 c provided in the mounting area 22 on which the plurality of semiconductor wafers 10 are mounted. Is provided.

【0006】上述した一組の小孔23a、23b、23
cは、半導体ウェハ10をサセプタ3に載置する際に、
図5に示すサセプタ3の下方に配置された半導体ウェハ
10の突き上げピン(図示省略)が挿入されるための小
孔である。突き上げピンは、半導体ウェハ10がウェハ
ハンドラ等によりサセプタ3に送られてきた時に、半導
体ウェハ10をサセプタ3表面より上方に突き出した突
き上げピンの先端で受け、その状態で突き上げピンが降
下して、半導体ウェハ10をサセプタ3の所定位置に載
置したり、成膜処理終了後に半導体ウェハ10をサセプ
タ3表面より上方に持ち上げた状態にして、半導体ウェ
ハ10をウェハハンドラに受け渡すものである。上述し
た半導体ウェハ10の載置領域22は、ウェハハンドラ
により突き上げピンの上方に搬送されてきた半導体ウェ
ハ10の位置で決まる領域である。
The above-described set of small holes 23a, 23b, 23
c, when placing the semiconductor wafer 10 on the susceptor 3,
These are small holes into which push-up pins (not shown) of the semiconductor wafer 10 arranged below the susceptor 3 shown in FIG. 5 are inserted. When the semiconductor wafer 10 is sent to the susceptor 3 by a wafer handler or the like, the push-up pins receive the semiconductor wafer 10 at the tips of the push-up pins projecting upward from the surface of the susceptor 3, and the push-up pins descend in that state. The semiconductor wafer 10 is placed at a predetermined position on the susceptor 3, or the semiconductor wafer 10 is lifted above the surface of the susceptor 3 after the film forming process is completed, and the semiconductor wafer 10 is transferred to a wafer handler. The mounting area 22 of the semiconductor wafer 10 described above is an area determined by the position of the semiconductor wafer 10 transferred above the push-up pins by the wafer handler.

【0007】ウェハハンドラ、突き上げピンおよびサセ
プタ3の回転方向の移動等の動作により、半導体ウェハ
10は小孔23a、23b、23cを一組とした、サセ
プタ3表面の複数の載置領域22に次々と載置される。
この半導体ウェハ10がサセプタ3上に載置領域22に
載置された状態の、図6(b)のP部の拡大図が図7で
ある。
[0007] By operations such as movement of the wafer handler, the push-up pins, and the susceptor 3 in the rotational direction, the semiconductor wafer 10 is successively formed in a plurality of mounting areas 22 on the surface of the susceptor 3 in which the small holes 23a, 23b, and 23c are set. Is placed.
FIG. 7 is an enlarged view of a portion P in FIG. 6B in a state where the semiconductor wafer 10 is mounted on the mounting area 22 on the susceptor 3.

【0008】次に、上述した平行平板型プラズマCVD
装置1を用いた、絶縁膜等を成膜する動作を説明する。
まず、サセプタ3の周辺部の載置領域22上に複数枚の
半導体ウェハ10を載置し、その後排気管7に接続する
排気系により、反応チャンバ2内を真空にする。その後
サセプタ3を駆動部により回転させながら、上部電極4
の加熱ヒータ9により半導体ウェハ10を加熱して所定
温度にする。その後、ガス配管6より反応チャンバ2内
に絶縁膜等を成膜するための反応ガス、例えば成膜する
絶縁膜をSiN膜とする時は、SiH4 ガスとNH3
スとの混合ガスを反応チャンバ2内に導入して、反応チ
ャンバ2内の反応ガスの圧力を所定圧力にした後、高周
波電源のパワーをONして、反応チャンバ2内にプラズ
マを発生させ、半導体ウェハ10上へSiN膜を堆積す
る。SiN膜の膜厚が所定膜厚となった段階で、高周波
電源のパワーをOFFしてプラズマを消滅させ、反応ガ
スの導入を停止して、反応チャンバ2内の反応ガスを排
気する。その後N2 ガス等を反応チャンバ2内に導入し
て、反応チャンバ2内の圧力を大気圧とした後、サセプ
タ3上の半導体ウェハ10を取り出す。
Next, the above-mentioned parallel plate type plasma CVD
An operation of forming an insulating film or the like using the apparatus 1 will be described.
First, a plurality of semiconductor wafers 10 are mounted on the mounting area 22 around the susceptor 3, and then the inside of the reaction chamber 2 is evacuated by an exhaust system connected to the exhaust pipe 7. Thereafter, while the susceptor 3 is rotated by the driving unit, the upper electrode 4
The semiconductor wafer 10 is heated to a predetermined temperature by the heater 9 described above. Thereafter, a reaction gas for forming an insulating film and the like in the reaction chamber 2 from the gas pipe 6, for example, when the insulating film to be formed is an SiN film, a mixed gas of SiH 4 gas and NH 3 gas is reacted. After being introduced into the chamber 2 and setting the pressure of the reaction gas in the reaction chamber 2 to a predetermined pressure, the power of the high-frequency power supply is turned on to generate plasma in the reaction chamber 2 and the SiN film on the semiconductor wafer 10. Is deposited. When the thickness of the SiN film reaches a predetermined thickness, the power of the high-frequency power supply is turned off to extinguish the plasma, the introduction of the reaction gas is stopped, and the reaction gas in the reaction chamber 2 is exhausted. Thereafter, N 2 gas or the like is introduced into the reaction chamber 2, the pressure in the reaction chamber 2 is set to the atmospheric pressure, and then the semiconductor wafer 10 on the susceptor 3 is taken out.

【0009】上述した平行平板型プラズマCVD装置1
により、半導体ウェハ10上に堆積したSiN膜は、当
初半導体ウェハ10面内でほぼ均一な膜厚となっている
が、上述したSiN膜のプラズマCVD作業を繰り返し
て行うと、半導体ウェハ10面内のSiN膜の膜厚は均
一性が悪くなり、図8に示すように、半導体ウェハ10
の中央より周辺に向かって膜厚が減少するような膜厚分
布となってくる。この様にSiN膜の膜厚分布が不均一
になると、このSiN膜を用いて作製される半導体装置
の特性に大きなばらつきを発生させる虞がある。そこ
で、膜厚の不均一性が大きくなる前の段階でプラズマC
VDの繰り返し作業を止め、サセプタ3上の載置領域2
2の外側に繰り返し堆積されることで蓄積した厚いSi
N膜をメカニカルクリーニングにより除去する、サセプ
タ3の保守作業を行う。この保守作業の頻度は高く、例
えば8回のプラズマCVD作業毎に、1回程度行う必要
があり、平行平板型プラズマCVD装置1の稼働率を低
下させ、また作業工数を増加させるという問題がある。
The above-mentioned parallel plate type plasma CVD apparatus 1
As a result, the SiN film deposited on the semiconductor wafer 10 initially has a substantially uniform thickness within the surface of the semiconductor wafer 10. However, if the above-described plasma CVD operation of the SiN film is repeatedly performed, The uniformity of the film thickness of the SiN film becomes worse, and as shown in FIG.
From the center toward the periphery. If the film thickness distribution of the SiN film becomes non-uniform in this way, there is a possibility that the characteristics of a semiconductor device manufactured using this SiN film will vary greatly. Therefore, before the non-uniformity of the film thickness becomes large, the plasma C
Stop the repetitive operation of VD, and place the mounting area 2 on the susceptor 3.
Thick Si accumulated by repeated deposition outside
The maintenance work of the susceptor 3 for removing the N film by mechanical cleaning is performed. The frequency of this maintenance work is high, for example, it is necessary to perform it about once every eight plasma CVD operations, which causes a problem that the operation rate of the parallel plate type plasma CVD apparatus 1 is reduced and the number of operation steps is increased. .

【0010】[0010]

【発明が解決しようとする課題】上記従来の平行平板型
プラズマCVD装置は、プラズマCVD作業回数の増加
と共に、半導体ウェハ上に堆積するSiN膜の、半導体
ウェハ面内の膜厚均一性が劣化するという問題があり、
この問題を回避するため、サセプタ上の載置領域の外側
に繰り返し堆積されることで蓄積した厚いSiN膜をメ
カニカルクリーニングして除去するという、サセプタの
保守作業を頻繁に行う必要があるので、プラズマCVD
装置の稼働率の低下と、作業工数の増加という問題があ
った。本発明は、上記事情を考慮してなされたものであ
り、その目的は、稼働率が良く、保守作業工数の少ない
プラズマCVD装置を提供することにある。
In the conventional parallel plate type plasma CVD apparatus described above, the uniformity of the thickness of the SiN film deposited on the semiconductor wafer within the semiconductor wafer surface is deteriorated as the number of plasma CVD operations is increased. There is a problem,
In order to avoid this problem, it is necessary to frequently perform a maintenance work on the susceptor, which is to mechanically clean and remove a thick SiN film accumulated by being repeatedly deposited outside the mounting area on the susceptor. CVD
There has been a problem that the operation rate of the device is reduced and the number of man-hours is increased. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a plasma CVD apparatus having a high operation rate and a small number of maintenance work steps.

【0011】[0011]

【課題を解決するための手段】本発明のプラズマCVD
装置は、上述の課題を解決するために提案するものであ
り、被処理基板を載置し、容量結合型でプラズマを発生
させる一方の電極にもなる電極基板を有するプラズマC
VD装置において、電極基板の被処理基板の載置面の、
被処理基板の載置領域外縁部に隣接して、高周波電圧に
よる放電作用の電界を強化する電界強化部を設けたこと
を特徴とするものである。
Means for Solving the Problems Plasma CVD of the present invention
The apparatus is proposed in order to solve the above-mentioned problem, and has a plasma C having an electrode substrate on which a substrate to be processed is mounted and which is also one electrode for generating plasma in a capacitive coupling type.
In the VD apparatus, the mounting surface of the substrate to be processed of the electrode substrate is
An electric field enhancing portion is provided adjacent to the outer edge of the mounting area of the substrate to be processed, for enhancing the electric field of the discharging action by the high frequency voltage.

【0012】本発明によれば、電極基板の被処理基板の
載置面の、被処理基板の載置領域外縁部に隣接して、高
周波電圧による放電作用の電界を強化する、溝部又は突
起部による電界強化部を設けることで、電界強化部の上
方の電界が強くなり、放電作用が大きくなるため、この
効果が、成膜作業回数の増加により被処理基板の載置領
域外に蓄積した厚い堆積膜のために、被処理基板の載置
領域外の電界の減少による放電作用減少を補うように働
き、被処理基板面内の成膜の膜厚均一性を多数回の成膜
作業後にも持続できる。従って、被処理基板面内の成膜
の膜厚均一性を維持するための、電極基板上に蓄積した
厚い堆積膜をメカニカルクリーニングで除去する電極基
板の保守作業を、従来のような頻度で行う必要がなくな
り、プラズマCVD装置の稼働率が向上し、保守作業工
数も大幅に低減できる。
According to the present invention, the groove or the protrusion for enhancing the electric field of the discharge action by the high-frequency voltage is provided on the mounting surface of the electrode substrate on which the substrate is to be processed, adjacent to the outer edge of the mounting area of the substrate to be processed. Since the electric field above the electric field enhancement part is strengthened and the discharge action is increased by providing the electric field enhancement part by this, this effect is increased due to an increase in the number of film forming operations, which is accumulated outside the mounting area of the substrate to be processed. The deposited film serves to compensate for the decrease in the discharge effect due to the decrease in the electric field outside the mounting area of the substrate to be processed, and to improve the uniformity of the film thickness within the surface of the substrate to be processed even after a large number of film forming operations. Can last. Therefore, in order to maintain the film thickness uniformity of the film formed on the surface of the substrate to be processed, the maintenance work of the electrode substrate for removing the thick deposited film accumulated on the electrode substrate by mechanical cleaning is performed as frequently as the conventional one. This eliminates the need, improves the operation rate of the plasma CVD apparatus, and can significantly reduce the number of maintenance work steps.

【0013】[0013]

【発明の実施の形態】以下、本発明の具体的実施の形態
例につき、添付図面を参照して説明する。なお従来技術
の説明で参照した図5〜図7中の構成部分と同様の構成
部分には、同一の参照符号を付すものとする。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings. The same components as those in FIGS. 5 to 7 referred to in the description of the related art are denoted by the same reference numerals.

【0014】実施の形態例1 本実施の形態例は、容量結合型プラズマCVD装置の一
つである平行平板型プラズマCVD装置に本発明を適用
した例であり、これを従来技術説明で用いた図5と、図
1および図2を参照して説明する。まず、本発明のプラ
ズマCVD装置の基本構成は、図5に示す従来例のプラ
ズマCVD装置1の構造と同様なので、同様な部分の説
明は省略し、本発明の特徴部分である、被処理基板を載
置し、容量結合型でプラズマを発生させる一方の電極に
もなる電極基板(サセプタ)に関して詳述する。
Embodiment 1 This embodiment is an example in which the present invention is applied to a parallel plate type plasma CVD apparatus which is one of capacitively coupled plasma CVD apparatuses, and this is used in the description of the prior art. This will be described with reference to FIG. 5, FIG. 1 and FIG. First, the basic configuration of the plasma CVD apparatus of the present invention is the same as that of the conventional plasma CVD apparatus 1 shown in FIG. And an electrode substrate (susceptor) which also serves as one electrode for generating plasma in a capacitive coupling type will be described in detail.

【0015】サセプタ30の構造は、例えば図1(a)
のサセプタ30の概略平面図、および図1(a)のB−
B部における概略断面図の図1(b)に示すように、円
板状となっており、この円板状のサセプタ30中央に
は、従来例と同様の回転軸8にサセプタ30を取り付け
るための孔21が設けられていて、サセプタ30周辺部
には、複数の被処理基板、例えば半導体ウェハ10を載
置する載置領域22に設けられた、3個の小孔23a、
23b、23cを一組とする複数の小孔群が設けられて
いる。載置領域22外縁部に隣接した領域には、高周波
電圧による放電作用の電界を強化する電界強化部、例え
ばサセプタ30表面に形成された溝部31が設けられて
いる。
The structure of the susceptor 30 is shown, for example, in FIG.
1 is a schematic plan view of the susceptor 30 shown in FIG.
As shown in FIG. 1B, which is a schematic cross-sectional view of a portion B, the susceptor 30 has a disk shape. In the peripheral portion of the susceptor 30, three small holes 23a provided in a mounting area 22 for mounting a plurality of substrates to be processed, for example, the semiconductor wafer 10,
A plurality of small hole groups each including 23b and 23c are provided. In a region adjacent to the outer edge of the mounting region 22, an electric field enhancing portion for enhancing an electric field of a discharge action by a high frequency voltage, for example, a groove 31 formed on the surface of the susceptor 30 is provided.

【0016】次に、上述した溝部31と半導体ウェハ1
0との位置関係を、図2を参照して説明する。ここで、
図2は半導体ウェハ10がサセプタ30に載置された状
態における、図1(b)のQ部の拡大図である。半導体
ウェハ10は、従来例と同様に、ウェハハンドラと3個
の小孔23a、23b、23cに対応して設けられてい
る突き上げピンの動作により、サセプタ30表面の載置
領域22に載置される。この半導体ウェハ10の載置領
域22外縁部に沿って溝部31が設けられている。半導
体ウェハ10のような円形状の被処理基板の場合の溝部
31は、図1(a)に示すように、円形状の半導体ウェ
ハ10の載置領域22の外側に位置する、円形状の構造
となる。
Next, the groove 31 and the semiconductor wafer 1
The positional relationship with 0 will be described with reference to FIG. here,
FIG. 2 is an enlarged view of a portion Q in FIG. 1B in a state where the semiconductor wafer 10 is mounted on the susceptor 30. The semiconductor wafer 10 is mounted on the mounting area 22 on the surface of the susceptor 30 by the operation of the wafer handler and the push-up pins provided corresponding to the three small holes 23a, 23b, 23c, as in the conventional example. You. A groove 31 is provided along the outer edge of the mounting area 22 of the semiconductor wafer 10. The groove 31 in the case of a circular substrate to be processed such as the semiconductor wafer 10 has a circular structure located outside the mounting region 22 of the circular semiconductor wafer 10 as shown in FIG. Becomes

【0017】上述した溝部31構造は、例えば半導体ウ
ェハ10の大きさが5インチ径の場合において、図2に
示すように、溝部31の幅Wを約10mm、溝部31の
深さDを約5mm、上面より見た円形状の溝部31の径
を、5インチ径の半導体ウェハ10の円形状の外縁部と
溝部31の内側側壁との距離Lが約1mmとなる径とす
る。
As shown in FIG. 2, for example, when the size of the semiconductor wafer 10 is 5 inches in diameter, the width W of the groove 31 is about 10 mm and the depth D of the groove 31 is about 5 mm. The diameter of the circular groove 31 viewed from the upper surface is a diameter at which the distance L between the circular outer edge of the 5-inch diameter semiconductor wafer 10 and the inner side wall of the groove 31 is about 1 mm.

【0018】次に、上記のサセプタ30を用いたプラズ
マCVD装置の動作について説明する。まず、従来例と
同様にして、サセプタ30の複数の半導体ウェハ10の
載置領域22に複数枚の半導体ウェハ10を載置し、そ
の後排気管7に接続する排気系により、反応チャンバ2
内を真空にする。その後サセプタ30を駆動部により回
転させながら、上部電極4の加熱ヒータ9により半導体
ウェハ10を所定温度に加熱する。その後、ガス配管6
より反応チャンバ2内に絶縁膜等を成膜するための反応
ガス、例えば成膜する絶縁膜をSiN膜とする時は、S
iH4 ガスとNH3 ガスとの混合ガスを反応チャンバ2
内に導入して、反応チャンバ2内の反応ガスの圧力を所
定の圧力にした後、高周波電源のパワーをONして、反
応チャンバ2内にプラズマを発生させ、半導体ウェハ1
0上へのSiN膜の堆積を開始する。SiN膜の膜厚が
所定膜厚となった段階で、高周波電源のパワーをOFF
してプラズマを消滅させ、反応ガスの導入を停止して、
反応チャンバ2内の反応ガスを排気する。その後N2
ス等を反応チャンバ2内に導入して、反応チャンバ2内
の圧力を大気圧とした後、サセプタ30上の半導体ウェ
ハ10を取り出す。
Next, the operation of the plasma CVD apparatus using the susceptor 30 will be described. First, in the same manner as in the conventional example, a plurality of semiconductor wafers 10 are mounted on the mounting area 22 of the plurality of semiconductor wafers 10 of the susceptor 30, and then the reaction chamber 2 is connected to the exhaust pipe 7 by an exhaust system.
Vacuum the inside. Thereafter, the semiconductor wafer 10 is heated to a predetermined temperature by the heater 9 of the upper electrode 4 while rotating the susceptor 30 by the driving unit. Then, the gas piping 6
A reaction gas for forming an insulating film or the like in the reaction chamber 2, for example, when the insulating film to be formed is an SiN film, S
Reaction gas mixture of iH 4 gas and NH 3 gas
After the pressure of the reaction gas in the reaction chamber 2 is set to a predetermined pressure, the power of the high-frequency power supply is turned on to generate plasma in the reaction chamber 2 and the semiconductor wafer 1.
The deposition of the SiN film on the substrate 0 is started. When the thickness of the SiN film reaches a predetermined thickness, the power of the high frequency power supply is turned off.
To extinguish the plasma, stop introducing the reaction gas,
The reaction gas in the reaction chamber 2 is exhausted. Thereafter, an N 2 gas or the like is introduced into the reaction chamber 2 to set the pressure in the reaction chamber 2 to atmospheric pressure, and then the semiconductor wafer 10 on the susceptor 30 is taken out.

【0019】上述したサセプタ30、即ち載置領域22
外縁部に隣接して溝部31を設けたサセプタ30を用い
たプラズマCVD装置においては、反応チャンバ2内
の、反応ガスであるSiH4 ガスとNH3 ガスとの混合
ガスに、高周波電源より電圧を印加して、上部電極4と
サセプタ30間にプラズマを発生させ、半導体ウェハ1
0上にSiN膜を堆積する際、図3に示すようなプラズ
マの密度分布、即ち半導体ウェハ10の外側に設けた溝
部31の上方にプラズマの密度の高い部分が発生する。
これは、平坦なサセプタ30表面に溝部31を設けたこ
とで、溝部31上部のコーナ31a、31bの電界が大
きくなり、この部分での放電作用が大きくなったことに
よるものである。
The above-described susceptor 30, that is, the mounting area 22
In the plasma CVD apparatus using the susceptor 30 provided with the groove 31 adjacent to the outer edge, a voltage is applied from a high frequency power supply to a mixed gas of a reaction gas, ie, a SiH 4 gas and an NH 3 gas, in the reaction chamber 2. To generate a plasma between the upper electrode 4 and the susceptor 30,
When the SiN film is deposited on the semiconductor wafer 10, a portion having a high plasma density is generated as shown in FIG. 3, that is, above the groove 31 provided outside the semiconductor wafer 10.
This is because the electric field in the corners 31a and 31b above the groove 31 is increased by providing the groove 31 on the surface of the flat susceptor 30, and the discharge action in this portion is increased.

【0020】この半導体ウェハ10の外側の溝部31上
方に密度の高いプラズマを発生させることで、SiN膜
のプラズマCVD作業を繰り返し行っても、図8に示す
従来例のSiN膜の膜厚分布、即ち半導体ウェハ10の
中央より周辺に向かって膜厚が減少するような膜厚分布
が発生し難くなる。この理由は、プラズマCVD装置に
よるSiN膜の堆積作業を繰り返すと、半導体ウェハ1
0の載置される載置領域外のサセプタ30表面には、S
iN膜の堆積作業の繰り返しにより、絶縁膜であるSi
N膜が厚く堆積して、従来例のサセプタ30においては
この厚いSiN膜がこの領域の電界を弱めて、放電作用
を小さくし、プラズマ密度減少を起こしたが、本発明の
サセプタ30を用いることで、上記のプラズマ密度減少
効果を補償する電界が、溝部31上部のコーナ31a、
31b部に発生することに起因すると推論される。
By generating a high-density plasma above the groove 31 outside the semiconductor wafer 10, even if the plasma CVD operation of the SiN film is repeated, the film thickness distribution of the conventional SiN film shown in FIG. That is, a film thickness distribution in which the film thickness decreases from the center to the periphery of the semiconductor wafer 10 is less likely to occur. The reason for this is that when the operation of depositing the SiN film by the plasma CVD apparatus is repeated, the semiconductor wafer 1
0 on the surface of the susceptor 30 outside the mounting area where the
By repeating the operation of depositing the iN film, the insulating film Si
The N film is deposited thickly, and in the conventional susceptor 30, the thick SiN film weakens the electric field in this region, reduces the discharge action, and reduces the plasma density. Thus, the electric field for compensating the above-mentioned plasma density decreasing effect is generated by the corners 31 a above the groove 31,
It is inferred that this is caused by the occurrence in the portion 31b.

【0021】上述したサセプタ30を用いたプラズマC
VD装置は、平坦性を維持したSiN膜の成膜作業を、
従来よりも多数回繰り返すことができるので、サセプタ
30の保守作業の頻度を少なくすることができ、プラズ
マCVD装置の稼働率の向上、および保守作業工数の大
幅な低減が可能となる。
The plasma C using the susceptor 30 described above
The VD apparatus performs a film forming operation of a SiN film while maintaining flatness,
Since it can be repeated many times as compared with the related art, the frequency of the maintenance work of the susceptor 30 can be reduced, and the operation rate of the plasma CVD apparatus can be improved and the number of maintenance work can be significantly reduced.

【0022】実施の形態例2 本実施の形態例は、容量結合型プラズマCVD装置の一
つである平行平板型プラズマCVD装置に本発明を適用
した例であり、これを従来技術説明で用いた図5と、図
4を参照して説明する。本発明のプラズマCVD装置の
基本的構造は、図5に示す従来例のプラズマCVD装置
1と同様なので、同様な部分の説明は省略し、本発明の
特徴であるサセプタの構造に関して詳述する。
Embodiment 2 This embodiment is an example in which the present invention is applied to a parallel plate type plasma CVD apparatus which is one of the capacitively coupled plasma CVD apparatuses, and is used in the description of the prior art. This will be described with reference to FIGS. Since the basic structure of the plasma CVD apparatus of the present invention is the same as that of the conventional plasma CVD apparatus 1 shown in FIG. 5, the description of the same parts will be omitted, and the structure of the susceptor which is a feature of the present invention will be described in detail.

【0023】本発明のサセプタ40は、電界強化部の形
状が実施の形態例1と異なるサセプタで、実施の形態例
1の図1(b)のQ部に対応する、半導体ウェハ10を
載置する載置領域近傍が図4の概略断面図のようになっ
ている。即ち、半導体ウェハ10を載置する載置領域外
縁部の外側のサセプタ40表面には、高周波電圧による
放電作用の電界を強化する電界強化部、例えば半導体ウ
ェハ10の載置領域の中心部を通る面での断面が円弧状
となる突起部41が設けられている。
The susceptor 40 of the present invention is a susceptor in which the shape of the electric field enhancing portion is different from that of the first embodiment, and mounts the semiconductor wafer 10 corresponding to the Q portion in FIG. 1B of the first embodiment. The vicinity of the mounting area is as shown in the schematic sectional view of FIG. That is, on the surface of the susceptor 40 outside the outer edge of the mounting area where the semiconductor wafer 10 is mounted, the electric field enhancer for enhancing the electric field of the discharge action by the high frequency voltage, for example, passes through the center of the mounting area of the semiconductor wafer 10. A projection 41 having a circular cross section in a plane is provided.

【0024】上述した突起部41構造は、例えば半導体
ウェハ10の大きさが5インチ径の場合において、図4
に示すように、半径Rが約6mmの円弧が、平坦なサセ
プタ40表面より約3mm程度突出した状態となってい
て、上面より見た円形状の突起部41の径を、5インチ
径の半導体ウェハ10の円形状の外縁部と突起部41の
内側端部との距離Lが約1mmの径となるようにする。
The structure of the above-described projection 41 is, for example, when the size of the semiconductor wafer 10 is 5 inches in diameter, as shown in FIG.
As shown in the figure, an arc having a radius R of about 6 mm protrudes about 3 mm from the surface of the flat susceptor 40, and the diameter of the circular protrusion 41 seen from the upper surface is set to 5 inches. The distance L between the circular outer edge of the wafer 10 and the inner end of the projection 41 is set to a diameter of about 1 mm.

【0025】上述したサセプタ40、即ち電界強化部で
ある突起部41を設けたサセプタ40を用いたプラズマ
CVD装置においては、反応チャンバ2内の、反応ガス
であるSiH4 ガスとNH3 ガスとの混合ガスに、高周
波電源より電力を印加して上部電極4とサセプタ40間
にプラズマを発生させ、半導体ウェハ10上にSiN膜
を堆積する際、実施の形態例1の図3に示すと同様なプ
ラズマの密度分布、即ち半導体ウェハ10の外側に設け
た突起部41の上方にプラズマの密度の高い部分が発生
する。これは、平坦なサセプタ40表面に上記のような
突起部41を設けると、この突起部41の上方の電界が
大きくなり、この部分での放電作用が大きくなることに
よるものである。
In the above-described plasma CVD apparatus using the susceptor 40, that is, the susceptor 40 provided with the projection 41 as the electric field enhancing portion, the reaction gas in the reaction chamber 2 is made of the SiH 4 gas and the NH 3 gas. When a plasma is generated between the upper electrode 4 and the susceptor 40 by applying power from a high frequency power supply to the mixed gas to deposit a SiN film on the semiconductor wafer 10, the same as that shown in FIG. A portion having a high plasma density is generated above the plasma density distribution, that is, above the protrusion 41 provided outside the semiconductor wafer 10. This is because when the above-described protrusion 41 is provided on the flat susceptor 40 surface, the electric field above the protrusion 41 increases, and the discharge action in this portion increases.

【0026】この半導体ウェハ10の外側の突起部41
上方の密度の高いプラズマを発生させることで、実施の
形態例1と同様に、SiN膜のプラズマCVD作業を繰
り返しおこなっても、図8に示す従来例の膜厚分布、即
ち半導体ウェハ10の中央より周辺に向かって膜厚が減
少するような膜厚分布が発生し難くなる。
Projection 41 outside semiconductor wafer 10
By generating a high-density plasma on the upper side, even if the plasma CVD operation of the SiN film is repeated as in the first embodiment, the film thickness distribution of the conventional example shown in FIG. A film thickness distribution such that the film thickness decreases toward the periphery hardly occurs.

【0027】従って、このサセプタ40を用いたプラズ
マCVD装置は、実施の形態例1と同様に、平坦性を維
持したSiN膜の成膜作業を、従来よりも多数回繰り返
すことができるので、サセプタ40の保守作業の頻度を
少なくすることができ、プラズマCVD装置の稼働率の
向上、および保守作業工数の大幅な低減が可能となる。
Therefore, the plasma CVD apparatus using the susceptor 40 can repeat the operation of forming the SiN film while maintaining the flatness many times more than in the prior art, as in the first embodiment. It is possible to reduce the frequency of the maintenance work of 40, improve the operation rate of the plasma CVD apparatus, and significantly reduce the number of maintenance work steps.

【0028】以上、本発明を2例の実施の形態例により
説明したが、本発明はこれらの実施の形態例に何ら限定
されるものではない。例えば、本発明の実施の形態例で
は、本発明を多数枚の半導体ウェハ上に同時に成膜す
る、所謂バッチ式の平行平板型プラズマCVD装置によ
り説明したが、一枚づつの半導体ウェハに成膜する、所
謂枚葉式の平行平板型プラズマCVD装置に適用しても
よい。また、本発明の実施の形態例では、容量結合型プ
ラズマCVD装置を平行平板型プラズマCVD装置によ
り説明したが、多極石英管型プラズマCVD装置や、同
軸円筒型プラズマCVD装置等に適用してもよい。
Although the present invention has been described with reference to the two embodiments, the present invention is not limited to these embodiments. For example, in the embodiments of the present invention, the present invention has been described with a so-called batch-type parallel plate type plasma CVD apparatus in which films are formed on a large number of semiconductor wafers at the same time. The present invention may be applied to a so-called single-wafer parallel plate type plasma CVD apparatus. In the embodiment of the present invention, the capacitively coupled plasma CVD apparatus is described as a parallel plate plasma CVD apparatus. However, the present invention is applied to a multipolar quartz tube plasma CVD apparatus, a coaxial cylindrical plasma CVD apparatus, and the like. Is also good.

【0029】更に、本発明の実施の形態例1では、サセ
プタの半導体ウェハの載置領域の外側に設ける電界強化
部の断面を矩形状の溝部として説明したが、断面が半円
形状や三角形状等となる溝部であってもよい。また、本
発明の実施の形態例2では、サセプタの半導体ウェハの
載置領域の外側に設ける電界強化部の断面を円弧形状の
突起部として説明したが、断面が三角形状や矩形状等と
なる突起部であってもよい。
Further, in the first embodiment of the present invention, the cross section of the electric field enhancing portion provided outside the semiconductor wafer mounting area of the susceptor is described as a rectangular groove, but the cross section is semicircular or triangular. It may be a groove part which becomes the same. Further, in the second embodiment of the present invention, the cross section of the electric field enhancing portion provided outside the mounting region of the semiconductor wafer of the susceptor has been described as an arc-shaped projection, but the cross section has a triangular shape, a rectangular shape, or the like. It may be a projection.

【0030】[0030]

【発明の効果】以上の説明から明らかなように、本発明
の容量結合型のプラズマCVD装置は、被処理基板を載
置し、高周波電力を印加する一方の電極にもなる電極基
板(サセプタ)表面の、被処理基板の載置領域外縁部に
隣接して、高周波電圧による放電作用の電界を強化す
る、溝部又は突起部による電界強化部を設けることで、
電界強化部の上方の電界が強くなり、放電作用が大きく
なるため、この効果が成膜作業回数の増加により被処理
基板の載置領域外に蓄積した厚い堆積膜のために、被処
理基板の載置領域外の電界の減少による放電作用減少を
補うように働き、被処理基板面内の成膜の膜厚均一性を
多数回の成膜作業後にも持続できる。従って、被処理基
板面内の成膜の膜厚均一性を維持するための、電極基板
上に蓄積した厚い堆積膜をメカニカルクリーニングで除
去する電極基板の保守作業を、従来のような頻度で行う
必要がなくなり、プラズマCVD装置の稼働率が向上
し、保守作業工数も大幅に低減できる。
As is apparent from the above description, in the capacitively coupled plasma CVD apparatus of the present invention, an electrode substrate (susceptor) on which a substrate to be processed is placed and which serves as one electrode to which high-frequency power is applied. On the surface, adjacent to the outer edge of the mounting area of the substrate to be processed, to enhance the electric field of the discharge action by the high-frequency voltage, by providing an electric field enhancing portion by a groove or a protrusion,
Since the electric field above the electric field enhancement part is strengthened and the discharge action is increased, this effect is caused by a thick deposited film accumulated outside the mounting area of the target substrate due to an increase in the number of film forming operations. It works so as to compensate for the decrease in the discharge action due to the decrease in the electric field outside the mounting region, and can maintain the uniformity of the film thickness in the surface of the substrate to be processed even after a number of film forming operations. Therefore, in order to maintain the film thickness uniformity of the film formed on the surface of the substrate to be processed, the maintenance work of the electrode substrate for removing the thick deposited film accumulated on the electrode substrate by mechanical cleaning is performed as frequently as the conventional one. This eliminates the need, improves the operation rate of the plasma CVD apparatus, and can significantly reduce the number of maintenance work steps.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態例1のサセプタの概略図
で、(a)は概略平面図、(b)は概略断面図である。
FIG. 1 is a schematic diagram of a susceptor according to a first embodiment of the present invention, wherein (a) is a schematic plan view and (b) is a schematic sectional view.

【図2】図1(b)のQ部に半導体ウェハを載置した状
態における、Q部の拡大図である。
FIG. 2 is an enlarged view of a portion Q in a state where a semiconductor wafer is mounted on the portion Q of FIG. 1B.

【図3】本発明の実施の形態例1のサセプタを用いたプ
ラズマCVD装置のプラズマ発生時のプラズマ密度分布
を説明する図で、サセプタの半導体ウェハの載置領域近
傍の概略断面図である。
FIG. 3 is a diagram for explaining a plasma density distribution when plasma is generated in a plasma CVD apparatus using the susceptor according to the first embodiment of the present invention, and is a schematic cross-sectional view near a mounting region of a semiconductor wafer of the susceptor.

【図4】本発明の実施の形態例2のサセプタの、半導体
ウェハの載置領域近傍の概略断面図である。
FIG. 4 is a schematic sectional view of a susceptor according to a second embodiment of the present invention in the vicinity of a mounting region of a semiconductor wafer;

【図5】従来のプラズマCVD装置の概略断面図であ
る。
FIG. 5 is a schematic sectional view of a conventional plasma CVD apparatus.

【図6】従来のプラズマCVD装置のサセプタの概略図
で、(a)は概略平面図、(b)は概略断面図である。
6A and 6B are schematic views of a susceptor of a conventional plasma CVD apparatus, wherein FIG. 6A is a schematic plan view and FIG. 6B is a schematic sectional view.

【図7】図6(b)のP部に半導体ウェハを載置した状
態における、P部の拡大図である。
FIG. 7 is an enlarged view of the P portion in a state where a semiconductor wafer is mounted on the P portion of FIG. 6B.

【図8】従来のプラズマCVD装置による複数回の成膜
作業後に、半導体ウェハ上に堆積されるSiN膜の膜厚
分布図である。
FIG. 8 is a diagram illustrating a film thickness distribution of a SiN film deposited on a semiconductor wafer after a plurality of film forming operations performed by a conventional plasma CVD apparatus.

【符号の説明】[Explanation of symbols]

1…平行平板型プラズマCVD装置、2…反応チャン
バ、3,30,40…サセプタ、4…上部電極、5…高
周波電源、6…ガス配管、6a,23a,23b,23
c…小孔、7…排気管、8…回転軸、9…加熱ヒータ、
10…半導体ウェハ、21…孔、22…載置領域、31
…溝部、41…突起部
DESCRIPTION OF SYMBOLS 1 ... Parallel plate type plasma CVD apparatus, 2 ... Reaction chamber, 3, 30, 40 ... Susceptor, 4 ... Upper electrode, 5 ... High frequency power supply, 6 ... Gas piping, 6a, 23a, 23b, 23
c: small hole, 7: exhaust pipe, 8: rotating shaft, 9: heater
10: semiconductor wafer, 21: hole, 22: mounting area, 31
... groove, 41 ... projection

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 被処理基板を載置し、容量結合型でプラ
ズマを発生させる一方の電極にもなる電極基板を有する
プラズマCVD装置において、 前記電極基板の前記被処理基板の載置面の、前記被処理
基板の載置領域外縁部に隣接して、高周波電圧による放
電作用の電界を強化する電界強化部を設けたことを特徴
とするプラズマCVD装置。
1. A plasma CVD apparatus having an electrode substrate on which a substrate to be processed is placed and which also serves as one electrode for generating plasma in a capacitive coupling type, wherein: A plasma CVD apparatus, further comprising: an electric field enhancing section provided adjacent to an outer edge of the mounting area of the substrate to be processed, for enhancing an electric field of a discharging action by a high-frequency voltage.
【請求項2】 前記電界強化部は、前記電極基板の平坦
面に形成された溝部であることを特徴とする、請求項1
に記載のプラズマCVD装置。
2. The device according to claim 1, wherein the electric field enhancing portion is a groove formed on a flat surface of the electrode substrate.
3. The plasma CVD apparatus according to 1.
【請求項3】 前記電界強化部は、前記電極基板の平坦
面に形成された突起部であることを特徴とする、請求項
1に記載のプラズマCVD装置。
3. The plasma CVD apparatus according to claim 1, wherein the electric field enhancing portion is a protrusion formed on a flat surface of the electrode substrate.
JP3845198A 1998-02-20 1998-02-20 Plasma cvd system Pending JPH11238727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3845198A JPH11238727A (en) 1998-02-20 1998-02-20 Plasma cvd system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3845198A JPH11238727A (en) 1998-02-20 1998-02-20 Plasma cvd system

Publications (1)

Publication Number Publication Date
JPH11238727A true JPH11238727A (en) 1999-08-31

Family

ID=12525657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3845198A Pending JPH11238727A (en) 1998-02-20 1998-02-20 Plasma cvd system

Country Status (1)

Country Link
JP (1) JPH11238727A (en)

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