JPH11238004A - System simulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system simulator constructing a simulation environment on a frame work. SOLUTION: A system simulator 1 is provided with a CPU simulator 3 simulating target CPU, an input/output I/O simulator 4 simulating a target input/ output device and a frame work 5 connecting the CPU simulator 3 and the input/output I/O simulator 4 with object communication are provided. A simulation environment which can execute a target program 2 by a host CPU system can be constructed on the frame work 5 directing the object by transferring respective instruction codes with object communication. The environment of the development of firmware and the development of the CPU system can be improved, firmware and the CPU system can easily and speedily be developed. Then, speedy development can be executed in the CPU system of the different input/output device with the free combination of the objects.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a system simulator, and more particularly, to a system simulator for constructing a simulation environment on a framework.

[0002]

2. Description of the Related Art In developing a CPU system including a processor such as a CPU (Central Processing Unit) and a DSP (Digital Signal Processor) and a program for the CPU system, an actual CPU system (hereinafter, referred to as a CPU system) will be described.
It is called a target CPU system. Before completion of the target CPU system, a program developed for the target CPU system (hereinafter, referred to as a target program) is transferred to a target CPU system by a different CPU system (hereinafter, referred to as a host CPU system) from the target CPU system. 2. Description of the Related Art Debugging and performance evaluation are performed using a simulator that operates simulated.

[0003] As such a simulator, conventionally,
For example, a CPU simulator capable of re-executing a target program from the same point even if the state information stored in the file is reduced (see Japanese Patent Application Laid-Open No. HEI 8-185341), interpreting machine language-level instruction codes of the target program, A CPU simulation method and a CPU simulator that speed up the simulation by converting the instruction code of the host CPU into instruction codes at a previous stage so as to eliminate the need to interpret a machine language level instruction of the target program at the time of executing the simulation (Japanese Patent Laid-Open Publication No. 6-2
Japanese Patent Application Laid-Open No. 7-281925), a plurality of simulators are independently operated on a workstation to simultaneously simulate processing of a single CPU and simulation of communication processing between CPUs. ) And a simulation system that simulates the operation of a plurality of CPUs in parallel and also simulates the operation of each CPU (see Japanese Patent Application Laid-Open No. 5-35534).

That is, each of the above simulators simulates a target CPU and an input / output device like a simulator of a target machine, but performs a target machine language translation process and a target program.
They are managed separately, and like a CPU simulator, a target CPU simulator, a target machine language translation process, and a target program are separately managed.

[0005]

However, such a conventional simulator does not have a target CPU.
Since the system, target machine language translation processing, and target program are managed separately, CPU and DSP
It takes time to develop the CPU system including the I / O device and the input / output device.
It was necessary to develop a U-dedicated simulator, and there was a need for improvement in rapid development.

Therefore, the first aspect of the present invention is to construct a simulation environment in which a target program can be executed by a host CPU system on an object-oriented framework by exchanging each instruction code by object communication. , Firmware development and CP
Improving the development environment of the U system, enabling simple and quick development of firmware and CPU systems, and rapid development of CPU systems of different input / output devices by freely combining objects. The purpose of the present invention is to provide a system simulator capable of performing such operations.

According to a second aspect of the present invention, a system simulator connects a CPU simulator that simulates a target CPU, an I / O simulator that simulates a target input / output device, and a CPU simulator and an I / O simulator by object communication. It is an object of the present invention to provide a system simulator capable of rapidly developing even a CPU system having an input / output device by including a framework processing means.

According to a third aspect of the present invention, a system simulator includes a plurality of system simulators for simulating a plurality of target CPU systems, a plurality of system simulators, and a frame for defining a relationship between the plurality of system simulators. And a work processing means, whereby a plurality of system simulators are operated in cooperation to appropriately simulate, and a target CPU system composed of a plurality of CPU systems is simply and quickly developed. It is an object of the present invention to provide a system simulator capable of performing such operations.

According to a fourth aspect of the present invention, a target CPU
Each instruction code at the machine language level of the target program in which each instruction code at the machine language level of the system is incorporated in the language of the framework is translated by a source code simulator and simulated. When a target program is created by incorporating the assembler code of the above into the language of the framework (for example, C ++ language), if the language of the framework is, for example, C ++ language, C ++
It is an object of the present invention to provide a system simulator that can easily and quickly develop a simulator without having to develop a dedicated simulator using a debugger or the like attached to the language.

[0010]

According to a first aspect of the present invention, a system simulator simulates, on a host CPU system, each instruction code at a machine language level of a target program for a target CPU system to be simulated. A system simulator for simulating the operation of the target CPU system on the host CPU system, by transmitting and receiving the instruction codes by object communication in a simulation environment in which the target program can be executed by the host CPU system. The above object is achieved by building on an object-oriented framework.

According to the above configuration, the simulation environment in which the target program can be executed by the host CPU system is constructed on the object-oriented framework by transmitting and receiving each instruction code by object communication. It is possible to improve the environment for development of CPUs and CPU systems, to enable simple and quick development of firmware and CPU systems, and to use different input / output device CPUs by freely combining objects. Rapid development can also be performed on the system.

In this case, for example, as described in claim 2, the system simulator includes the target C
The system may include a CPU simulator for simulating a PU, an I / O simulator for simulating a target input / output device, and framework processing means for connecting the CPU simulator and the I / O simulator by the object communication.

According to the above configuration, the system simulator is a CPU simulator that simulates a target CPU, an I / O simulator that simulates a target input / output device, and a framework that connects the CPU simulator and the I / O simulator by object communication. Processing means;
, A CP with an input / output device
Rapid development can also be performed on U systems.

Further, for example, as set forth in claim 3, the system simulator includes a plurality of system simulators simulating a plurality of the target CPU systems, the plurality of system simulators being activated, and the plurality of system simulators. Framework processing means for defining a relationship between simulators.

According to the above configuration, the system simulator includes a plurality of system simulators for simulating a plurality of target CPU systems, a framework processing for activating the plurality of system simulators and defining a relationship between the plurality of system simulators. Means, a plurality of system simulators can be operated in cooperation with each other to appropriately simulate, and a target CP composed of a plurality of CPU systems can be provided.
U systems can be developed simply and quickly.

Further, for example, as set forth in claim 4, the target program includes the target CP.
Each instruction code at the machine language level of the U system is incorporated in the language of the framework, and the system simulator includes a source code simulator that translates each instruction code at the machine language level of the target program. The instruction code translated by the simulator may be interpreted and simulated.

According to the above arrangement, each instruction code at the machine language level of the target program in which each instruction code at the machine language level of the target CPU system is incorporated in the language of the framework is translated by the source code simulator. Since the simulation is performed, for example, a target program can be created by incorporating assembler code of a target CPU system into a language of a framework (for example, C ++ language). As a language of the framework, for example, C ++ If you use a language, C
The simulator can be easily and quickly developed without the need to develop a dedicated simulator using a debugger or the like attached to the ++ language.

[0018]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. It should be noted that the embodiments described below are preferred embodiments of the present invention, and therefore, various technically preferable limitations are added. However, the scope of the present invention is not limited to the following description. The embodiments are not limited to these embodiments unless otherwise specified.

FIGS. 1 to 4 show a first embodiment of the system simulator of the present invention. FIG. 1 shows a system simulator 1 to which the first embodiment of the system simulator of the present invention is applied. FIG.

In FIG. 1, a system simulator 1
Builds a simulation environment on an object-oriented framework.

That is, the system simulator 1 includes a target program 2, a CPU simulator 3, an input / output I / O simulator 4, a framework 5, and the like.
(Central Processing Unit) or target DS
P (Digital Signal Processor) (hereinafter collectively referred to as a target CPU), an input / output device to be simulated (hereinafter referred to as a target input / output I / O), and a simulation connected to the target input / output I / O The operation of a target program 2 (hereinafter, simply referred to as a target program) created for a CPU system (hereinafter, referred to as a target CPU system) including a target peripheral device (hereinafter, a target peripheral device) is referred to as a target. The simulation is performed on a CPU system (hereinafter, referred to as a host CPU system) such as a CPU, a DSP, an input / output device, and peripheral devices different from the CPU system.

In object-oriented system development, a core simulator (CPU simulator) for simulating a target CPU, an I / O simulator for simulating target I / O, and target peripheral devices connected to the target I / O are generally simulated. The EXT simulator and the target assembler source code are divided into units called classes. This class is a module that summarizes data and operations on it.
Operations are called methods, and attributes are called methods.

Hierarchical relations can be defined between classes. A class higher in the hierarchy is called a superclass, and a lower class is called a subclass. Subclass methods inherit from superclass methods. For example, there is a class B as a subclass of the class A, and methods a1 and a2 are defined as methods defined in the class A.
There is a method b1 in the method defined in class B.
If there is, the methods of class B are methods a1, a2, and b1. Here, for example, class B
Defines a method a2 having the same name as the method of the class A, in the class B, the method a2 defined in the class B is used.

An object-oriented framework is a set of interoperable classes that derive a reusable program.

In general, a CPU or a DSP acquires a program from an address set in a program counter, translates the acquired program, and executes the processing of the program.
Processing is performed by changing the processing content according to an external factor (for example, an interrupt or the like).

The system simulator 1 performs this series of operations by providing an environment in which the series of operations is replaced with the generation and reception of an event by the framework 5.

That is, in the system simulator 1,
All objects such as the target program 2, the CPU simulator 3, and the input / output I / O simulator 4 are registered in the framework 5, and communication between the objects is performed to simulate the target program 2.

For this purpose, the framework 5 includes a superclass of the CPU simulator 3 that abstracts a module that simulates each instruction code at a machine language level of the target CPU system, a superclass of assembler translation, and an abstracted input / output simulator. Provides 3 superclasses.

The superclass of the framework 5 has functions of object management and event transmission and event reception in order to realize a wide range of system simulation. A function of registering any object such as an output simulator and communication between objects can be realized.

Then, the target program 2, the CPU
Each object of the simulator 3 and the input / output I / O simulator 4 is connected to the framework 5 by a message path 6, and the message path 6 is connected to the input / output I / O
When the simulator 4 is an object having a function of a serial port, the simulator 4 transmits and receives a serial port input / output message and a serial port control message.

The system simulator 1 realizes this inter-object communication by constructing a network between applications.

The system simulator 1 realizes a flexible configuration by registering transmission / reception of events of each object in the framework 5.

The registration procedure when registering this object in the framework 5 is performed as shown in FIG. That is, the object acquires the handle number that is its own destination (step S1), and notifies the framework 5 of the types of receivable messages using the acquired handle number (step S2). Next, the object notifies the framework 5 of the type of message that can be transmitted (step S3), and then notifies the framework 5 of the method and type that can be activated (step S3).
4).

On the other hand, the framework 5 has a function of connecting to a partner corresponding to the type of message, and connects to a partner corresponding to the type of message from the object to accept registration of an object.

That is, the system simulator 1 realizes a simulation by constructing an environment on the framework 5 in which a series of operations is replaced by generation and reception of an event in the host CPU. Then, as described above, the host CPU acquires the program from the address set in the program counter as its basic operation,
This is executed after program translation, but the processing contents of this basic operation are changed by an external factor (such as an interrupt).

In the system simulator 1, the event management class of the framework 5 manages the occurrence of an event as an event object, and the event issuing component can also explicitly describe the event receiving component. It is also possible to define an event management class for managing an event receiving component. Since the system simulator 1 adopts such an event management method, it can be defined as a general-purpose class, and has a function of hooking an event when implementing or evaluating hardware simulation. Can be realized.

As described above, the system simulator 1 uses the framework 5 for superclass and assembler translation of the CPU simulator 3 in which the framework 5 abstracts a module for simulating each instruction code at the machine language level of the target CPU system. Since the super class is provided, the target program 2
Each instruction code at the machine language level of the U system can be described in a state of being incorporated in the language of the framework. For example, if the target program 2 is described in C ++ language and each instruction code at the machine language level of the target CPU system is in assembler language, as shown in FIG. 3, the target program 2 described in C ++ language is used. Of the target CPU as a character string in the factor of dsp ()
It is created by describing each instruction code at the machine language level of the system in assembler language.

The framework 5 translates the assembler code character string of the target program 2 into a machine language and then transfers it to the CPU simulator 3, which then simulates the instruction.

Although the jump instruction and the subroutine call instruction at the machine language level are strictly different from the goto statement and the function used in the C ++ language, the jump instruction in the machine language is a program instruction. A command to be set in a counter (hereinafter, referred to as a PC as necessary), and a CALL instruction merely performs an operation of saving a next address to be processed on the stack before the CALL instruction. Therefore, it is not possible to realize all assembler instruction descriptions within the grammar of the C ++ language. However, even when developing assembler code, an exceptional PC operation is required to improve readability. Is not implemented, so that there is no practical problem. As a result, grammar constraints,
For example, except for jumping out of a subroutine, use the following method to incorporate each instruction code of the assembler language, which is the machine language level of the target CPU system, into the C ++ language, which is the framework language. Can be.

That is, in assembler, when describing assembler code, it is general to describe using a pseudo instruction. The pseudo instruction has a function of replacing a numerical value as a label character string, and a PC jump. In the instruction and the subroutine call instruction, the address of the jump destination is not described by a numerical value but by a label name corresponding to the address.

For example, in the above-mentioned C ++ macro, when a jump destination is described by a label, the label of the jump destination is registered in advance, so that the goto in the C ++ language is registered.
It can be replaced by a statement or a function.

In the indirect jump instruction peculiar to the assembler, the jump destination can be replaced in advance by replacing the jump destination with a label, and can be appropriately processed.

Then, as described above, the system simulator 1 converts the factor of dsp () of the target program 2 described in the C ++ language into a machine language of the target CPU system described in the assembler language as a character string. After the framework 5 translates each instruction code of the level and develops it into a machine language, the instruction code is transferred to the CPU simulator 3, and the CPU simulator 3 simulates the instruction.

For example, in the example shown in FIG. 3, as shown in FIG. 4, the framework 5 translates the assembler code of the factor character string of the dsp () macro into a machine language (step P1), and the CPU simulator 3 To simulate the translated instruction contents (step P2). CPU
The simulator 3 checks whether the instruction is a call instruction (call instruction), that is, a subroutine call instruction (step P3). If the instruction is a call instruction, the simulator 3 calls a function, that is, executes a method. The process ends (Step P4).

If it is determined in step P3 that the instruction is not a call instruction, the CPU simulator 3 checks whether the instruction is a jump instruction (jump instruction) (step P3).
5) In the case of a jump instruction, a search is made from a PC (program counter) value for the presence of a label character string registered in advance, and the corresponding jump instruction is executed.
The process ends (Step P6). If it is not a jump instruction in step P5, the CPU simulator 3
The process ends as it is.

As described above, the system simulator 1
A simulation environment in which the target program 2 can be executed by the host CPU system is constructed on the object-oriented framework 5 by exchanging each instruction code by object communication. Therefore, the environment for the development of firmware and the development of the CPU system can be improved.
A PU system can be developed, and rapid development can be performed in CPU systems of different input / output devices by freely combining objects.

The system simulator 1 is composed of a CPU simulator 3 simulating a target CPU and an input / output I / O simulator 4 simulating a target input / output device.
5 that connects the CPU simulator 3 and the input / output I / O simulator 4 with object communication
Therefore, rapid development can be performed even in a CPU system having an input / output device.

Further, the system simulator 1 translates each machine language level instruction code of the target program 2 in which the machine language level instruction code of the target CPU system is incorporated in the language of the framework 5 by a source code simulator. And then simulate. Thus, for example, the assembler code of the target CPU system can be translated into the framework language (eg,
The target program can be created by embedding it in the C ++ language. When using the C ++ language as the framework language, for example, use the debugger attached to the C ++ language. Simulator development can be performed easily and quickly without the need to develop a simulator.

FIG. 5 is a diagram showing a second embodiment of the system simulator of the present invention. This embodiment is a system simulator applied to two CPU systems.

FIG. 5 shows a system simulator 10 to which the second embodiment of the system simulator of the present invention is applied.
In the system simulator 10, the system simulator 20 and the system simulator 30 are connected by a message path 40, and a network is constructed.

The system simulator 20 includes an α target program 21, an αCPU simulator 22, an α input / output I / O simulator 23, an α framework 24, and the like.
Simulator 22 and α input / output I / O simulator 23
Are connected to the α framework 24 by a message path 25.

The system simulator 30 includes a β target program 31, a β CPU simulator 32, a β input / output I / O simulator 33, a β framework 34, etc., and a β target program 31, a β CPU simulator 32, and a β input / output I / O simulator. Each of the objects 33 is connected to the β framework 34 by a message path 35.

Then, the α framework 24 and the β framework 34 are connected by a message path 40, and the simulator 20 and the simulator 30 are in a state of constructing a network.

Each of the system simulator 20 and the system simulator 30 has the same function as the system simulator 1 of the first embodiment, and the framework 17 of the system simulator 20 and the framework 18 of the system simulator 30 Performs object communication via the message path 40.

Therefore, the two system simulators 20 and 30 of the system simulator 20 and the system simulator 30 can be operated in cooperation with each other to appropriately simulate the system, and the target CPU system including a plurality of CPU systems can be simplified. And it can be developed quickly.

Note that in the second embodiment,
The case where the system simulator 10 is constructed by the two system simulators 20 and 30 has been described. However, the invention is not limited to the two system simulators, and a system simulator that operates two or more system simulators in cooperation with each other is constructed. Is also good.

Although the invention made by the inventor has been specifically described based on the preferred embodiments, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible.

[0058]

According to the system simulator of the first aspect of the present invention, a simulation environment in which a target program can be executed by a host CPU system is transmitted and received through an object communication by an instruction communication, so that a target program can be executed on an object-oriented framework. It can improve the environment for firmware development and CPU system development, enabling simple and quick development of firmware and CPU system, and free objects. Rapid development can be performed even for CPU systems of different input / output devices depending on the combination.

According to the system simulator of the second aspect, the system simulator is connected to the target CP.
U, a CPU simulator, an I / O simulator that simulates a target input / output device, and a framework processing unit that connects the CPU simulator and the I / O simulator by object communication. Rapid development can be performed even in a CPU system provided with the device.

According to the third aspect of the present invention, the system simulator includes a plurality of system simulators for simulating a plurality of target CPU systems, a plurality of system simulators, and a plurality of system simulators. And a framework processing means for defining a relationship, so that a plurality of system simulators can be operated in cooperation with each other to appropriately simulate, and a target CPU system composed of a plurality of CPU systems can be provided. Simple,
And it can be developed quickly.

According to the system simulator of the present invention, each instruction code at the machine language level of the target CPU system is sourced from each instruction code at the machine language level of the target program in which the instruction code is incorporated in the language of the framework. Since it is translated and simulated by a code simulator, for example, the assembler code of the target CPU system is translated into a framework language (for example,
The target program can be created by embedding it in the C ++ language. When using the C ++ language as the framework language, for example, use the debugger attached to the C ++ language. Simulator development can be performed easily and quickly without the need to develop a simulator.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a system simulator to which a first embodiment of a system simulator according to the present invention is applied.

FIG. 2 is a flowchart showing a procedure for registering an object in the framework of FIG. 1;

FIG. 3 is a view showing an example of a description example of assembler source code of the target program of FIG. 1;

FIG. 4 is a flowchart showing the processing procedure of the target program of FIG. 3 in the system simulator of FIG. 1;

FIG. 5 is a conceptual diagram of a system simulator to which a second embodiment of the system simulator of the present invention is applied.

[Explanation of symbols]

 1 System Simulator 2 Target Program 3 CPU Simulator 4 Input / Output I / O Simulator 5 Framework 6 Message Path 10, 20, 30 System Simulator 21 α Target Program 22 αCPU Simulator 23 α Input / Output I / O Simulator 24 α Framework 25 Messages Path 31 β target program 32 β CPU simulator 33 β input / output I / O simulator 34 β framework 35 message path 40 message path

Claims (4)

[Claims] 1. A target C to be simulated
A system simulator for simulating, on a host CPU system, instruction codes at a machine language level of a target program for a PU system on a host CPU system to simulate the operation of the target CPU system on the host CPU system. A system simulator constructed on an object-oriented framework by transmitting and receiving each of the instruction codes by object communication, by executing a simulation environment that can be executed by the host CPU system. 2. The system simulator according to claim 1, further comprising: a CPU simulator simulating the target CPU; an I / O simulator simulating a target input / output device;
2. The system simulator according to claim 1, further comprising framework processing means for connecting a PU simulator and an I / O simulator by the object communication. 3. The system simulator includes: a plurality of system simulators for simulating a plurality of target CPU systems; a framework process for activating the plurality of system simulators and defining a relationship between the plurality of system simulators; The system simulator according to claim 1 or 2, further comprising: means. 4. The target program, wherein each instruction code at a machine language level of the target CPU system is incorporated in a language of the framework, and the system simulator comprises: an instruction code at each machine language level of the target program. 4. The system simulator according to claim 1, further comprising a source code simulator that translates the instruction code, interpreting and simulating the instruction codes translated by the source code simulator.