JPH11237997A - Parity generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parity generator with which parity is generated at a high speed without lowering the operating frequency of a transmission system. SOLUTION: This parity generator has a holding means F for dividing a parity arithmetic circuit into plural divided parity arithmetic circuits PL1 and PL2, fetching and outputting the arithmetic result obtained by the divided parity arithmetic circuit on the preceding step among these divided parity arithmetic circuits for each timing of a prescribed clock and a selecting means SEL for selecting the output either of such a holding means or of the arithmetic results and supplying it to a divided parity arithmetic circuit on the following step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a parity generation device in an information data transmission system.

[0002]

2. Description of the Related Art In order to improve the reliability of transmitted / received data, there is known a system for transmitting information data to be transmitted by adding a parity bit as a check bit.
The transmission side of such a transmission system is provided with a parity operation circuit for obtaining a parity for each information data of each block. On the transmission side of the transmission system, information data to be transmitted to which the parity bit obtained by the arithmetic circuit is added is transmitted as one transmission data block.

Here, since the parity operation circuit is composed of a combinational logic circuit having a large number of logic stages, there is a delay corresponding to the number of logic stages from when information data is supplied until parity is obtained. Therefore, when the system clock used in the transmission system becomes faster, the arithmetic processing by the parity arithmetic circuit cannot keep up with the clock, and there is a possibility that an erroneous parity is added to the information data.

Therefore, in such a transmission system, there is a problem that the operating frequency must be lowered in accordance with the processing time of the parity operation circuit.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has as its object to provide a parity generation apparatus capable of obtaining parity at high speed without lowering the operating frequency of the transmission system itself. With the goal.

[0006]

A parity generation device according to the present invention is a parity generation device provided with a parity operation circuit for obtaining a parity based on information data, wherein the parity operation circuit is divided into a plurality of divided parity operation circuits. Holding means for fetching and outputting the operation result obtained by the divided parity operation circuit at the preceding stage of the divided parity operation circuit at every predetermined clock timing, and outputting the output of the holding means and the operation result. Selecting means for selectively selecting one of the above and supplying the selected one to the subsequent divided parity operation circuit.

[0007]

According to the parity generating apparatus of the present invention, the parity operation circuit is divided into a plurality of divided parity operation circuits, and each of the divided parity operation circuits is connected or directly connected via holding means. , The parity can be generated at high speed without lowering the frequency of the clock used in the transmission system.

[0008]

FIG. 1 is a diagram showing an example of a parity generation device according to the present invention. In the parity generation apparatus shown in FIG. 1, one parity operation circuit is divided into first parity operation circuits PL ₁ by dividing the logic stage thereof.
When, is divided into a second split parity operation circuit PL _2.

FIG. 2 is a diagram showing an example of such a parity operation circuit. First, in the parity operation circuit shown in FIG. 2, one block calculates a parity bit for 16-bit information data.
A first logic stage of EX1 to EX8 and a second logic stage of EX9 to EX12
A logic stage, a third logic stage EX13 and EX14, and E
It consists of a fourth logic stage X15.

With this configuration, in the parity operation circuit shown in FIG. 2, the number of bits having the logical level "1" in the 17 bits including the supplied information data and the parity bit is always an even number. The logic level of the parity bit is determined. Therefore, from the supply of the information data to the determination of the parity bit, a processing time of four stages of the exclusive OR circuit is consumed.

At this time, in the parity generation device shown in FIG. 1, for example, the parity calculation circuit as shown in FIG.
_1, is constructed by dividing the second divided parity operation circuit PL _2. That is, the circuit block including the first and second logic stages in FIG. 2 is referred to as a first divided parity operation circuit PL ₁ , and the circuit block including the third and fourth logic stages is referred to as a second divided parity operation circuit PL _2. .

FIGS. 3 and 4 are diagrams showing the internal configuration of each of the first divided parity operation circuit PL ₁ and the second divided parity operation circuit PL ₂ when such division is performed. Here, in FIG. 1, the first divided parity operation circuit PL ₁ performs a parity operation based on the supplied information data, and supplies the operation intermediate result P obtained at this time to the 2TO1 selector SEL and the flip-flop F. . Incidentally, when the internal structure of the first divided parity operation circuit PL ₁ is that shown in Figure 3, the exclusive OR circuit EX9~E
The output P _{1-4 of} each of the X12 becomes the above-mentioned calculation intermediate result P.
Flip-flop F is the incorporation in accordance with the timing of the supplied operation intermediate result signal P system clock signal from the first dividing the parity operation circuit PL _1, supplied to the 2TO1 selector SEL so as computation intermediate result signal P ' .

The 2TO1 selector SEL selects a logical value of a division switching signal from the operation intermediate result signal P supplied from the first divided parity operation circuit PL ₁ and the operation intermediate result signal P ′ supplied via the flip-flop F. The one according to the level is selected as an alternative and this is selected as the second divided parity operation circuit PL ₂
To supply. For example, when the logical level of the division switching signal is "1", the 2TO1 selector SEL selects the operation intermediate result signal P 'supplied from the flip-flop F, while the logical level of the division switching signal is "0". , The operation intermediate result signal P supplied from the first divided parity operation circuit PL ₁ is selected and the second divided parity operation circuit PL _{2 is selected.}
To supply.

The second divided parity operation circuit PL ₂ obtains a parity bit based on the operation intermediate result signal supplied from the 2TO1 selector SEL, and outputs this as a final parity bit. As described above, the parity generation apparatus shown in FIG. 1 selectively selects whether to perform the operation processing by dividing the parity operation circuit into two in units of logical stages or to perform the operation processing without division. It is a configuration that can be implemented.

An example of the operation of the configuration shown in FIG. 1 will be described below. First, if the system clock used in the transmission system is relatively fast, and therefore all the parity operations cannot be completed within one cycle of this system clock, the logic level "1" is set. The division switching signal is supplied to the 2TO1 selector SEL. At this time, 2TO1 selector SEL would be alternatively selected to supply to the second divided parity operation circuit PL ₂ the supplied operation intermediate result signal P 'via the flip-flop F.

That is, if the parity operation cannot be completed within one cycle of the system clock, the first and second divided parity operation circuits PL ₁ and PL ₂ are connected via a flip-flop. Then, the parity bit is obtained by multiplying two cycle periods. According to such a configuration, the number of logical stages in each divided operation circuit is naturally smaller than the total number of logical stages before division and the delay time is reduced, so that a high-speed system clock can be used.

On the other hand, if the system clock is relatively slow and the parity operation can be completed within one cycle, a division switching signal of logic level "0" is supplied to the 2TO1 selector SEL. At this time, 2TO1 selector S
EL will be supplied with operation intermediate result signal P supplied from the first division parity operation circuit PL ₁ directly to the second split parity operation circuit PL _2.

That is, when the system clock is slow enough to end the parity operation within one cycle, the first divided parity operation circuit PL ₁ and the second divided parity operation circuit PL ₂ are connected to a flip-flop. The configuration is such that the parity bit is obtained without any intervention and the parity bit is obtained within one cycle period. In the above embodiment, the division switching signal is generated in accordance with the level of the frequency of the system clock. However, the present invention is not limited to such a condition. For example, the division switching signal may be arbitrarily controlled from outside. You may be able to do it. In short, in connecting the divided parity operation circuit of the preceding stage and the divided parity operation circuit of the subsequent stage, it is possible to selectively select either via a holding means such as a flip-flop or directly connecting without such a holding means. What is necessary is just to have a configuration that can be used.

FIG. 2 shows an example of the internal configuration of the parity operation circuit. However, the parity operation circuit to be divided in the present invention is not limited to this configuration. In short, the present invention can be applied to any circuit formed by a combinational logic circuit having a plurality of logic stages. Further, in the above embodiment, the configuration example in which one parity operation circuit is divided into two is shown. However, the number of divisions is not limited to two, and the present invention is applicable to any division number of three or more. It is possible.

FIG. 5 shows that one parity operation circuit is divided into three parts such as a first divided parity operation circuit PL ₁ , a second divided parity operation circuit PL ₂ , and a third divided parity operation circuit PL ₃ in units of logical stages. FIG. 2 is a diagram illustrating a configuration of a parity generation device when formed. In FIG. 5, a first divided parity operation circuit PL ₁ and a second divided parity operation circuit P
Between L _2, and respectively between the second divided parity operation circuit PL ₂ and the third divided parity operation circuit PL _3, has a configuration providing a 2TO1 selectors and the flip-flop similar to FIG.

The first divided parity calculation circuit PL ₁ performs a parity calculation on the supplied information data, and uses the obtained calculation intermediate result as a first calculation intermediate result signal PA as a 2TO1 selector SEL and a flip-flop FA. To each of the 2TO1 selector SEL1, when the logic level of the first division switching signal is "0", the second as it takes first operational intermediate result signal PA dividing the parity operation circuit PL ₂
While the logical level of the first division switching signal is "1".
If it supplies the first operation intermediate result signal PA which is supplied through the flip-flop FA to the second divided parity operation circuit PL _2.

The second divided parity operation circuit PL ₂ has a 2TO1
First operation intermediate result signal PA supplied from selector SEL1
, And the intermediate operation result obtained at this time is used as a second intermediate operation result signal PB as a 2TO1 selector SE
L2 and the flip-flop FB. 2TO1 selector SEL2, when the second dividing logic level of the switching signal is "0", while supplying such second computing intermediate result signal PB as the third divided parity operation circuit PL _3, the second split switching when the logic level of the signal is "1" supplies the second computation intermediate result signal PB supplied via the flip-flop FB to the third divided parity operation circuit PL _3.

The third divided parity operation circuit PL ₃ has 2TO1
Second operation intermediate result signal PB supplied from selector SEL2
, And a final parity bit is obtained. As described above, in the parity generation apparatus shown in FIG. 5, by setting the division switching signals 1 and 2 independently, whether the parity calculation processing is executed in two or three or three is performed. It is possible to select whether or not to do so. Note that there are two ways of dividing into two depending on how the division switching signals 1 and 2 are set. That is, the logical level of the division switching signal 1 is changed to "
1 If set to 0 "", the logic level of the divided switching signal 2 ", and the second divided parity operation circuit PL ₂ and the third split parity operation circuit PL ₃ is directly connected, these a first dividing the parity operation circuit PL ₁ a two-split structure of the. other hand, splitting off the logic level of the signal 1 "0", divided by setting the switching the logic level of the signal 2 "1", the first dividing the parity operation circuit PL ₁ second divided parity an operation circuit PL ₂ is directly connected,
These and is of a two-piece construction of the third divided parity operation circuit PL _3.

[0024]

As described above in detail, the parity generation apparatus according to the present invention divides a parity operation circuit into a plurality of divided parity operation circuits, and uses a divided parity operation circuit at a preceding stage among these divided parity operation circuits. Holding means for taking in the calculated result at every predetermined clock timing and outputting the result; and selectively selecting one of the output of the holding means and the result of the calculation and sending the selected result to the subsequent divided parity calculation circuit. Since the configuration is provided with the selection means for supplying, the parity can be generated at high speed without lowering the clock frequency used in the transmission system.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a parity generation device according to the present invention.

FIG. 2 is a circuit diagram illustrating an example of a configuration of a parity operation circuit.

3 is a circuit diagram showing an example of the internal configuration of the first divided parity operation circuit PL _1.

4 is a circuit diagram showing an example of the internal configuration of the second divided parity operation circuit PL _2.

FIG. 5 is a circuit diagram showing an example of a parity generation device according to another embodiment of the present invention.

[Description of Signs of Main Parts]

PL ₁ first division parity operation circuit PL ₂ second division parity operation circuit F flip-flop SEL 2TO1 selector

Claims (4)

[Claims] 1. A parity generation device comprising a parity operation circuit for obtaining a parity based on information data, wherein the parity operation circuit is divided into a plurality of divided parity operation circuits. Holding means for taking in and outputting the operation result obtained by the divided parity operation circuit of the preceding stage at every predetermined clock timing; and selectively selecting one of the output of the holding means and the operation result. And a selecting unit for supplying the data to the divided parity operation circuit at the subsequent stage. 2. The parity generation device according to claim 1, wherein each of the divided parity operation circuits is obtained by dividing the parity operation circuit into a plurality of logic stages. 3. The selecting means selects the output of the holding means when the predetermined clock is relatively high-speed and supplies it to the subsequent divided parity operation circuit, while the predetermined clock is low-speed. 2. The parity generating apparatus according to claim 1, wherein in the case of (1), the operation result is selected and supplied to the subsequent divided parity operation circuit. 4. The method according to claim 1, wherein the selection unit selects one of an output of the holding unit and the operation result according to an externally supplied signal, and supplies the selected one to the subsequent divided parity operation circuit. The parity generation device according to claim 1, wherein: