JPH11234302A - Queue device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process the large amount of data with relatively simple circuit configuration indepently of the number of lines, ports, virtual connections or virtual paths, etc. SOLUTION: In element blocks 11-1n, the queue priority orders of the respective data and a counter value showing the oldness of the input counted by a counter inside a counter module 2 are stored and held respectively as comparison numerical values A and B. At the time of outputting the data, the ones of the highest queue priority order and the oldest input are selected by a block ID selector 3 and the block ID is outputted from the block ID selector 3. By outputting the pertinent data based on the block ID from a memory storing a data main body not shown in Figure, the large amount of the data are processed by the constitution simpler than heretofore.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a queuing device used in an ATM switch, a switching hub, and the like, and more particularly, to a queuing device having a simplified configuration and improved processing capability.

[0002]

2. Description of the Related Art Conventionally, as an apparatus of this type, there is, for example, one shown in FIG. Hereinafter, this conventional apparatus will be described with reference to FIG. 14. First, this apparatus is suitable for processing data having a so-called priority, and particularly, a configuration in a case where there are three levels of priorities. It is shown. That is, this queuing device is a known / known FIFO (F
first to third priority FIFOs 85 to 87 that are provided in correspondence with the priority of data and store address values at which data is stored;
Idle for storing addresses of empty data areas
FIFO 84 and Input Controlle for controlling data input
r81 and Output Controller 8 for controlling data output
2 and a Date Buffer 83 for storing data as main components.

The received data externally input to the Input Controller 81 is the original data to which a predetermined identifier indicating the priority order or judgment data for determining the priority order is added. Is input, first, the Data Controller
The address value indicating the free data area in r83 is Idl
e It is taken out from the FIFO 84. Then, the priority of the data is determined based on the identifier and the like included in the received data. For example, if the priority is the second priority, the free data area address value read by the input controller 81 is used. Is written to the second priority FIFO 86, and the received data itself is written to the above-mentioned free data area address in the DataBuffer 83.

On the other hand, the Output Controller 82 checks whether or not the address value is stored in the first priority FIFO 85, and if the address value is stored, the Data Buffer 83
, The data written to the address value is read out and sequentially transmitted, and the address value is written to the idle FIFO 84.
The operation of the Output Controller 82 is the first priority FIFO.
This operation is repeated until 85 becomes empty, and thereafter, the same operation is repeated for the second priority FIFO 86 and the third priority FIFO 87.

[0005] Such a queuing device is suitable for a case where data has a priority. However, in an ATM switch or a switching hub, not only a case where data is sequentially output in a priority order, but also, for example, the data is output. In some cases, when a line is overloaded, data for the line needs to be temporarily dequeued.
FIG. 15 shows an example of a configuration of a publicly-known and well-known queuing device that enables processing when such data needs to be temporarily removed from the queue. This device will be described with reference to FIG.

This queuing device includes first and second FIFOs 911 and 9 for accumulating address values of data to be transmitted for each so-called virtual connection.
12 and first and second timers 921 and 922 for counting the waiting time required for each virtual connection.
And a Data Buffer 93 for storing data, and a Traffic Ca for performing operations necessary for controlling traffic.
lculator90 and Output Contr for controlling data output
The oller 94 is a main component.
In such a configuration, for example, virtual channel 1
When a transmission request is generated from the first FIF, the address value of the Data Buffer 93 storing the data to be transmitted is changed to the first FIF.
This is input to O911.

[0007] Then, the Output Controller 94 transmits the cell that is the target of the transmission request.
It is determined by calculation whether or not a predetermined cell flow rate is not violated. If it is determined that the cell flow rate does not violate a predetermined cell flow rate, the corresponding cell data is read from the Data Buffer 93 and output controller 94 is output. Is output via the. On the other hand, when it is determined by the Output Controller 94 that the flow rate does not exceed the predetermined cell flow rate, the waiting time until the output cell 94 does not violate the predetermined cell flow rate is the first time.
Is set in the timer 921, so-called time counting is performed. When a predetermined waiting time is counted by the first timer 921, the data buffer 93 is counted.
The corresponding cell data is read from
This is output via the troller 94. That is, the transmission request from the virtual channel 1 is temporarily removed from the queue during the waiting time set in the first timer 921. Virtual channel 2
Is basically processed in the same manner as when a transmission request is made on the virtual channel 1 described above.

[0008]

However, in the case of the former conventional apparatus, as the number of data priorities increases, and as the number of queues increases, the number of necessary FIFOs also increases, and There is a problem that the configuration is complicated and the price is increased. Furthermore, since the capacity of the FIFO corresponds to the number of received data written to the Data Buffer 83 due to the function described above,
Assuming that the number of received data is 100, the FIFO must have the capacity to write 100 address values, and if there are two or more types of queues, the capacity must be multiplied by the number of the types. Becomes That is, if the received data is 100 and the queue type is 10, the FIFO is
A memory having a write capacity of 100 × 10 = 1000 address values is required, and the capacity is cumulatively increased. Since this capacity is not always required, it is uneconomical. If you want
There is a problem that it becomes a big obstacle.

On the other hand, in the latter conventional device described above, the FIFO and the timer determine the size of the line in which the device is used,
That is, although only the number of virtual connections or virtual paths is required, in general, an exchange may handle hundreds to thousands of virtual connections or virtual paths, which complicates the device configuration and increases the cost. Become. Therefore, although practical when the number of virtual connections or virtual paths is extremely small, there is a problem that practicality is low in terms of economy.

The present invention has been made in view of the above-mentioned circumstances, and a large-scale data processing can be performed with a relatively simple configuration without a circuit scale depending on the number of lines and ports, the number of virtual connections and virtual paths, and the like. It provides a queuing device that enables it. Another object of the present invention is to provide a queuing device that can temporarily remove data from a queue according to the status of a connected line and that has a relatively simple configuration and good economical efficiency. To provide. further,
It is another object of the present invention to provide a queuing device that guarantees the order of cells and packets.

[0011]

The queuing device according to the present invention has a counter having a number corresponding to the maximum possible value of the first identification value input together with the first command from the outside. When the first command is input, the first command
A counter for outputting a counter value corresponding to the first identification value input together with the command as a counter value, and incrementing the counter value of the counter by one, and storing for each of a plurality of preset block identification numbers A first identification value input together with a command from the outside and a counter value from the counting means in a storage area designated by a predetermined block identification number in accordance with the command; An identification information storage unit that outputs the block identification number, the first identification value, and the counter value in response to the command; and a plurality of block identification numbers, a first identification value, and a plurality of block identification numbers input from the identification information storage unit. From among the counter values, the one in which the first identification value has a predetermined value indicating the highest priority is selected, and when the number of the first identification values indicating the highest priority is one, First While outputting the block identification number and the counter value together with the different value, if there are a plurality of selected first identification values, the one whose counter value indicates the predetermined highest priority value is selected from among them. , Top priority selecting means for outputting a block identification number and a first identification value together with the counter value, wherein the identification information storage means comprises:
Is input to the storage area corresponding to the block identification number externally input together with the first command.
When the second command is input, the first identification value and the counter value of the storage area corresponding to all block identification numbers are output together with the corresponding block identification numbers, When the third command is input, the magnitude relationship between each first identification value stored in the storage area and the first identification value input together with the third command is defined by the third command. The first identification value stored in the storage area corresponding to the magnitude relationship is selected, and the block identification number and the counter value are output together with the first identification value.

In this configuration, in particular, for example, a first identification value represented by priority of a queue and a count value indicating the oldness of the input as additional information of data are stored for each block identification number. It is characterized in that it is configured to be stored and managed in the identification information storage means, and that the highest priority selection means selects a block identification number of high priority data. Unlike this, there is no need to provide a storage means for each first identification value, that is, for example, for each priority of a queue, and
Since a high-priority data is reliably selected, a queuing device capable of handling a large amount of data with a simple configuration is provided, in which the circuit scale is less affected by the number of lines and the like. .

According to a sixth aspect of the present invention, in the queuing apparatus, the first identification value and the second identification value input together with the first command from the outside correspond to the product of the maximum number of possible values. The first command is input, and when the first command is input, the counter value corresponding to the first discrimination value and the second discrimination value input together with the first command is determined. A counter which outputs a counter value and increments the counter value by one, and has a storage area for each of a plurality of preset block identification numbers, and a first identification value and a first identification value which are input together with a command from outside. While storing a second identification value and a counter value from the counting means in a storage area designated by a predetermined block identification number in accordance with the command, the block identification number in response to the command, First identification value An identification information storage unit that outputs a second identification value and a counter value; and a plurality of block identification numbers, a first identification value, a second identification value, and a counter value input from the identification information storage unit. On the basis of the first identification value, the second identification value, and the counter value, the one with the highest priority is selected, and the block identification number, the first identification value, the second identification value, and the counter value are output. When the first command is input, the first identification value is stored in a storage area corresponding to the block identification number externally input together with the first command. , The second identification value and the counter value are stored, and when the second command is input, the first identification value, the second identification value, and the counter value of the storage area corresponding to all the block identification numbers are stored. Output with the block identification number When the third command is input, the magnitude relationship between each first identification value stored in the storage area and the first identification value input together with the third command is defined by the third command. And selecting a first identification value stored in the storage area corresponding to the magnitude relation to be performed, and outputting a second identification value, a block identification number, and a counter value together with the first identification value. Things.

[0014] Such a configuration has, in particular, a first identification value represented by, for example, a priority of a queue as additional information of data, and a second identification value represented by, for example, a type of queue. The count value indicating the oldness of the input is stored and managed in the identification information storage means for each block identification number, and the block identification number of the data with the highest priority is selected by the highest priority selection means. Therefore, unlike the related art, there is no need to provide a storage unit for each priority, and data with a high priority is reliably selected. A queuing device that is less affected by the number of lines and the like and can handle a large amount of data with a simple configuration is provided.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. First, first
The embodiment will be described with reference to FIGS. The queuing device according to the first embodiment includes a plurality of element blocks (denoted as "Element Block" in FIG. 1) 11, 12,... 1n, and a block ID selector as the highest priority selecting means (in FIG. 1, "Block ID S
elector) 3 and a counter module as a counting means (referred to as "Counter Module" in FIG. 1)
2 is a main component, and receives a block selection signal, a command as command, and data from the outside, respectively, and operates as described later (see FIG. 1). .

A block selection signal (denoted as “Block Selection” in FIG. 1) is transmitted via a block selection bus 4 to each of the element blocks 11 to 1n.
To the command (referred to as “Command” in FIG. 1)
Is connected to each element block 11 via the command bus 5.
To 1n and the counter module 2, and additional information of data to be described later are input to each of the element blocks 11 to 1n and the counter module 2 via the data bus 6.

The element blocks 11 to 1n store the priority of a queue as a first identification value, a counter value indicating the order of input to the queue, and a block ID as a block identification number. Are output to the block ID selector 3 as necessary, respectively, as a comparative numerical value A, a comparative numerical value B, and a block ID (details will be described later). Here, the first identification value is additional information relating to the data which is input from the outside together with the data, that is, one of the additional information of the data.

The block ID selector 3 compares the comparison value A, the comparison value B and the block ID from each of the element blocks 11 to 1n under predetermined conditions. B and the block ID are output (details will be described later).

The counter module 2 has a counting function and has the same number of counting functions as the number of priorities in the queue. In each priority order, the order in which data is input is counted. The counter value (denoted as “Counter Value” in FIG. 1) is transmitted to each of the element blocks 11 to 1 through the counter value bus 7 as necessary.
n (see below for details).

Here, a preferred configuration example of the element blocks 11 to 1n will be described with reference to FIG.
First, the element blocks 11 to 1n are composed of a command analyzer (indicated as “Command Interpreter” in FIG. 2) 501 and an address decoder (“Ad in FIG. 2”).
d Decoder) 502 and a block ID register (denoted as “Block ID Reg.” in FIG. 2) 503
And a register for a comparison value A as a first register for realizing the first storage means (“Comp.Value R
A) 504, a register for comparison numerical value B (described as “Comp. Value Reg. B” in FIG. 2) 505 as a second register for realizing the second storage means, and a block ID The driver 506, the driver 507 for the comparison value A, and the driver 508 for the comparison value B are configured as main components.

The command analyzer 501 analyzes a command and, based on the result of the analysis, registers the comparative numerical value A
04 and a write signal (noted as “WR” in FIG. 2) for the register 505 for comparison value B, and an output enable signal (noted as “OE” in FIG. 2) for each of the drivers 506 to 508. It is designed to be output (details will be described later). The address decoder 502
It is determined whether or not the block ID set in advance for each of the element blocks 11 to 1n and stored in the block ID register 503 matches a predetermined block ID input as a block selection signal. In this case, the command analyzer 501 sets a my address signal (indicated as “My Add” in FIG. 1) for notifying the command analyzer 501 that the element block has been designated, to a so-called active state.
Is to be output to Here, as the block selection signal, as described above, in addition to the case where it is used to specify a specific element block, a predetermined code for specifying all the element blocks 11 to 1n is input. Case (hereinafter,
Such a state is also referred to as “broadcast”. In this case, the block selection signal is input to the address decoder 502 as a broadcast state, so that the address decoder 502 outputs a my address signal. It is set to the active state and output to the command analyzer 501. The configuration, functions, and the like of other components will be clarified in the operation description described later.

Regarding the operation in such a configuration,
The description will focus on each of the element blocks 11 to 1n and the counter module 2. First, as a premise, in the above configuration, commands input as commands include a “comparison numerical value write request command” as a first command, a “total output command” as a second command, and a “total output command” as a third command. It is assumed that there are three “conditional output commands”. The "conditional output command" is used to output data when the priority of the queue is equal to the predetermined order X, and to output data when the priority of the queue> the predetermined order X. It is assumed that the data is classified into three types, that is, data that is output when the priority of the queue <the predetermined order X.

In the comparative numerical value write request command, the "priority of the queue" is simultaneously sent on the data bus 6. In the conditional output command, a condition “queue priority X” is simultaneously sent to the data bus 6. Here, the “queue priority” is used to identify a plurality of queues, each of which has a priority.

Under this premise, for example, when a comparison numerical value write request command is input, the counter module 2
Sends the value of the counter on the data bus 6 corresponding to the "priority of the queue" as the counter value. That is, the counter module 2 is provided with a counter (not shown) for each priority of the queue, and when a comparison numerical value write request command is input, the counter value of the corresponding counter at that time is set in each element block. 11 to 1n, and thereafter the counter is counted up.

Here, the number of bits of each counter of the counter module 2 depends on the total number of element blocks. That is, for example, if the total number of element blocks is 2 n, the counter needs (n + 1) bits. The counter value of this counter is used to determine the oldness of the input to the queue. For example, if the total number of element blocks is 2 n, it is assumed that the counter has n bits. Then, it is not possible to judge which was input earlier by comparing the two counter values. That is, for example, assuming that the total number of element blocks is 8 and the counter is 3 bits, one counter can count up to 8 times including “000”. Therefore, if data input exceeds this,
As a matter of course, the counter value of the counter returns to “000” again, and counting up is restarted from that value. Therefore, in this case, the comparison between the two 3-bit counter values “001” and “010” does not serve as an index indicating which was input first. However, in this case, if the number of bits of the counter is set to 4 bits, considering that the difference between the two counter values does not exceed 2 ⁿ , “0001” and “0010” are considered.
Then, it is possible to determine that "0001" has been input earlier.

Next, the operation of the element blocks 11 to 1n will be described. First, information for specifying the element blocks 11 to 1n is externally input to the block selection bus 4. The information is decoded by the address decoder 502. When the decoding result matches the identifier (block ID) preset for each of the element blocks 11 to 1n, the address decoder 502 activates the my address signal, and the command analyzer 501. In addition, the address decoder 502 outputs the block selection signal to all the element blocks 11
1 to 1n, that is, when the simultaneous broadcast is indicated, the my address signal is activated.

The command on the command bus 5 is analyzed by the command analyzer 501 when the my address signal is activated. First, when a comparison numerical value write request command is input, each element block 11
The command analyzers 501 to 1n activate the write signal, write the "queue priority" sent from the outside onto the data bus 6 to the register 504 for the comparison numerical value A, and simultaneously execute the bus for the counter value. The value of the counter sent from the counter module via the counter 7 is the comparison value B
Is written to the register 505. Thereafter, the register 504 for the comparative numerical value A is set as described above.
Are referred to as “comparison value A”, and the value written to the comparison value B register 505 is referred to as “comparison value B”.

Next, when the total output command is input, the command analyzer 501 activates the output enable signal. As a result, via the block ID driver 506, the block ID is set to the comparative numerical value A driver 507.
Via the driver 508 for the comparison value B
, The comparison value B is output. In the state where the element blocks 11 to 1n do not output anything, the output ports of the driver 507 for comparison numerical value A and the driver 508 for comparison numerical value B are configured to be "1" in all bits. I have.

When a conditional output command is input, the command analyzer 501 outputs the “queue priority”, which is the output condition sent on the data bus 6, and the comparative numerical value A register 504. The values are compared, and if the conditions are met, the output enable signal is activated. As a result, the block ID driver 506 sends the block I
D indicates that the comparison numerical value A
However, the comparative numerical value B driver 508 outputs the comparative numerical value B
Are respectively output.

Next, a more specific configuration example of the block ID selector 3 and its operation will be described with reference to FIG. Block ID selector 3 in this configuration example
Are the block ID selector submodules 311 to 31
(n / 2), 321-32 (n / 4),... 3i are hierarchically connected. In the following description, the block ID selector sub-module 311
.. 31i (n / 2), 321-32 (n / 4),..., 3i, if they do not indicate a specific block ID submodule, they will be referred to as a block ID selector submodule 300. . That is, for each of the two adjacent element blocks of the previous element blocks 11 to 1n, the block ID selector sub-module 3
11 to 31 (n / 2) are provided, and these (n / 2) block ID selector sub-modules 31 to 31 (n /
Contrary to 2), as in the case of the previous stage, two blocks are set as one set, and on the other hand, a block I having the same configuration
D selector submodules 321 to 32 (n / 4) are provided respectively, so that a plurality of block ID selector submodules 300 are combined to form a so-called hierarchical structure. Has become.

The block ID selector sub-module 300 preferably has a configuration as shown in FIG. That is, the block ID selector sub-module 300 includes a comparator A (denoted as “Comparator A” in FIG. 4) 41, a comparator B (denoted as “Comparator B” in FIG. 4) 42, and a selector (FIG. , "Selector") is a main component.

The comparator A41 receives two comparison values A, and outputs the two comparison results as a select A signal (FIG. 4).
Is written as "Select A") to the selector 43. Two comparison numerical values B are input to the comparator B42, and the two comparison results are output to the selector 43 as a select B signal (denoted as "Select B" in FIG. 4). Then, the selector 43 selects and outputs one of the two comparison numerical values A, B and the block ID based on the select A signal or the select B signal, as described later.

The block ID selector 3 having the above configuration inputs the block ID, the comparison value A and the comparison value B output from each of the element blocks 11 to 1n, and inputs the comparison value A and the comparison value B respectively. By comparison, the highest priority value is selected, and the comparison value A and the comparison value B are output together with the block ID having that value. As described above, the comparison value A indicates the priority of the queue, and the comparison value B indicates the order of input to the queue. Accordingly, the block ID selector 3 first compares all the comparison values A, and selects the block I having the smallest comparison value A (that is, the first priority) from among them.
Select D. If there are a plurality of minimum comparison values A, the comparison value B is compared, and a block ID corresponding to the first input data in the queue is selected, and the block ID is selected together with the block ID. , Comparative numerical value A and comparative numerical value B are output.

In this embodiment, the highest priority value of the comparative numerical value A is set to the minimum value. However, whether the highest priority value of the comparative numerical value A becomes the minimum value or the maximum value is determined by using the apparatus. It should be selected according to the conditions of a typical system, and does not affect the gist of the present invention.

In the case of the configuration shown in FIG. 3, the comparison value A (1) from the first element block (denoted as “Element Block (1)” in FIG. 1) 11 and the second element block ( In FIG. 1, the comparison value A (2) from the “Element Block (2)” 12) is compared by the block ID selector sub module 311. The value is compared with the block ID from the smaller element block. The comparison value A and the comparison value B are output to the next stage. If the comparison values A (1) and A (2) are equal, then the first
Is compared with the comparison value B (2) from the second element block 12, and the comparison value along with the block ID from the element block to which the data was previously input. A and the comparison value B are output to the next stage. This operation is performed by the other block ID selector sub-modules 313 to 313.
31 (n / 2), 321-32 (n / 4),..., 3i are basically the same, and the description of the respective operations is omitted here.

Here, which of the two element blocks data is input first is determined as follows. As described above, assuming that the total number of element blocks is 2 ⁿ , (n + 1) digital bits representing the comparison value B are required. Since the total number of element blocks is 2 ⁿ , the difference between the two comparison values B does not exceed 2 ⁿ . However, the counter in the counter module 2 is 2
Note that after counting between ^{(n + 1)} -1, it returns to 0. The following can be said from these. That is, if two numerical values to be compared are X and Y, respectively,

1) When 2 ⁿ > X ≧ 0 and 2 ⁿ > Y ≧ 0, as a result of XY, if bit (n + 2) = 0, then Y first

2) When 2 ⁿ > X ≧ 0 and 2 ⁿ > Y ≧ 0, as a result of XY, if bit (n + 2) = 1, then X first

3) 2 ^{(n + 1)} > X ≧ 2 ⁿ and 2 ^{(n + 1)}
> Y ≧ 2 ⁿ , as a result of XY, bit (n
+2) = 0, then Y first,

4) 2 ^{(n + 1)} > X ≧ 2 ⁿ and 2 ^{(n + 1)}
> Y ≧ 2 ⁿ , as a result of XY, bit (n
+2) = 1, then X first,

5) 2 ⁿ > X ≧ 0 and 2 ^{(n + 1)} > Y ≧
In the case of 2 ⁿ , as a result of XY, bit (n + 1)
If = 0, then Y first,

6) 2 ⁿ > X ≧ 0 and 2 ^{(n + 1)} > Y ≧
In the case of 2 ⁿ , as a result of XY, bit (n + 1)
If = 1, X first,

7) 2 ^{(n + 1)} > X ≧ 2 ⁿ and 2 ⁿ > Y
In the case of ≧ 0, the result of XY is bit (n + 1)
If = 0, then Y first,

8) 2 ^{(n + 1)} > X ≧ 2 ⁿ and 2 ⁿ > Y
In the case of ≧ 0, the result of XY is bit (n + 1)
If = 1, then Y first

Each of them is input. Here, bit (n + 1) means the (n + 1) th bit from the least significant bit, and bit (n + 2) means the (n + 2) th bit from the least significant bit. As described above, in the next-stage block ID selector sub-modules 321 to 32 (n / 4) to which the comparison result from the previous stage is input, similarly, the two comparison values A are compared, and further, if necessary. The comparison value B is compared with the block ID having the higher priority.
The comparison value A and the comparison value are output to the next stage, respectively, and the same operation is repeated in each of the block ID selector submodules (not shown) at the next stage and thereafter, the block ID of the highest-priority data is selected, and the block ID is selected. The comparison numerical value A and the comparison numerical value B are output from the last-stage block ID selector sub-module 3i together with the ID. In the first embodiment described above, the command analyzer 501 controls the write control means according to the second aspect.
The output control means, the judgment output means and the forced output prohibition means are realized.

Next, as a second embodiment, the first embodiment will be described.
FIG. 5 shows an example of the configuration of a more complex queuing device configured using the basic queuing device shown in the embodiment of FIG.
This will be described with reference to FIG. In FIG. 5,
For example, the notation “Block ID (1)” means that it is the first block ID, and the block ID =
It does not mean 1, but the same applies to other notations. Further, the same applies to other drawings hereinafter. First, the configuration of the apparatus will be described with reference to FIG. In the figure, the portion indicated by reference numeral A is the device portion in the first embodiment shown previously with reference to FIGS. 1 to 4, and thus the detailed description is omitted here. Hereinafter, different points will be mainly described. The same components as those shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below. The queuing device shown in FIG. 5 has, in particular, 32 element blocks 11, 12,..., 132. An input controller (noted as “Input Controller” in FIG. 5) 61 as a means and a control adjuster (FIG. 5)
In FIG. 5, an “Arbiter” 62 and an output controller as an output control means (“Output Controlle” in FIG. 5)
r) 63 and an input address generator as an input address generating means (“Address Generat” in FIG. 5).
or) 64 and an output address generator (in FIG. 5, “Address Gener
ator) 65, and a data buffer (denoted as “Data Buffer” in FIG. 5) 66 as data storage means.
And are constituted as main components.

The input controller 61 has a data input enable signal (in FIG. 5, "In Data Abailable" in FIG. 5) indicating that there is data input to the input controller 61 from outside.
) Is input, whereby the input controller 61
Is an input data read signal (in FIG. 5, “In Data
Read), and when this data read signal is activated, data is input. The input controller 61 receives a block ID from the block ID selector 3 as described later.

.., And 132. As will be described later, the input controller 61
Input-side block selection signal (in FIG. 5, denoted as "Block Selection I")
132 is determined as an input-side command (in FIG. 5, denoted as “Command I”), and the operation of the element blocks 11, 12,. The additional information of the data necessary for performing such operations is output as input-side data (denoted as "Data I" in FIG. 5), while the address initial value (see FIG. 5 output an "Init Add") and an address count signal (denoted as "Add Inc." in FIG. 5), and are written to the data buffer 66 for the data buffer 66. External data (Fig. 5
Output "Writen Data").

When the access request from the input controller 61 and the access request from the output controller 63 to each of the element blocks 11, 12,... One of the access requests is prioritized, and then the other access request is satisfied. It should be noted that the condition under which one is prioritized is determined by the specific environmental conditions in which the device is used, and need not be limited to a specific condition. The output controller 63 outputs a data output enable signal (not shown) to an external device (not shown) connected to the output stage of the output controller 63 to notify that data can be output. In FIG. 5, “Out Data Abailable” is output, and an output data read signal (in FIG. 5, “Out Data Abailable” in FIG. 5) indicating that the external device is ready to read data. Data Read "
Is input in a so-called active state, predetermined data is output (details will be described later).

The output controller 63 outputs an output-side block selection signal (referred to as "Block Selection O" in FIG. 5) which is a signal for selecting a predetermined element block 11, 12,... The command for instructing the operation state of the element blocks 11, 12,...
nd O ”) as element blocks 11 and 12
... Additional information of data necessary for determining the operation of 132 is output as output side data (denoted as "Data O" in FIG. 5) (details will be described later). The output controller 63 receives the block ID from the block ID selector 3 and, in a predetermined case as described later, sends an address initial value to the output address generator 65 (in FIG. 5, " Init Add) and an address counting signal (“Add Inc.” in FIG. 5).
) And reads data from the data buffer 66.

The input address generator 64 and the output address generator 65 have the same basic configuration and operation, and the input address generator 64 is provided with the address input from the input controller 61. The first address value to be output to the data buffer 66 is set based on the initial value, and the address value is advanced by one each time the address count signal is activated. The output address generator 65 is provided with the output controller 6.
The first address value to be output to the data buffer 66 is set on the basis of the address initial value input from No. 3, and the address value is advanced by one each time the address count signal is activated. Things.

The data buffer 66 accumulates the data input via the input controller 61 at the address indicated by the address value input from the input address generator 64, while storing the output address generator The data at the address indicated by the address value inputted from the address 65 is output.

Next, the operation in this configuration will be described. First, as a precondition, it is assumed that the number of bits for representing the comparison value A is 3 bits. The number of bits for representing the comparison value B is determined by the element blocks 11 and 12.
Since 132 are 32 as described above, the number of bits is 6 bits. And each element block 1
132 are assigned block IDs 0, 1, 2,... 31 in order from the first element block 11. Each of these block IDs
Are written in the block ID registers 503 of the element blocks 11, 12,... Further, the number of queues is 6, and the queue numbers are Queue0, Queue
1 ... Queue5.

Then, assuming that Queue 0 is the queue with the highest priority, Queue 1 is the second, Que
ue2 is the third queue. Queue5 is the queue with the lowest priority. "Queue priority" is "000", "001", "01" in order from Queue0.
It shall be coded as "0", "011", "100", "101". Further, in addition to these five queues, an IdleQueue having a meaning as an initial value is provided, and “110” is assigned to the Idle Queue as “queue priority”. Then, the priorities of these queues are treated as the comparison numerical value A.

In this embodiment, when nothing is output as the comparison value A, all bits are assumed to be "1", and "111" is not assigned as a value indicating the priority of the queue. In the initial state, it is assumed that all of the element blocks 11, 12,... 132 are unused. Furthermore, in the initial state, the register 504 for the comparison value A indicates “11” indicating Idle Queue.
"0" is stored in the comparison value B register 505 in the order from the first element block 11, "0", "1".
It is assumed that numerical values indicating block IDs are set in ascending order.

Under such prerequisites, a method of inputting a queue will be described first. It is assumed that data input from the outside is a so-called data block of a group such as an ATM cell or a packet. The input controller 61 always checks the data input enable signal.
When this signal is active, it means that there is a data block to be externally input. Then, when the data input enable signal becomes active, the input controller 61 reads one word of data by setting the data read signal to a so-called on / off state.

When the data input enable signal becomes active, the input controller 61 outputs to the control adjuster 62 a conditional output instruction of “110” indicating Idle Queue as the priority of the queue. In this case, it is assumed that the input side block selection signal is set to the simultaneous broadcast state. Therefore, at this point, the comparison numerical value A register 50 of all the element blocks 11, 12,.
4 is set to “110”. This means that all the element blocks 11, 12, ... 132 belong to the Idle Queue. Then, as described in the precondition, the register 505 for the comparison value B is set to “0”, “1”,. Block I
.., 13 in the order of block ID.
2 means that the Idle Queue is set.

For this reason, all the element blocks 1
., 132 sends the block ID, the comparison value A, and the comparison value B to the block ID selector 3 respectively. Then, the block ID selector 3 searches for the oldest value of the comparison numerical value B.
At this point, the oldest value of the comparison value B is 0, and its block ID is “0”. Therefore, block I
The D selector 3 sends “0” as the block ID, and this block ID is input to the input controller 61 and the output controller 63, respectively. In this way, the input controller 61 uses the element block with the block ID “0” for the data block to be currently input.

On the other hand, after detecting that the data input enable signal is active, the input controller 61 turns on / off the data read signal and reads the header of the input data block. Then, the input controller 61 determines from the information written in the header of the input data block which priority queue this input data block is to be put in.

Here, for example, it is assumed that this data block is determined to be the data block of the third priority, that is, the data block to be input to Queue 2 from the header of the input data block. Then
The input controller 61 sets the block selection signal to “0”.
The comparison numerical value write request command
132 are written to the comparison value A register 504 of the element block 11 having the block ID = 0 as the comparison value A. At this time, the counter value “000000” corresponding to Queue 2 is output from the counter module 2 and written into the register 505 for the comparison value B of the element block with the block ID = 0. As a result, the element block 11 with the block ID = 0 is taken out of the Idle Queue and the Queue 2
Is input to

Then, the input controller 61 sets the block ID
The read data block is written to the address of the data buffer 66 corresponding to = 0. As a method of writing the data, there is a method of using a conversion table of each block ID and a buffer address, a method of shifting the block ID to the left by a predetermined number of bits, for example, and using this as a buffer address. In either case, the input controller 61 determines the initial value of the write address based on the block ID, and this is input to the input address generator 64 as an address initial value signal.

Subsequently, the input controller 61 turns on / off the address count signal each time data is input from the outside. Thus, the input address generator 64 sends the value input as the address initial value signal onto the buffer address bus 8, and outputs the address value in ascending order each time the address count signal is turned on / off. By doing
When the data block is one word at a time, the data buffer 66
Will be written to the area specified by the buffer address. In this writing, first, the header of the data block already taken in by the input controller 61 is written into the data buffer 66, and the data read signal is turned on / off, so that the data block is written in word units. Are sequentially written to the data buffer 66 via the input controller 61, and this writing operation is repeated until the data input enable signal becomes negative.

The input controller 61 repeats the above operation every time a new data block is input. For example, after the data input for Queue2 described above, for Queue0, Queue2, Queue3, Q
Assuming that data blocks for ueue0 are sequentially input, element blocks 12 to 15 are used. As a result, the respective values are set in the register 504 for comparison value A and the register 505 for comparison value B of the first to fifth element blocks 11 to 15 as shown in FIG. .

Next, the operation on the output side will be described. First, the element blocks 11, 12,... 132 are in the last state of the above-described operation description, that is, the first to fifth states.
It is assumed that the element blocks 11 to 15 are in use and the numerical values as shown in FIG. 6 are held. The output controller 63 sets the output side block selection signal as a broadcast state, and sends out a conditional output command for outputting a queue with a priority order of “<110”. This command is input to the command analyzer 501 of each of the element blocks 11, 12,... 132 via the control adjuster 62, and as a result, the command has five block IDs shown in FIG. Only the first to fifth element blocks 11 to 15 are provided. Therefore, the first to fifth element blocks 1
From 1 to 15, a block ID, a comparative numerical value A and a comparative numerical value B are output, respectively, while nothing is output from the other element blocks 16 to 132.

As described above, in the element blocks 16 to 132 in a state where nothing is output, the output ports of the comparison value A register 504 and the comparison value B register 505 are: All bits are "1". The block ID selector 3 is:
As described above, the minimum value of the comparative numerical value A (in other words, the priority of the queue is the highest priority) is selected. At this time, the minimum value is “000” and the block ID is They are "1" and "4" (see FIG. 6). Since there are a plurality of minimum values, the block ID selector 3 compares the comparison value B. The comparison numerical value B from the element block 12 having the block ID “1” is “000000”, and the block ID is “4”.
The comparison value B from the element block 15 of “00” is “00”.
0001 ”(see FIG. 6), the comparative numerical value B =“ 0 ”
“00000” is determined to be the highest priority. Therefore, the block ID selector 3 outputs block ID = 1.

When the block ID = 1 is input, the output controller 63 determines the initial value of the read address of the data buffer 66 based on the block ID, similarly to the input controller 61, and By outputting to the output address generator 65 as a value, the initial value of the address is set in the output address generator 65. The basic operation of the output address generator 65 is the same as that of the input address generator 64 described above. Therefore, when the address set as the initial value is output from the output address generator 65 to the data buffer 66, the data at that address is read from the data buffer 66 to the output controller 63. Each time the address counting signal from the output controller 63 is turned on / off,
The address value of the output address generator 65 is counted up, the value is output to the data buffer 66, and the data of the input address is sequentially read from the data buffer 66 to the output controller 63 word by word. Becomes

The output controller 63 that has read the data from the data buffer 66 activates the data output enable signal and transfers the signal to an external device (not shown) connected to the output controller 63. Signal that the data to be prepared is ready. On the other hand, the external device activates an output data read signal for notifying the output controller 63 that data can be read each time data is read. , Data is sent out on the output data bus 6 one word at a time. Then, when all the data of the corresponding data block has been transmitted, the output controller 63 sets the data output enable signal to negative.

As described above, when the data output for one Queue (Queue 0 in this case) is completed, finally, the output controller 63 outputs a comparative numerical value write request command, and “110” indicates the block ID. = 1 in the comparison numerical value A register 504 of the element block 12. By this processing, the block ID
The element block 12 of = 1 is removed from Queue 0 and has been input to the Idle Queue. Then, the output controller 63 sets the output-side block selection signal to the broadcast state, searches for the next highest priority block ID, and repeats the same operation as described above to output the corresponding data. In this way, data output is repeated in order from the highest priority.

In the above-described second embodiment,
Each component is assumed to be realized by so-called hardware, but is not limited to such a configuration. For example, a so-called CPU or DSP
It goes without saying that the configuration may be realized by executing software that performs the above-described operation using. For example, the input controller 61, the control adjuster 62, the output controller 63, and the like may be realized by executing software by a CPU or a DSP.

Next, a third embodiment will be described with reference to FIG. 1 and FIGS. In the third embodiment, an element block having another structure which can be used in the structure shown in FIG. 1 instead of the element block shown in FIG. 2 is shown. . The same components as those shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. Hereinafter, different points will be mainly described. In the following description, the element block shown in FIG.
In this embodiment, the element block will be referred to as "element block 100a" for convenience. The element block 100a in this embodiment is a comparative numerical value C register as a third register for realizing third storage means for storing a predetermined numerical value (“Comp.
Value Reg. C ”510 and a driver 509 for a comparative numerical value C are newly provided. The element block 100a has a configuration suitable for a case where there is such an input, assuming that there is a type in the queue and data indicating the type of the queue is input from the outside. is there.

That is, in the third embodiment, first,
When the comparison numerical value write request command is inputted, at the same time, the second data which is one of the additional information of the data is placed on the data bus 6.
"Queue type" is sent as the identification value of the comparison value C register 510.
Is written to. This “queue type” is, for example, A
An output port of a TM exchange or a switching hub can be positioned. That is, in an ATM switch or a switching hub, a queue may be created for each output port to be transmitted, and this queue may have a plurality of priorities for each output port. Can be used as an identifier indicating a queue category in such a case.

The element block 100a in the third embodiment is suitable for a queuing device having a configuration shown in FIG. 10 described later. In this case, the counter module 2a (see FIG. Each queue type has a counter for counting the "queue priority". Then, when the comparison numerical value write request command is input, as in the first embodiment, the counter module 2a sends the value of the counter corresponding to the "priority of the queue" on the data bus 6 as the counter value. After that, the counter module 2a counts up this counter. Therefore, in this case, the counter module 2a has the same number of counters as the product of "queue type" and "queue priority". Here, the fact that the number of bits of each counter depends on the total number of element blocks 100a is the same as described in the first embodiment.
Is 2 to the power of n, the counter needs (n + 1) bits for the same reason as described in the first embodiment.

Further, in the third embodiment, the first
It is assumed that an “output function stop command” as a fourth command and an “output function activation command” as a fifth command are used in addition to the commands described in the embodiments. The “output function stop command” is a command for stopping the output function of an element block assigned to a queue corresponding to a predetermined “queue type”. In the “output function stop command”, it is assumed that the “queue type” is simultaneously transmitted on the data bus 6 with a predetermined code. When the output function stop command is input, the command analyzer 501A reads the value of the register for comparison value C 510, compares the value with the value indicating the “queue type” sent on the data bus 6, and determines whether the values match. Then, the state transits to the output function suspension state (details will be described later).

On the other hand, the "output function activation command" is a command for activating the output function of an element block assigned to a queue corresponding to a predetermined "queue type" from a stopped state. is there. Even when this command is input, the "queue type" is simultaneously transmitted on the data bus 6 with a predetermined code. When the output function activation command is input while the element block 100a is in the output stop state, the command analyzer 5
01A reads the value of the comparison value C register 510 (hereinafter, the value stored in the comparison value C register 510 is referred to as “comparison value C”), and reads the “queue” sent on the data bus 6. The output function is changed from the stopped state to the activated state when the values match with each other (the details will be described later). That is, this command serves to temporarily dequeue certain types of queues.

Next, the operation of the element block 100a having such a configuration will be described. When a block selection signal is sent out onto the block selection bus 4, the information is decoded by an address decoder 502, and when it matches a block ID preset in the element block 100a, the my address signal is activated. This is the same as in the first embodiment. Also, the address decoder 502 activates the my address signal when the block selection signal is set to the broadcast state, similarly to the first embodiment.

The command analyzer 501A analyzes a command input via the command bus 5 when the my address signal becomes active, similarly to the first embodiment. When a command to request writing of a comparative numerical value is input to the command analyzer 501A, the command analyzer 50A
1A activates the write signal, and compares the “queue priority” on the data bus 6 with the comparison value A register 5
04, the counter value sent on the counter value bus 7 is written in the register 505 for comparison value B, and furthermore, a predetermined value indicating the "type of queue" sent on the data bus 6 Is written to the comparison value C register 510.

When the total output command is input, the command analyzer 501A activates the output enable signal, and outputs the block ID from the block ID driver 506 and the comparative numerical value A from the comparative numerical value A driver 507.
, And the comparison value B is output from the comparison value B driver 508 and the comparison value C is output from the comparison value C driver 509. When the element block 100a does not output anything, all bits of the output ports of the driver 507 for comparison value A, the driver 508 for comparison value B, and the driver 509 for comparison value C are set to "1". It is.

Further, when the conditional output command is input, the command analyzer 501A reads the value on the data bus 6 and the values of the comparison value A register 504 and the comparison value C register 510 and compares them. When the condition is satisfied, the output enable signal is activated, the block ID is output from the block ID driver 506, and the comparison value A is output from the comparison value A driver 507.
The comparison value B is output from the comparison value B driver 508, and the comparison value C is output from the comparison value C driver 509.

Next, the above-described element block 100a
A configuration example of the block ID selector sub-module corresponding to the above configuration will be described with reference to FIG. 8 and FIG. In addition,
For the same components as those shown in FIG.
The same reference numerals are given and the detailed description is omitted, and different points will be mainly described below. In the following description, the block ID selector submodule shown in FIGS. 8 and 9 will be referred to as “block ID selector submodule 300a” for convenience. This block ID selector sub-module 300a is provided with a comparator C corresponding to the configuration shown in FIG.
(Indicated as "Comparator C" in FIG. 8) 44 is newly added.

That is, the comparator C44 receives two comparison values C, and outputs the comparison result as a select C signal (denoted as "Select C" in FIG. 8). Is what it is. Then, based on the select A signal, the select B signal, and the select C signal, the selector 43b receives the block ID, the comparative numerical value A, the comparative numerical value B, and the comparative numerical value C, each of which is input two by two.
Is selected and output. Although the configuration of the block ID selector using the block ID selector sub-module 300a having such a configuration is not particularly shown, the block ID selector sub-module 300a having the above-described configuration is shown in FIG. Basically, the connection is made hierarchically in the same manner as in the previous embodiment shown in FIG.

Next, the operation of the block ID selector sub-module 300a in the above configuration will be described.
The comparison of the comparative numerical value A and the comparative numerical value B is exactly the same as the case of the embodiment shown in FIGS. That is, when two comparison values A are the same,
Which of the priorities is higher is determined by the values of the two comparison values B. In this embodiment, the comparative numerical value C
Exists. The comparison value C is handled as follows. For example, in some applications, "queue type" may have a priority. That is,
For example, this is a case where there is a priority for each output port when the "queue type" is associated with the output port. In such a case, the selector 43b first selects the higher priority by the select A signal, and if the comparison numerical value A is the same, the selector C selects the higher priority "queue type" by the select C signal. Select
Further, when the comparison value C is the same, the older block ID in the queue may be selected by the select B signal.

In another application, there is a case where the "queue type" must be treated exactly the same without giving a priority. For example, "queue type"
And the output port correspond to each other, and the output port is equivalent. In this case, a chance must be given to each output port to transmit data evenly. To achieve this, two comparative values C
(a) and C (b) may be selected with the same probability.

A more specific embodiment of the comparator C44 for realizing this is shown in FIG. 9, and this embodiment will be described below with reference to FIG. This comparator C44
Comprises a random number generator 46, first and second exclusive OR elements 48a and 48b, and a comparator 47. The random number generator 46 always generates a new random number, and the bit width of the random number is the same as the comparative value C. Then, the output is supplied to the first and second exclusive OR elements 48a and 48a.
8b. A comparison value C (a) and a comparison value C (b) are input to the first and second exclusive OR elements 48a and 48b, respectively, and a so-called exclusive OR operation with the value from the random number generator 46 is performed. Is performed, and the result is input to the comparator 47. Then, the comparator 47 selects the larger one of the input two exclusive OR operation results,
A signal indicating the selection result is output as a select C signal. With such a configuration, the comparative numerical value C (a) and the comparative numerical value C (b) are selected with the same probability.

Similar results can be obtained by alternately selecting the comparison value C (a) and the comparison value C (b) instead of the above-described configuration. Furthermore, a random number is used in the same manner as in the above-described embodiment. When the random number is an odd number, a comparative value C (a) is selected, and when the random number is an even number, a comparative value C (b) is selected. It may be configured.
In such a configuration, the operation of the selector 43b is basically the same as that described above. That is,
The selector 43b selects the higher priority according to the select A signal, and if the comparison numerical value A is the same, selects the one in which the comparison numerical value C indicates the "queue type" having the higher priority. Further, if the comparison value C is the same, the one whose comparison value B indicates the older block ID in the queue is selected. In the third embodiment, the command analyzer 501A implements the write control unit, the output control unit, and the determination output unit in claim 11 and the forced output prohibition unit in claim 12. It has become.

Next, as a fourth embodiment, a queuing device using the above-described element block 100a will be described with reference to FIGS. The same components as those in the configuration example shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted. Hereinafter, different points will be mainly described. The basic configuration of this queuing device is the same as that shown in FIG. 5 except that a plurality of output ports are provided. That is, the output controller 63a in this embodiment
Has four output ports P0 to P3. At the output ports P0, P1, P2, and P3, a data output enable signal (in FIG. 10, the description of the output port is described as "Out Data Abailable"), and an output data read signal (in FIG. 10, the description of the output port) Followed by “Out Data Read”), enable signal (in FIG. 10, notation of “Enable” after notation of output port) and data (in FIG. 10, after output port notation, “Dat”)
a Out ”) is output or input.

Here, the enable signal is a signal newly introduced in the fourth embodiment, which is inputted from an external device (not shown).
In other words, it is activated when the external device can transmit the data block to the output controller 63a. On the contrary, the external device receives the transmission of the data block from the output controller 63a. If it is not possible, it will be regarded as negative. The state in which a data block cannot be transmitted refers to a case where congestion or the like occurs at the end of the port and a situation in which it is desired to temporarily reduce traffic. Conventional so-called FI
In the FO, for example, when a data block for the output port P0 is input from the input port, the output port P0 is temporarily in a state where transmission is impossible, and then when a data block for the output port P1 is input from the input port, the output is performed. Even if the port P1 can be transmitted, there is a disadvantage that the data block for the output port P1 cannot be transmitted because the data block for the output port P0 is at the front, but in the case of the fourth embodiment, By using such an enable signal and temporarily removing predetermined data from the queue as described later, the inconvenience of the conventional device can be solved.

Hereinafter, a specific description will be given. First, it is assumed that the numbers of the output ports P0 to P3 are assigned in advance to "queue types". Therefore, the register 510 for the comparison value C of the element blocks 11a, 12a,. Here, the output port number is the output port P0
Is "00", the output port P1 is "01", the output port P2 is "10", and the output port P3 is "11". The “priority of the queue” is assumed to be the same as the concept of the queuing device described earlier with reference to FIG. Furthermore, no priority is given to the "queue type".

When data is input, the input controller 61a determines the output port number (ie, "queue type") and "queue priority" from the contents of the header of the data block header. . Here, each of the element blocks 11a, 12a,... 132a is set to the state of the Idle Queue in the initial state, and the block IDs are “0”, “0”, If "1"... "31" are set, the block ID = 0 is read into the input controller 61a, so that the first element block 11a is
The command is taken out of the Idle Queue, and a comparison numerical value write command is input from the input controller 61a. As a result, the output port number is written in the comparison value C register 510 of the first element block 11a, and the “queue priority” is set in the comparison value A register 504 in the comparison value B register. In 505, the counter value from the counter module 2a is written. Then, the input data block is written in a predetermined address area of the data buffer 66 corresponding to the block ID of the block element 11a. Less than,
Each time data is input, numerical values are sequentially input to the second element block 12a and thereafter in the same manner as described above, and data is accumulated in the corresponding area of the data buffer 66. .

Here, assuming that the data block is data of Queue 1 for output port P 0 and data of Queue 0 for output port P 1, as shown in FIG.
It is assumed that data of Queue0 is sequentially input to the output port P0, data of Queue1 is output to the output port P0, and data of Queue0 is output to the output port P0.
In this state, the highest priority is given to the element block 12a with the block ID = 1 and the block I
This is the element block 13a of D = 2. In this state, the output controller 63a determines that the priority of the queue <“110”
Is output, as a result, either block ID = 1 or block ID = 2 is selected and output. Which is output depends on the operation timing at that time.
In this embodiment, first, assuming that the element block 13a having the block ID = 2 is selected as a result, the output controller 63a operates the output address generator 65 to read the corresponding data from the data buffer 66 and It is determined that the data is for the output port P0 based on the comparison value C input from the block ID selector 3. The output controller 63a outputs the output port P0.
Determine whether the enable signal is active,
When it is determined that the enable signal is active, a data block is output in accordance with the so-called on / off of an output data read signal input to the output port P0 from an external device (not shown).

After the data block corresponding to the information of the element block 13a is output, the output controller 63a
Again outputs a conditional output command with queue priority <“110”. As a result, block ID = 1
Is obtained. The element block 12a with the block ID = 1 is for the data block for the output port P1 (see FIG. 11). At this time, if the enable signal at the output port P1 is negative, the data block cannot be transferred to the output port P1. Therefore, the output controller 63a sets the output port P1
Outputs the output function stop command for. as a result,
Until the output function activation command is input, the element block 12a with the block ID = 1 is forced to make the output enable signal negative and is in the output stop state. As a result, the data for the output port P1 becomes Que.
It is in a state temporarily removed from ue0.

After the output controller 63a outputs the output function stop command, the output controller 63a again sets the priority of the queue <“11”.
Output a conditional output command of "0". As a result, the next highest priority block ID = 4 (see FIG. 11) is selected, and the output controller 63a outputs data at the output port P0 in the same manner as in the case of the previous block ID = 2. Will be done. Then, when the enable signal of the output port P1 becomes active, the output controller 63a outputs an output function activation command for the output port P1, and outputs the element block 12a.
Is released from the output stop state. Subsequently, the output controller 63a outputs a conditional output command with the priority of the queue <110, and as a result, the block ID is returned again.
= 1 is obtained, and data is output from the output port P1.

As described above, the function of recognizing the "queue type" and incorporating a function of temporarily stopping the output for each "queue type" are included, so that a predetermined output port can be connected. Temporarily stop the output of the queue, select the highest priority from the other queues sequentially,
Will be able to output.

In the above-described fourth embodiment,
Each component is assumed to be realized by so-called hardware, but is not limited to such a configuration. For example, a so-called CPU or DSP
It goes without saying that the configuration may be realized by executing software that performs the above-described operation using. For example, the input controller 61a, the control adjuster 62, the output controller 63a, etc.
May be realized by executing software.

Next, as a fifth embodiment, another configuration example of the element block will be described with reference to FIG. The same components as those shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. Hereinafter, different points will be mainly described. In the following description, the element block having the configuration shown in FIG.
b "for convenience. In this embodiment, a timer for adjusting the output timing (“Tim
2 is different from the configuration example shown in FIG. 2 in that a configuration is newly provided.

First, in the case of this embodiment, when a comparative numerical value write request command is input, the data bus 6
It is assumed that the "queue priority" and the timer value are sent at the same time. In the case of the configuration example described above with reference to FIG. 2, when an output command is input after writing of the comparison values A and B, the element block 100 sends the comparison value. However, in the element block 100b according to the fifth embodiment, the output is stopped by the timer 512 until a predetermined time elapses as described below.

That is, the comparison values A and B are stored in the comparison value A register 504 and the comparison value B register 50, respectively.
5 is written by the command analyzer 501B.
A timer time write signal (denoted as “WR TIM” in FIG. 12) is activated for the timer 512, and the timer value sent to the data bus 6 by the comparison numerical value write request command is set in the timer 512. . And timer 5
At the same time, the command analyzer 501B sets the output enable signal to negative, and the element block 100b enters the output stop state. When the timer 512 finishes counting the time of the previously set timer value and the timer value becomes zero, the timer 512 outputs a command to the command analyzer 501B.
To the end signal (denoted as “EXP” in FIG. 12)
Is activated, and as a result, the command analyzer 501
B activates the output enable signal,
The element block 100b is set to an output activated state.

The significance of adding such a function is as follows.
That is, the time that can be output can be delayed by the time specified by the timer value. This function can be used for a so-called traffic shaper. A traffic shaper is a device that shapes desired traffic. For example, in an ATM or the like, a certain physical line is used by a plurality of virtual connections. In this case, traffic is managed for each virtual connection,
It also shapes traffic as needed.

For example, when one data block is transmitted per second and when five data blocks are transmitted continuously every five seconds, the data transfer rate is determined when both are compared in a relatively long time span. Are substantially the same,
Comparing the two in a very short time span, it can be said that a lot of traffic is flowing at one time when five data blocks are sent in succession. Switches and switches often require a function of retransmitting a set of so-called bursty data blocks at predetermined intervals. Element block 1 described above
00b is suitable for realizing this function. That is, when the comparison value write request command is output, the timer 5
If the timer value is written so that the absolute time at which the time count value of 12 becomes zero occurs at regular intervals, it becomes possible to transmit burst-like input data blocks at regular intervals.

Next, as a sixth embodiment, the fifth embodiment will be described.
Another configuration example of the element block 100b having a timer function for adjusting the output timing as in the embodiment of the present invention will be described with reference to FIG. Please note that
The same components as those shown in FIG. 2 or FIG. 12 are denoted by the same reference numerals, and detailed description thereof will be omitted. Hereinafter, different points will be mainly described. In the following description, the element block having the configuration shown in FIG.
For convenience. This sixth embodiment is different from the configuration example shown in FIG. 12 in that a comparative value D register 513 is provided instead of the timer 512 shown in FIG. That is, in this embodiment, an absolute time is transmitted on the data bus 6 in response to the comparison value write request command on the data bus 6 in place of the timer value in the fifth embodiment. 513.

On the other hand, the command analyzer 501B is a publicly-known command analyzer.
The real time can be recognized using a known means, and the value of the register 513 for comparison value D can be compared with the current time. Then, the command analyzer 501B stores the current time in the register 5 for the comparison numerical value D.
Until the time at which the data is written to No. 13, the output enable signal is set to be negative and each comparison value (comparison value A, B, C)
Is stopped, and when it is determined that the value of the comparison value D register 513 matches the actual time, the output enable signal is activated and each comparison value can be transmitted.

In any of the above-described embodiments,
Which element block 100 (see FIG. 2), 100
a (see FIG. 7), 100b (see FIG. 12), 100c
(See FIG. 13) also has an address decoder 502, and when a block selection signal is input, it is determined whether or not it matches a preset block ID and whether or not it is in a so-called broadcast state. Is done,
Although a predetermined element block specified by the block selection signal is selected, such a configuration is not necessarily required. That is, for example, in the example shown in FIGS. 1 and 2, the element block 11
A dedicated wiring for transmitting a signal for selecting each element block is provided according to the number of .about.1n, and is connected to the command analyzer 501. Then, a signal of a predetermined level is applied to the wiring connected to the command analyzer 501 of the element block desired to be selected. If the command analyzer 501 detects the predetermined level, the element block is selected. It may be recognized that there is. With such a configuration, the address decoder 502 can be eliminated. The configuration for selecting an element block is not limited to the configuration described above, and may be variously configured by a known / known technology as a technology for selecting a desired element from a plurality of elements. is there.

Finally, in each of the above-described embodiments, a command to write a comparative numerical value,
Commands such as a total output command, a conditional output command, an output function stop command, and an output function activation command are defined, and various examples have been given in which these commands are transferred on a command bus and sent to each element block. , This is only one form and need not be limited to using such commands. That is, for example, a completely similar function is realized by a configuration in which signals such as a comparison numerical value write request signal, a total output signal, a conditional output signal, an output function stop signal, and an output function activation signal are directly input to the element block. Is what you can do.

[0103]

As described above, according to the present invention,
A first identification value, which is one of information added to the data,
A counter value indicating the oldness of the input is managed for each block identification number, so that unlike the related art, the number of storage means corresponding to the maximum value that the first identification value can take, Since there is no need for storage elements, a queuing device that can process a large amount of data with a relatively simple configuration does not depend on the number of lines and ports, the number of virtual connections and virtual paths, etc. Can be provided. Also, by configuring the highest priority selection means to select the first identification value as the first identification value,
It is possible to provide a queuing device that guarantees the order of cells and packets. Further, in particular, in the inventions according to claims 6 to 13, in addition to the above effects, the second aspect
Since the second identification value is used for identification of an output port, for example, if the second identification value is used for identification of an output port, the second identification value may be used for the external device depending on the operation state of the external device connected to the output port. It is possible to temporarily remove data from the queue, and it is possible to perform efficient data processing with a simple configuration and provide a queue device with good economy.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a configuration example of a queuing device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration example of an element block used in the queuing device shown in FIG. 1;

FIG. 3 is a configuration diagram showing a configuration example of a block ID selector used in the queuing device shown in FIG. 1;

FIG. 4 is a configuration diagram showing a configuration example of a block ID selector submodule used for the block ID selector shown in FIG. 3;

FIG. 5 is a configuration diagram illustrating a configuration example of a queuing device according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram for explaining changes in respective values of a block ID, a register for a comparison value A, and a register for a comparison value B in an operation example of the queuing device shown in FIG. 5;

FIG. 7 is a configuration diagram illustrating a configuration example of an element block according to a third embodiment of the present invention.

8 is a configuration diagram showing a configuration example of a block ID selector sub-module used for the element block shown in FIG. 7;

9 is a configuration diagram illustrating a configuration example of a comparator C illustrated in FIG. 8;

FIG. 10 is a configuration diagram illustrating a configuration example of a queuing device according to a fourth embodiment of the present invention.

11 shows a block ID, a register for a comparative value A, and a comparative value B in the operation example of the queuing device shown in FIG.
FIG. 6 is an explanatory diagram for explaining changes in respective values of a register for comparison and a register for comparison numerical value C.

FIG. 12 is a configuration diagram showing a configuration example of an element block according to a fifth embodiment of the present invention.

FIG. 13 is a configuration diagram illustrating a configuration example of an element block according to a sixth embodiment of the present invention.

FIG. 14 is a configuration diagram showing one configuration example of a conventional queuing device.

FIG. 15 is a configuration diagram showing another configuration example of a conventional queuing device.

[Explanation of symbols]

 2 ... Counter module (first embodiment) 2a ... Counter module (fourth embodiment) 3 ... Block ID selector (first embodiment) 3a ... Block ID selector (fourth embodiment) 61 ... Input control Unit (first embodiment) 61a Input controller (fourth embodiment) 63 Output controller (first embodiment) 63a Output controller (fourth embodiment) 64 Input address generation Device 65: Output address generator 66: Data buffer 501: Command analyzer (first embodiment) 501A: Command analyzer (third embodiment) 502: Address decoder 503: Block ID register 504: Comparative numerical value A Register 505: Register for comparison value B 510: Register for comparison value C 513: Register for comparison value D

Claims (18)

[Claims] 1. A counter having a number corresponding to the maximum possible value of a first identification value input together with a first command from the outside, and when the first command is input, the first counter Counting means for outputting the value of the counter corresponding to the first identification value input together with the command as a counter value and incrementing the counter value of the counter by one, and a storage area for each of a plurality of preset block identification numbers A first identification value input together with a command from outside,
The counter value from the counting means is stored in a storage area designated by a predetermined block identification number according to the command, while the block identification number, the first identification value, and the counter are stored according to the command. Identification information storage means for outputting a value; and a plurality of block identification numbers, a first identification value, and a counter value input from the identification information storage means, wherein the first identification value has a highest priority. If the number having the given value is selected and the number of the first identification values indicating the highest priority is one, the block identification number and the counter value are output together with the first identification value, and the selected value is selected. If there are a plurality of first identification values, a counter value indicating a predetermined highest priority value is selected from among them, and the block identification number and the first identification value are set together with the counter value. Highest priority selection to output Means for storing, when a first command is input, a first identification value and a counter in a storage area corresponding to a block identification number externally input together with the first command. When the second command is inputted, the first discriminating value and the counter value of the storage area corresponding to all the block discriminating numbers are output together with the corresponding block discriminating numbers, and the third command is inputted. In this case, the magnitude relationship between each of the first identification values stored in the storage area and the first identification value input together with the third command is a magnitude relationship defined by the third command. A queuing device for selecting a first identification value stored in the storage area and outputting a block identification number and a counter value together with the first identification value. 2. The identification information storage means, wherein a storage area is composed of a plurality of element blocks to which a block identification number is previously assigned, wherein the element blocks are written and stored with a first identification value from outside. A first storage unit, a second storage unit in which a counter value is written and stored from the outside, a block identification number storage unit in which a predetermined block identification number is stored, To the first storage means.
Write control means for writing the discrimination value of the counter value to the second storage means path, and the first and second storage means and the block identification number storage means based on an external command. Output control means for outputting the value held in each of them; and comparing a value input from the outside with a value held in the first storage means based on a command from the outside, and satisfying a predetermined comparison condition. The value of the corresponding first storage means is stored in the second storage unit.
2. The queuing device according to claim 1, further comprising: a judgment output unit for outputting the data together with the values held in the storage unit and the block identification number storage unit. 3. The identification information storage means has a storage area composed of a plurality of element blocks to which a block identification number is assigned in advance, wherein the element blocks are written and stored with a first identification value from outside. A first register, a second register in which a counter value is externally written and stored, a block ID register in which a predetermined block identification number is held, and a second register in accordance with a command input from outside. A command analyzer for controlling the first and second registers and the block ID register, wherein the command analyzer receives a first command and outputs a block identification number designated from the outside. If they match, the first identification value externally input to the first register is externally input to the second register. Counter values are written, and when a second command is input and the block identification numbers specified from the outside match, the values are held in the first and second registers and the block ID register, respectively. If the third command is input and the block identification number specified from the outside matches, the first identification value input together with the third command and the first identification value are output. The register value of 1 is
It is determined whether or not the magnitude relation defined by the third command is satisfied. If it is determined that the magnitude relation is satisfied, the values held in the first and second registers and the block ID register are output. The queuing device according to claim 1, wherein the queuing device is configured as described above. 4. The element block has a timer for counting a time corresponding to a timer value input from the outside, and the timer is configured to generate a timer value in response to a timer time write signal output by a command analyzer. While the time counting is started simultaneously with the setting of the above, when the time counting corresponding to the set timer value is performed, an end signal is output to the command analyzer, and the command analyzer writes the timer time. The first register, the second register and the block ID together with the output of the signal
While the output of the value held in each register to the outside is inhibited, the end signal is input from the timer, and at the same time, the first register, the second register, and the block I
4. The queuing device according to claim 3, wherein the values held in the D registers can be output to the outside. 5. Data for writing and storing externally input data in accordance with an externally input write address signal and outputting stored data in accordance with an externally input read address signal. A memory means for determining and outputting an initial address value when writing data to the data storage means based on an externally input address initial value; Input address generating means for advancing the address value by one each time the data is read, and an initial address value for reading data from the data storage means based on an externally input address initial value. In addition to determining and outputting, each time the externally input address count signal is brought into a predetermined state, the address value is advanced by one and output. A block identification number, a command and data additional information to the element block based on the externally input command, data and additional information of the data and the block identification number from the highest priority selection means. On the other hand, based on the block identification number from the highest priority selecting means, an address initial value for the input address generating means is determined and output,
An input control means for outputting an address count signal to the input address generation means in accordance with an input state of data from the outside, and further outputting externally input data to the data storage means; Based on the block identification number from the selection means, determine and output an address initial value for the output address generation means, while reading data output from the data storage means, from the destination of the data, An output control means for outputting, when an output data read signal indicating that data is ready to be read in a predetermined state, outputs the data. Claim 2,
The queuing device according to claim 3. 6. A counter having a number corresponding to a product of the maximum number of possible values of a first identification value and a second identification value input together with a first command from the outside, Is output as a counter value corresponding to the first identification value and the second identification value input together with the first instruction, and the counter of the counter is input. A counting means for advancing the value by one; a first identification value and a second identification value having a storage area for each of a plurality of block identification numbers set in advance and input together with an instruction from outside; And the counter value of
In response to the command, the information is stored in a storage area designated by a predetermined block identification number, and the block identification number, the first identification value, the second identification value, and the counter value are output in response to the command. An identification information storage unit, a first identification value, a second identification value from a plurality of block identification numbers, a first identification value, a second identification value, and a counter value input from the identification information storage unit. And a highest priority selecting means for selecting the highest priority based on the counter value and outputting a block identification number, a first identification value, a second identification value, and a counter value of the identification information. When the first command is input, the storage means stores the first identification value, the second identification value, and the counter value in a storage area corresponding to the block identification number externally input together with the first command. And the second command is input In the case, the first identification value, the second identification value, and the counter value of the storage area corresponding to all the block identification numbers are output together with the corresponding block identification numbers, and when a third command is input, the storage area is output. The magnitude relationship between each of the first identification values stored in the storage unit and the first identification value input together with the third command is stored in the storage area corresponding to the magnitude relationship defined by the third command. A queuing device that selects the first identification value thus output and outputs a second identification value, a block identification number, and a counter value together with the first identification value. 7. A high-priority selection means, comprising: a plurality of block identification numbers input from the identification information storage means; a first identification value;
From the second identification value and the counter value, the one in which the first identification value has a predetermined value indicating the highest priority is selected, and the number of the first identification values indicating the highest priority is one. In some cases, the second identification value, the block identification number, and the counter value are output together with the first identification value, while the selected first identification value is output.
In the case where there are a plurality of identification values, the one in which the second identification value has the value indicating the highest priority is selected, and when the selected second identification value is one, Outputs the first identification value, the block identification number, and the counter value together with the second identification value. If there are a plurality of the selected second identification values, the counter value Select the one that indicates the old input, its first identification value,
7. The queuing device according to claim 6, wherein a second identification value, a counter value, and a block identification number are output. 8. The highest priority selecting means includes a plurality of block identification numbers input from the identification information storage means, a first identification value,
From the second identification value and the counter value, the one in which the first identification value has a predetermined value indicating the highest priority is selected, and the number of the first identification values indicating the highest priority is one. In some cases, the second identification value, the block identification number, and the counter value are output together with the first identification value, while the selected first identification value is output.
When there are a plurality of identification values, the first and second identification values, the second identification value, the block identification number, and the counter value are selected at random, and each time they are selected, 7. The queuing device of claim 6, wherein: 9. The identification information storage means has a storage area composed of a plurality of element blocks to which a block identification number has been previously assigned, wherein the element block has a first identification value written and stored from outside. A first storage unit, a second storage unit in which a counter value is written and stored from the outside, a third storage unit in which a second identification value is written and stored from the outside, A block identification number storage unit for storing the block identification number, and a first storage unit based on an external command.
Writing control means for writing a counter value to the second storage means path and a second identification value to the third storage means, respectively; and Output control means for outputting the values held respectively from the third storage means and the block identification number storage means, and the values input from the outside and stored in the first storage means based on an external command. And compares the value of the first storage unit corresponding to a predetermined comparison condition with the value of the second storage unit.
9. A judgment output means for outputting together with a value stored in each of the third storage means and the block identification number storage means, and a judgment output means. Queuing device. 10. In accordance with an external command, output of a value held in each of the first to third storage means and the block identification number storage means by the output control means is inhibited for a predetermined period, and the judgment output means is inhibited. 10. The queuing device according to claim 9, further comprising a forced output prohibiting unit for prohibiting the output of the values held in the first to third storage units and the block identification number storage unit for a predetermined period. 11. An identification information storage means, wherein a storage area is composed of a plurality of element blocks to which a block identification number has been previously assigned, wherein the element block has a first identification value written from outside and stored. A first register, a second register in which a counter value is written and stored from outside, a third register in which a second identification value is written and stored from outside, and a predetermined block identification. A block ID register that holds a number, and a command analyzer that controls the first to third registers and the block ID register according to a command input from the outside. When the first command is input and the block identification numbers specified from the outside match, the external input to the first register is performed. The first identification value obtained is added to the counter value externally input to the second register, and the second identification value externally input to the third register is written. When the command of No. 2 is input and the block identification numbers specified from the outside match, the values held in the first to third registers and the block ID register are output, and When the instruction of No. 3 is input and the block identification numbers specified from the outside match, the first identification value input together with the third instruction and the value of the first register are:
It is determined whether or not the magnitude relation defined by the third command is satisfied. If it is determined that the magnitude relation is satisfied, the values held in the first to third registers and the block ID register are output. 9. The queuing device according to claim 6, wherein the queuing device is configured as described above. 12. When the fourth command is input, the command analyzer determines the value of the value held in each of the first and second registers and the block ID register until the fifth command is input. 2. The output is prohibited.
The queuing device of claim 1. 13. An externally input data is written according to an externally input write address signal,
Data storage means for outputting stored data in accordance with an externally input read address signal; and writing data to the data storage means based on an externally input address initial value. Input address generating means for determining and outputting an initial value of an address, and advancing an address value by one each time an externally input address count signal is brought into a predetermined state; The address initial value is determined and output at the time of reading data from the data storage means based on the address initial value to be read out from the data storage means. An output address generation means for advancing the value by one, and an externally input command, data, additional information of the data, and Based on the lock identification number, the block identification number, the command and the additional information of the data are output to the element block. Determine the value and output it,
An input control means for outputting an address count signal to the input address generation means in accordance with an input state of data from the outside, and further outputting externally input data to the data storage means; When it is determined that an external device connected to the plurality of output ports has an output port and that an enable signal corresponding to a state in which the external device cannot capture data is input in a predetermined state. While prohibiting output to the output port, from the external device, when it is determined that an enable signal corresponding to a state in which the external device is capable of capturing data is input in a predetermined state, On the basis of the block identification number from the highest priority selection means, an address initial value for the output address generation means is determined and output, Output control means for reading data output from the data storage means and outputting the data from an output port determined based on a second identification value from the highest priority selection means. Claim 6, Claim 7,
The queuing device according to claim 8, claim 9, claim 10, claim 11, or claim 12. 14. A magnitude relationship between a first identification value defined by a third instruction and input together with the third instruction and a plurality of first identification values stored in the identification information storage means. 2. The method according to claim 1, wherein the first identification value input together with the third command is equal to a plurality of first identification values stored in the identification information storage means. , Claim 2, Claim 3, Claim 4, Claim 5, Claim 6, Claim 7, Claim 8, Claim 9, Claim 10, Claim 11, Claim 12, or Claim 13. Queuing device. 15. A magnitude relation between a first identification value defined together with the third command and input to the third command and a plurality of first identification values stored in the identification information storage means. Wherein the plurality of first identification values stored in the identification information storage means are larger than the first identification value input together with the third command. Claim 2, Claim 3, Claim 4, Claim 5, Claim 6, Claim 7, Claim 8, Claim 9, Claim 10, Claim 11,
The queuing device according to claim 12 or claim 13. 16. A magnitude relation between a first identification value defined together with the third command and input to the third command and a plurality of first identification values stored in the identification information storage means. 2. The method according to claim 1, wherein the plurality of first identification values stored in the identification information storage means are smaller than the first identification value input together with the third command. Claim 2, Claim 3, Claim 4, Claim 5, Claim 6, Claim 7, Claim 8, Claim 9, Claim 10, Claim 11,
The queuing device according to claim 12 or claim 13. 17. The method according to claim 1, wherein the command inputted externally is a command represented by a predetermined digital code corresponding to the contents of the command. Claim 5, Claim 6, Claim 7, Claim 8, Claim 9, Claim 10, Claim 11, Claim 12,
Claim 13, Claim 14, Claim 15, or Claim 16
A queuing device as described. 18. The method according to claim 1, wherein the externally input command is an analog signal corresponding to the content of the command. The queuing device according to claim 7, claim 8, claim 9, claim 9, claim 10, claim 11, claim 12, claim 13, claim 14, claim 15, or claim 16.